- 24 Mar, 2022 1 commit
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Milad Fa authored
P10 comes with prefixed instruction (2 x 4-byte instructions) which allow for using larger immediate values. `paddi` has been added in this CL which uses a 34-bit immediate. Prefixed instructions cannot cross 64-byte boundaries, i.e we cannot have the first 4-bytes on one side and the second 4-bytes emitted on the other side of the boundary. Therefore we need to align generated code to 64 bytes and emit a nop whenever the boundary is being crossed midway (check emit_prefix). Change-Id: I90e9953089214e15eeef0d70147ea5943fe05f45 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3528993Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Farazmand <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/main@{#79612}
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- 18 Nov, 2021 1 commit
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Milad Fa authored
Change-Id: Ie61638fbc61b5a84dc9ba396e4df7193a2ebd6a7 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3291547Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/main@{#77978}
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- 30 Aug, 2021 1 commit
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Milad Fa authored
Port 67113424 Original Commit Message: Like https://chromium-review.googlesource.com/c/v8/v8/+/2994804, but for arm and arm64. R=thakis@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: I4fbc42c48db2c43e55279ab40681c0735106d454 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3129640Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/main@{#76577}
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- 12 Aug, 2021 1 commit
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Milad Fa authored
Change-Id: I89694796962d46b4fb1ae244ee39639576659465 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3092025Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#76273}
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- 11 Aug, 2021 1 commit
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Milad Fa authored
MovFloatToInt and MovIntToFloat have been optimized on Power8 and above to use VSX instructions instead if using the memory. Change-Id: I77af9aa20aa477f8f9e3ec9545445ef777aa0c72 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3087726 Commit-Queue: Milad Fa <mfarazma@redhat.com> Reviewed-by:
Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#76241}
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- 10 Aug, 2021 1 commit
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Milad Fa authored
This Cl optimizes 64bit FP min/max using scalar VSX instructions. FP values are always stored in DP format in a FP register which means 32bit FP min/max ops will also benefit from this change. Change-Id: I181e61b2d28ddf6920b548d33cb4d926da856be8 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3086023 Commit-Queue: Milad Fa <mfarazma@redhat.com> Reviewed-by:
Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#76212}
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- 03 Aug, 2021 1 commit
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Milad Fa authored
I/F 32x4 and 64x2 ReplaceLane opcodes are optimized on P10. Change-Id: I28ddc2b4e66ca39414e9c3ed2efd0eea268f1a07 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3067803Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#76066}
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- 30 Jul, 2021 1 commit
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Junliang Yan authored
Change-Id: Ic1fb152ced8535982f4e918df691e5c6e4cfaa68 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3063506Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#76025}
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- 29 Jul, 2021 1 commit
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Milad Fa authored
mtvsrdd uses 2 gprs as input. Change-Id: I4446a51bda1196ce262e3a90ed7c840da89c9d16 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3061478Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#76009}
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- 27 Jul, 2021 1 commit
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Milad Fa authored
This cl uses the newly added instructions on power10 for extracting the sign bits. Change-Id: I9e4fa3bdd7fa5fc7004695c1d3ac29e3906d5207 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3056506Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#75947}
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- 26 Jul, 2021 1 commit
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Junliang Yan authored
Change-Id: I99448ed94e8ef0cb2ea9fdf6e629757bda595d54 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3054472Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#75930}
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- 22 Jul, 2021 1 commit
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Dan Elphick authored
Removes unnecessary includes of v8.h from src/diagnostics/gdb-jit.h src/diagnostics/system-jit-win.h src/diagnostics/unwinder.h by predeclaring types or using more appropriate headers. Bug: v8:11879 Change-Id: I17f42acfef8e61133988453d67c3c0d473ff0337 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3045702 Auto-Submit: Dan Elphick <delphick@chromium.org> Commit-Queue: Dan Elphick <delphick@chromium.org> Reviewed-by:
Ross McIlroy <rmcilroy@chromium.org> Cr-Commit-Position: refs/heads/master@{#75870}
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- 07 Jul, 2021 1 commit
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Milad Fa authored
A few fixes are applied in this CL: 1- Instructions which use UIM in V8 only use bits 16 to 19 inclusive. 2- get_simd_register is set to return a reference and not a copy. 3- On vector extract and insert instructions, UIM could be used to select specific bytes as starting point which may not reflect a lane. Vector splat uses UIM as a lane selector which remains unchanged in this CL. Change-Id: Ieb43afb977dac11d3ea10a2f265c2823f64457e3 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3011166Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#75618}
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- 22 Jun, 2021 2 commits
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Milad Fa authored
Port 9010201c Original Commit Message: Moves VSNPrintf, SNPrintf and StrNCpy out of utils/utils.h into base/strings.h. R=delphick@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: Ia06003c1daea94e3767083b910bee1498bec37cd Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2979474Reviewed-by:
Dan Elphick <delphick@chromium.org> Commit-Queue: Dan Elphick <delphick@chromium.org> Cr-Commit-Position: refs/heads/master@{#75312}
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Dan Elphick authored
Moves VSNPrintf, SNPrintf and StrNCpy out of utils/utils.h into base/strings.h. Bug: v8:11879 Change-Id: I0e165cb27c42f89c9acd1c6378514b40a90cd18d Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2972732 Auto-Submit: Dan Elphick <delphick@chromium.org> Reviewed-by:
Clemens Backes <clemensb@chromium.org> Reviewed-by:
Ross McIlroy <rmcilroy@chromium.org> Commit-Queue: Dan Elphick <delphick@chromium.org> Cr-Commit-Position: refs/heads/master@{#75308}
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- 18 Jun, 2021 2 commits
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Junliang Yan authored
Change-Id: Ie092921e4a9c1e4a0acee827f73570f3f9617712 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2971557Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#75261}
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Dan Elphick authored
The adding of base:: was mostly prepared using git grep and sed: git grep -l <pattern> | grep -v base/vector.h | \ xargs sed -i 's/\b<pattern>\b/base::<pattern>/ with lots of manual clean-ups due to the resulting v8::internal::base::Vectors. #includes were fixed using: git grep -l "src/utils/vector.h" | \ axargs sed -i 's!src/utils/vector.h!src/base/vector.h!' Bug: v8:11879 Change-Id: I3e6d622987fee4478089c40539724c19735bd625 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2968412Reviewed-by:
Clemens Backes <clemensb@chromium.org> Reviewed-by:
Hannes Payer <hpayer@chromium.org> Commit-Queue: Dan Elphick <delphick@chromium.org> Cr-Commit-Position: refs/heads/master@{#75243}
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- 10 Jun, 2021 1 commit
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Milad Fa authored
We can detect the sequence during instruction selection and if possible emit a single load/store byte reversed opcode instead of doing the same separately (i.e load/store and then reverse). Change-Id: Ib7d0c8c7105382637c33cafac5b5f4e23e8e553d Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2950243Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#75076}
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- 03 Jun, 2021 1 commit
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Milad Fa authored
Change-Id: Ie16a4542179a9661991a4e1696d1b7a952b0e305 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2936605Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#74941}
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- 20 May, 2021 1 commit
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Milad Fa authored
This CL adds vector splat byte, word and halfword to codegen, disassembler and the simulator. It also optimizes a number of Simd opcodes by using the added instructions as well as VSX splat immediate (xxspltib). Change-Id: I2c4eba33e81542f901d7cdc669c50b510e48c4c8 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2909525Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#74701}
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- 13 May, 2021 2 commits
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Milad Fa authored
xxbrq includes a constant value of `31` as part the opcode. This CL includes this constant within constants-ppc instead of adding it while emitting code. Change-Id: I897f5f86165c7b006a829dcb2ee2a0c9dc2ef1b3 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2891935Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#74558}
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Milad Fa authored
vnegw and vnegd are also added to the opcode list as well as the disassembler and the simulator. Change-Id: I852fbe4469b2dd3c3872aa846a0b680e35e1dba6 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2892630Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#74556}
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- 22 Apr, 2021 1 commit
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Milad Fa authored
Using the added lxvx and stxvx instructions, we can load and store vector register values in a single instruction. MRR encoding does not have a 16 byte alignment requirement. Change-Id: I9c1d80fd867a0e79d3390e4a05e08cdf2a2e4835 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2845734Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#74130}
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- 07 Apr, 2021 1 commit
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Milad Fa authored
From PPC ABI: >The condition code register fields CR0, CR1, CR5, CR6, and CR7 are volatile. The condition code register fields CR2, CR3, and CR4 are nonvolatile. We can safely clear Cr field 6 without the need to save its content first. Clearing the entire CR register will cause crashes if it's not restored properly. Change-Id: I854f5631294f56f542b1a6f4e23dd7dbcf000d7d Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2810802Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#73837}
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- 29 Mar, 2021 1 commit
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Milad Fa authored
Change-Id: Id9c82a83dca73aedd3ce98b648fc195aecb00c90 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2791562Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#73714}
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- 16 Mar, 2021 2 commits
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Milad Fa authored
Change-Id: I06633381ad6bfd84090e7553404425d28a90f47a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2765443Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#73450}
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Milad Fa authored
Change-Id: I575dffb8810ccc9e73cae2413c7993e0f4fdbbdd Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2764623 Commit-Queue: Milad Fa <mfarazma@redhat.com> Reviewed-by:
Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#73447}
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- 12 Mar, 2021 1 commit
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Milad Fa authored
Also fixed the disassembler to include 10th bit of instruction. Change-Id: Idc6659a8a9d6a291b68537bae533a32970a4441d Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2757567 Commit-Queue: Milad Fa <mfarazma@redhat.com> Reviewed-by:
Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#73382}
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- 23 Dec, 2020 1 commit
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Milad Fa authored
Instructions include: vupkhsw vupklsh vupkhsh vupklsb vupkhsb Change-Id: Ie11961dbf1f4838e96efe6704c8d938a62213b93 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2601660Reviewed-by:
Junliang Yan <junyan@redhat.com> Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#71872}
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- 22 Dec, 2020 1 commit
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Milad Fa authored
Change-Id: I4e70f176fa08c9a6b6f40683248d4c32c8e16f59 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2598588Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#71865}
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- 17 Dec, 2020 1 commit
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Milad Fa authored
Change-Id: I2fb08d891112f8d88896a116622688ce6ea83a10 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2595312Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#71837}
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- 14 Dec, 2020 2 commits
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Milad Fa authored
Change-Id: I669eaed12f352398b8e34b1f74262f46562745cb Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2591047Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#71745}
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Milad Fa authored
Simd128Registers::names_ is also removed as the stringification will be done by DEFINE_REGISTER_NAMES. PPC FP and Vector Register (VR and VSR) Layou: VR0 is VSR32 and goes all the way to VSR63 which is used by V8 Vector operations. VSR[0]0 - FPR[0] VSR[0]128 | | | VSR[31] - FPR[31] VSR[32] - VR[0] VR[0]128 | | | V VSR[63] - VR[31] Change-Id: Ied2a530b08d1eb40af59ce44f848d638f2a6dc9f Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2587356Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#71735}
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- 11 Dec, 2020 1 commit
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Milad Fa authored
PPC has a set of 64 Vector Registers called VSX. The lower 32 of them are shared with Floating Point register (only 64 bit of the registers are used for FP operations). The upper 32 registers are VR registers which are only used for VMX Vector operations. VSX Vector operations have the option to use the lower 32 or upper 32 registers using the TX bit set on the instructions. VMX operations only use the upper 32 registers. In V8 we always set the VSX TX bit to "1" to make sure all the vector operations take place on the upper 32 registers. Change-Id: Ib3ea03254cbdc9547c3b698fe19c0c6b28138741 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2585260 Commit-Queue: Milad Fa <mfarazma@redhat.com> Reviewed-by:
Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#71722}
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- 30 Nov, 2020 1 commit
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Zhi An Ng authored
Bug: v8:11074 Change-Id: I478f4390523ddf7cfb87dd22cef5ed331be5c875 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2558267Reviewed-by:
Andreas Haas <ahaas@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#71468}
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- 21 Oct, 2020 1 commit
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Milad Fa authored
Port d6c586f7 R=solanes@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: I73098589bc2246e389432be18b11bcf3242df308 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2488021Reviewed-by:
Santiago Aboy Solanes <solanes@chromium.org> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#70681}
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- 29 Jul, 2020 1 commit
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Milad Farazmand authored
lvx and stvx require 16-byte aligned addresses. This CL enables loading and storing to addresses which are not 16-byte aligned. Change-Id: I5635e857a979520822c8b30bb5477a159e97e6e5 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2327648Reviewed-by:
Junliang Yan <jyan@ca.ibm.com> Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com> Cr-Commit-Position: refs/heads/master@{#69135}
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- 28 Jul, 2020 1 commit
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Milad Farazmand authored
Port 51b53dd3 R=rstz@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com BUG= LOG=N Change-Id: Ic2ee6e75afd5da8bb7f35dfde4b1d85231f1cf4a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2318045Reviewed-by:
Andreas Haas <ahaas@chromium.org> Reviewed-by:
Junliang Yan <jyan@ca.ibm.com> Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com> Cr-Commit-Position: refs/heads/master@{#69100}
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- 26 May, 2020 1 commit
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Milad Farazmand authored
Change-Id: Ife10d7c8634cbd6b542dc522a49124f790f51921 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2216434Reviewed-by:
Junliang Yan <jyan@ca.ibm.com> Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com> Cr-Commit-Position: refs/heads/master@{#67992}
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- 15 May, 2020 1 commit
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Milad Farazmand authored
Also modified simd ExtractLane to use the input lane. Change-Id: Icc40226c1f3e001eb588e8c44570399c19582404 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2199643Reviewed-by:
Junliang Yan <jyan@ca.ibm.com> Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com> Cr-Commit-Position: refs/heads/master@{#67826}
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