1. 24 Mar, 2022 1 commit
    • Milad Fa's avatar
      PPC: Introduce Power10 prefixed instructions · d7966ecd
      Milad Fa authored
      P10 comes with prefixed instruction (2 x 4-byte instructions)
      which allow for using larger immediate values. `paddi` has
      been added in this CL which uses a 34-bit immediate.
      
      Prefixed instructions cannot cross 64-byte boundaries, i.e we cannot
      have the first 4-bytes on one side and the second 4-bytes emitted on
      the other side of the boundary. Therefore we need to align generated
      code to 64 bytes and emit a nop whenever the boundary is being crossed
      midway (check emit_prefix).
      
      Change-Id: I90e9953089214e15eeef0d70147ea5943fe05f45
      Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3528993Reviewed-by: 's avatarJakob Gruber <jgruber@chromium.org>
      Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
      Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
      Cr-Commit-Position: refs/heads/main@{#79612}
      d7966ecd
  2. 18 Nov, 2021 1 commit
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    • Milad Fa's avatar
      PPC: Fix UIM on disassembler and the simulator · 12b2a870
      Milad Fa authored
      A few fixes are applied in this CL:
      
      1- Instructions which use UIM in V8 only use bits 16 to 19 inclusive.
      2- get_simd_register is set to return a reference and not a copy.
      3- On vector extract and insert instructions, UIM could be used
      to select specific bytes as starting point which may not reflect a lane.
      Vector splat uses UIM as a lane selector which remains
      unchanged in this CL.
      
      Change-Id: Ieb43afb977dac11d3ea10a2f265c2823f64457e3
      Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3011166Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
      Commit-Queue: Milad Fa <mfarazma@redhat.com>
      Cr-Commit-Position: refs/heads/master@{#75618}
      12b2a870
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  29. 11 Dec, 2020 1 commit
    • Milad Fa's avatar
      PPC: [disasm] Introduce Simd128 vector registers · f664005a
      Milad Fa authored
      PPC has a set of 64 Vector Registers called VSX.
      The lower 32 of them are shared with Floating Point register (only
      64 bit of the registers are used for FP operations).
      
      The upper 32 registers are VR registers which are only used for
      VMX Vector operations.
      
      VSX Vector operations have the option to use the lower 32 or upper
      32 registers using the TX bit set on the instructions. VMX operations
      only use the upper 32 registers.
      
      In V8 we always set the VSX TX bit to "1" to make sure all the vector
      operations take place on the upper 32 registers.
      
      Change-Id: Ib3ea03254cbdc9547c3b698fe19c0c6b28138741
      Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2585260
      Commit-Queue: Milad Fa <mfarazma@redhat.com>
      Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
      Cr-Commit-Position: refs/heads/master@{#71722}
      f664005a
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