PPC: Implement mtcr on disassembler and the simulator

Change-Id: I575dffb8810ccc9e73cae2413c7993e0f4fdbbdd
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2764623
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Reviewed-by: Junliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/master@{#73447}

src/codegen/ppc/assembler-ppc.cc

@@ -1477,7 +1477,8 @@ void Assembler::mcrfs(CRegister cr, FPSCRBit bit) {
 
 void Assembler::mfcr(Register dst) { emit(EXT2 | MFCR | dst.code() * B21); }
 
-void Assembler::mtcrf(unsigned char FXM, Register src) {
+void Assembler::mtcr(Register src) {
+  uint8_t FXM = 0xFF;
   emit(MTCRF | src.code() * B21 | FXM * B12);
 }
 #if V8_TARGET_ARCH_PPC64

src/codegen/ppc/assembler-ppc.h

@@ -922,7 +922,7 @@ class Assembler : public AssemblerBase {
   void mtxer(Register src);
   void mcrfs(CRegister cr, FPSCRBit bit);
   void mfcr(Register dst);
-  void mtcrf(unsigned char FXM, Register src);
+  void mtcr(Register src);
 #if V8_TARGET_ARCH_PPC64
   void mffprd(Register dst, DoubleRegister src);
   void mffprwz(Register dst, DoubleRegister src);

src/compiler/backend/ppc/code-generator-ppc.cc

@@ -2985,7 +2985,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ li(ip, Operand(1));
       // Check if both lanes are 0, if so then return false.
       __ vxor(kScratchSimd128Reg, kScratchSimd128Reg, kScratchSimd128Reg);
-      __ mtcrf(0xFF, r0);  // Clear cr.
+      __ mtcr(r0);  // Clear cr.
       __ vcmpequd(kScratchSimd128Reg, src, kScratchSimd128Reg, SetRC);
       __ isel(dst, r0, ip, bit_number);
       break;
@@ -2998,7 +2998,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
   __ li(ip, Operand(1));                                               \
   /* Check if all lanes > 0, if not then return false.*/               \
   __ vxor(kScratchSimd128Reg, kScratchSimd128Reg, kScratchSimd128Reg); \
-  __ mtcrf(0xFF, r0); /* Clear cr.*/                                   \
+  __ mtcr(r0); /* Clear cr.*/                                          \
   __ opcode(kScratchSimd128Reg, src, kScratchSimd128Reg, SetRC);       \
   __ isel(dst, ip, r0, bit_number);
     case kPPC_I64x2AllTrue: {

src/diagnostics/ppc/disasm-ppc.cc

@@ -1060,6 +1060,10 @@ void Decoder::DecodeExt2(Instruction* instr) {
       Format(instr, "ldbrx   'rt, 'ra, 'rb");
       return;
     }
+    case MTCRF: {
+      Format(instr, "mtcr    'rs");
+      return;
+    }
 #endif
   }
 

src/execution/ppc/simulator-ppc.cc

@@ -3880,6 +3880,14 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
       set_d_register_from_double(frt, frt_val);
       return;
     }
+    case MTCRF: {
+      // This only simulates mtcr.
+      int rs = instr->RSValue();
+      uint8_t fxm = instr->Bits(19, 12);
+      DCHECK_EQ(fxm, 0xFF);
+      condition_reg_ = static_cast<int32_t>(get_register(rs));
+      break;
+    }
     // Vector instructions.
     case LVX: {
       DECODE_VX_INSTRUCTION(vrt, ra, rb, T)