PPC: [disasm] Introduce Simd128 vector registers

PPC has a set of 64 Vector Registers called VSX.
The lower 32 of them are shared with Floating Point register (only
64 bit of the registers are used for FP operations).

The upper 32 registers are VR registers which are only used for
VMX Vector operations.

VSX Vector operations have the option to use the lower 32 or upper
32 registers using the TX bit set on the instructions. VMX operations
only use the upper 32 registers.

In V8 we always set the VSX TX bit to "1" to make sure all the vector
operations take place on the upper 32 registers.

Change-Id: Ib3ea03254cbdc9547c3b698fe19c0c6b28138741
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2585260
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Reviewed-by: Junliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/master@{#71722}

src/codegen/ppc/constants-ppc.cc

@@ -21,6 +21,27 @@ const char* DoubleRegisters::names_[kNumDoubleRegisters] = {
     "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
     "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"};
 
+// PPC FP and Vector Register (VR and VSR) Layout.
+// VR0 is VSR32 and goes all the way to VSR63 which is used by V8 Vector
+// operations.
+//
+// VSR[0]0 - FPR[0]                     VSR[0]128
+//   |
+//   |
+//   |
+// VSR[31] - FPR[31]
+// VSR[32] - VR[0]                      VR[0]128
+//   |
+//   |
+//   |
+//   V
+// VSR[63] - VR[31]
+const char* Simd128Registers::names_[kNumSimd128Registers] = {
+    "v0",  "v1",   "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
+    "v8",  "v9",   "v10", "v11", "v12", "v13", "v14", "v15",
+    "v16", "v17",  "v18", "v19", "v20", "v21", "v22", "v23",
+    "v24", "vr25", "v26", "v27", "v28", "v29", "v30", "v31"};
+
 int DoubleRegisters::Number(const char* name) {
   for (int i = 0; i < kNumDoubleRegisters; i++) {
     if (strcmp(names_[i], name) == 0) {

src/codegen/ppc/constants-ppc.h

@@ -74,6 +74,9 @@ const int kNumRegisters = 32;
 // FP support.
 const int kNumDoubleRegisters = 32;
 
+// Vector support.
+const int kNumSimd128Registers = 32;
+
 const int kNoRegister = -1;
 
 // Used in embedded constant pool builder - max reach in bits for
@@ -3044,6 +3047,12 @@ class DoubleRegisters {
  private:
   static const char* names_[kNumDoubleRegisters];
 };
+
+// Helper functions for converting between Vector register names.
+class Simd128Registers {
+ public:
+  static const char* names_[kNumSimd128Registers];
+};
 }  // namespace internal
 }  // namespace v8
 

src/diagnostics/ppc/disasm-ppc.cc

@@ -67,8 +67,11 @@ class Decoder {
   // Printing of common values.
   void PrintRegister(int reg);
   void PrintDRegister(int reg);
+  void PrintVectorRegister(int reg);
   int FormatFPRegister(Instruction* instr, const char* format);
+  int FormatVectorRegister(Instruction* instr, const char* format);
   void PrintSoftwareInterrupt(SoftwareInterruptCodes svc);
+  const char* NameOfVectorRegister(int reg) const;
 
   // Handle formatting of instructions and their options.
   int FormatRegister(Instruction* instr, const char* option);
@@ -117,6 +120,8 @@ void Decoder::PrintDRegister(int reg) {
   Print(RegisterName(DoubleRegister::from_code(reg)));
 }
 
+void Decoder::PrintVectorRegister(int reg) { Print(NameOfVectorRegister(reg)); }
+
 // Print SoftwareInterrupt codes. Factoring this out reduces the complexity of
 // the FormatOption method.
 void Decoder::PrintSoftwareInterrupt(SoftwareInterruptCodes svc) {
@@ -138,6 +143,11 @@ void Decoder::PrintSoftwareInterrupt(SoftwareInterruptCodes svc) {
   }
 }
 
+const char* Decoder::NameOfVectorRegister(int reg) const {
+  if (0 <= reg && reg < 32) return Simd128Registers::names_[reg];
+  return "novectorreg";
+}
+
 // Handle all register based formatting in this function to reduce the
 // complexity of FormatOption.
 int Decoder::FormatRegister(Instruction* instr, const char* format) {
@@ -184,6 +194,26 @@ int Decoder::FormatFPRegister(Instruction* instr, const char* format) {
   return retval;
 }
 
+int Decoder::FormatVectorRegister(Instruction* instr, const char* format) {
+  int retval = 2;
+  int reg = -1;
+  if (format[1] == 't') {
+    reg = instr->RTValue();
+  } else if (format[1] == 'a') {
+    reg = instr->RAValue();
+  } else if (format[1] == 'b') {
+    reg = instr->RBValue();
+  } else if (format[1] == 'c') {
+    reg = instr->RCValue();
+  } else {
+    UNREACHABLE();
+  }
+
+  PrintVectorRegister(reg);
+
+  return retval;
+}
+
 // FormatOption takes a formatting string and interprets it based on
 // the current instructions. The format string points to the first
 // character of the option string (the option escape has already been
@@ -211,6 +241,17 @@ int Decoder::FormatOption(Instruction* instr, const char* format) {
     case 'D': {
       return FormatFPRegister(instr, format);
     }
+    case 'X': {
+      // Check the TX/SX value, if set then it's a Vector register.
+      if (instr->Bit(0) == 1) {
+        return FormatVectorRegister(instr, format);
+      }
+      // Double (VSX) register.
+      return FormatFPRegister(instr, format);
+    }
+    case 'V': {
+      return FormatVectorRegister(instr, format);
+    }
     case 'i': {  // int16
       int32_t value = (instr->Bits(15, 0) << 16) >> 16;
       out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value);