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Commit dd04f25b authored by Milad Farazmand's avatar Milad Farazmand Committed by Commit Bot
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PPC: [wasm-simd] Moving simd opcodes to the assembler header 


Change-Id: Ife10d7c8634cbd6b542dc522a49124f790f51921
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2216434Reviewed-by: 's avatarJunliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#67992}
parent 966692e5
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Showing with 142 additions and 196 deletions
src/codegen/ppc/assembler-ppc.cc
View file @ dd04f25b
......@@ -1768,118 +1768,11 @@ void Assembler::mfvsrwz(const Register ra, const DoubleRegister rs) {
emit(MFVSRWZ | rs.code() * B21 | ra.code() * B16 | SX);
}
void Assembler::mtvsrd(const DoubleRegister rt, const Register ra) {
void Assembler::mtvsrd(const Simd128Register rt, const Register ra) {
int TX = 1;
emit(MTVSRD | rt.code() * B21 | ra.code() * B16 | TX);
}
void Assembler::vor(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb) {
emit(VOR | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vxor(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb) {
emit(VXOR | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vnor(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb) {
emit(VNOR | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vsro(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb) {
emit(VSRO | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vslo(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb) {
emit(VSLO | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vperm(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb, const DoubleRegister rc) {
emit(VPERM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
rc.code() * B6);
}
void Assembler::vaddudm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VADDUDM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vadduwm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VADDUWM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vadduhm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VADDUHM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vaddubm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VADDUBM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vaddfp(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VADDFP | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vsubfp(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VSUBFP | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vsubudm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VSUBUDM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vsubuwm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VSUBUWM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vsubuhm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VSUBUHM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vsububm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VSUBUBM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vmuluwm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VMULUWM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vpkuhum(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VPKUHUM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vmuleub(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VMULEUB | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vmuloub(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb) {
emit(VMULOUB | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
void Assembler::vmladduhm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb, const Simd128Register rc) {
emit(VMLADDUHM | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
rc.code() * B6);
}
// Pseudo instructions.
void Assembler::nop(int type) {
Register reg = r0;
......
src/codegen/ppc/assembler-ppc.h
View file @ dd04f25b
......@@ -448,18 +448,44 @@ class Assembler : public AssemblerBase {
#undef DECLARE_PPC_XX3_INSTRUCTIONS
#define DECLARE_PPC_VX_INSTRUCTIONS_A_FORM(name, instr_name, instr_value) \
inline void name(const DoubleRegister rt, const DoubleRegister rb, \
inline void name(const Simd128Register rt, const Simd128Register rb, \
const Operand& imm) { \
vx_form(instr_name, rt, rb, imm); \
}
#define DECLARE_PPC_VX_INSTRUCTIONS_B_FORM(name, instr_name, instr_value) \
inline void name(const Simd128Register rt, const Simd128Register ra, \
const Simd128Register rb) { \
vx_form(instr_name, rt, ra, rb); \
}
inline void vx_form(Instr instr, DoubleRegister rt, DoubleRegister rb,
inline void vx_form(Instr instr, Simd128Register rt, Simd128Register rb,
const Operand& imm) {
emit(instr | rt.code() * B21 | imm.immediate() * B16 | rb.code() * B11);
}
inline void vx_form(Instr instr, Simd128Register rt, Simd128Register ra,
Simd128Register rb) {
emit(instr | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
}
PPC_VX_OPCODE_A_FORM_LIST(DECLARE_PPC_VX_INSTRUCTIONS_A_FORM)
PPC_VX_OPCODE_B_FORM_LIST(DECLARE_PPC_VX_INSTRUCTIONS_B_FORM)
#undef DECLARE_PPC_VX_INSTRUCTIONS_A_FORM
#undef DECLARE_PPC_VX_INSTRUCTIONS_B_FORM
#define DECLARE_PPC_VA_INSTRUCTIONS_A_FORM(name, instr_name, instr_value) \
inline void name(const Simd128Register rt, const Simd128Register ra, \
const Simd128Register rb, const Simd128Register rc) { \
va_form(instr_name, rt, ra, rb, rc); \
}
inline void va_form(Instr instr, Simd128Register rt, Simd128Register ra,
Simd128Register rb, Simd128Register rc) {
emit(instr | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
rc.code() * B6);
}
PPC_VA_OPCODE_A_FORM_LIST(DECLARE_PPC_VA_INSTRUCTIONS_A_FORM)
#undef DECLARE_PPC_VA_INSTRUCTIONS_A_FORM
RegList* GetScratchRegisterList() { return &scratch_register_list_; }
// ---------------------------------------------------------------------------
......@@ -950,49 +976,7 @@ class Assembler : public AssemblerBase {
// Vector instructions
void mfvsrd(const Register ra, const DoubleRegister r);
void mfvsrwz(const Register ra, const DoubleRegister r);
void mtvsrd(const DoubleRegister rt, const Register ra);
void vxor(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb);
void vnor(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb);
void vor(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb);
void vsro(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb);
void vslo(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb);
void vperm(const DoubleRegister rt, const DoubleRegister ra,
const DoubleRegister rb, const DoubleRegister rc);
void vaddudm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vadduwm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vadduhm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vaddubm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vaddfp(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vsubfp(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vsubudm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vsubuwm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vsubuhm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vsububm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vmuluwm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vpkuhum(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vmuleub(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vmuloub(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb);
void vmladduhm(const Simd128Register rt, const Simd128Register ra,
const Simd128Register rb, const Simd128Register rc);
void mtvsrd(const Simd128Register rt, const Register ra);
// Pseudo instructions
......
src/codegen/ppc/constants-ppc.h
View file @ dd04f25b
This diff is collapsed.
src/diagnostics/ppc/disasm-ppc.cc
View file @ dd04f25b
......@@ -364,6 +364,10 @@ void Decoder::DecodeExt0(Instruction* instr) {
Format(instr, "vperm 'Dt, 'Da, 'Db, 'Dc");
return;
}
case VMLADDUHM: {
Format(instr, "vmladduhm 'Dt, 'Da, 'Db, 'Dc");
return;
}
}
switch (EXT0 | (instr->BitField(10, 0))) {
case VSPLTB: {
......@@ -398,6 +402,62 @@ void Decoder::DecodeExt0(Instruction* instr) {
Format(instr, "vslo 'Dt, 'Da, 'Db");
break;
}
case VADDUDM: {
Format(instr, "vaddudm 'Dt, 'Da, 'Db");
break;
}
case VADDUWM: {
Format(instr, "vadduwm 'Dt, 'Da, 'Db");
break;
}
case VADDUHM: {
Format(instr, "vadduhm 'Dt, 'Da, 'Db");
break;
}
case VADDUBM: {
Format(instr, "vaddubm 'Dt, 'Da, 'Db");
break;
}
case VADDFP: {
Format(instr, "vaddfp 'Dt, 'Da, 'Db");
break;
}
case VSUBFP: {
Format(instr, "vsubfp 'Dt, 'Da, 'Db");
break;
}
case VSUBUDM: {
Format(instr, "vsubudm 'Dt, 'Da, 'Db");
break;
}
case VSUBUWM: {
Format(instr, "vsubuwm 'Dt, 'Da, 'Db");
break;
}
case VSUBUHM: {
Format(instr, "vsubuhm 'Dt, 'Da, 'Db");
break;
}
case VSUBUBM: {
Format(instr, "vsububm 'Dt, 'Da, 'Db");
break;
}
case VMULUWM: {
Format(instr, "vmuluwm 'Dt, 'Da, 'Db");
break;
}
case VPKUHUM: {
Format(instr, "vpkuhum 'Dt, 'Da, 'Db");
break;
}
case VMULEUB: {
Format(instr, "vmuleub 'Dt, 'Da, 'Db");
break;
}
case VMULOUB: {
Format(instr, "vmuloub 'Dt, 'Da, 'Db");
break;
}
}
}
......
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