PPC: Fix xxbrq encoding to include opcode constant

xxbrq includes a constant value of `31` as part the opcode. This CL
includes this constant within constants-ppc instead of adding
it while emitting code.


Change-Id: I897f5f86165c7b006a829dcb2ee2a0c9dc2ef1b3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2891935Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#74558}

src/codegen/ppc/assembler-ppc.cc

@@ -1900,12 +1900,6 @@ void Assembler::xxspltib(const Simd128Register rt, const Operand& imm) {
   emit(XXSPLTIB | rt.code() * B21 | imm.immediate() * B11 | TX);
 }
 
-void Assembler::xxbrq(const Simd128Register rt, const Simd128Register rb) {
-  int BX = 1;
-  int TX = 1;
-  emit(XXBRQ | rt.code() * B21 | 31 * B16 | rb.code() * B11 | BX * B1 | TX);
-}
-
 // Pseudo instructions.
 void Assembler::nop(int type) {
   Register reg = r0;

src/codegen/ppc/assembler-ppc.h

@@ -448,6 +448,7 @@ class Assembler : public AssemblerBase {
   }
 
   PPC_XX2_OPCODE_A_FORM_LIST(DECLARE_PPC_XX2_INSTRUCTIONS)
+  PPC_XX2_OPCODE_B_FORM_LIST(DECLARE_PPC_XX2_INSTRUCTIONS)
 #undef DECLARE_PPC_XX2_INSTRUCTIONS
 
 #define DECLARE_PPC_XX3_INSTRUCTIONS(name, instr_name, instr_value)    \
@@ -1043,7 +1044,6 @@ class Assembler : public AssemblerBase {
   void stxvd(const Simd128Register rt, const MemOperand& src);
   void stxvx(const Simd128Register rt, const MemOperand& src);
   void xxspltib(const Simd128Register rt, const Operand& imm);
-  void xxbrq(const Simd128Register rt, const Simd128Register rb);
 
   // Pseudo instructions
 

src/codegen/ppc/constants-ppc.h

@@ -418,6 +418,10 @@ using Instr = uint32_t;
   /* Saturate */                                                             \
   V(xvcvdpuxws, XVCVDPUXWS, 0xF0000320)
 
+#define PPC_XX2_OPCODE_B_FORM_LIST(V) \
+  /* Vector Byte-Reverse Quadword */  \
+  V(xxbrq, XXBRQ, 0xF01F076C)
+
 #define PPC_XX2_OPCODE_UNUSED_LIST(V)                                        \
   /* VSX Scalar Square Root Double-Precision */                              \
   V(xssqrtdp, XSSQRTDP, 0xF000012C)                                          \
@@ -520,12 +524,11 @@ using Instr = uint32_t;
   /* VSX Vector Test for software Square Root Single-Precision */            \
   V(xvtsqrtsp, XVTSQRTSP, 0xF00002A8)                                        \
   /* Vector Splat Immediate Byte */                                          \
-  V(xxspltib, XXSPLTIB, 0xF00002D0)                                          \
-  /* Vector Byte-Reverse Quadword */                                         \
-  V(xxbrq, XXBRQ, 0xF000076C)
+  V(xxspltib, XXSPLTIB, 0xF00002D0)
 
 #define PPC_XX2_OPCODE_LIST(V)  \
   PPC_XX2_OPCODE_A_FORM_LIST(V) \
+  PPC_XX2_OPCODE_B_FORM_LIST(V) \
   PPC_XX2_OPCODE_UNUSED_LIST(V)
 
 #define PPC_EVX_OPCODE_LIST(V)                                                \
@@ -2956,9 +2959,17 @@ class Instruction {
       PPC_XFX_OPCODE_LIST(OPCODE_CASES)
       return static_cast<Opcode>(opcode);
     }
+    // Some XX2 opcodes have integers hard coded in the middle, handle those
+    // first.
+    opcode = extcode | BitField(20, 16) | BitField(10, 2);
+    switch (opcode) {
+      PPC_XX2_OPCODE_B_FORM_LIST(OPCODE_CASES)
+      return static_cast<Opcode>(opcode);
+    }
     opcode = extcode | BitField(10, 2);
     switch (opcode) {
-      PPC_XX2_OPCODE_LIST(OPCODE_CASES)
+      PPC_XX2_OPCODE_A_FORM_LIST(OPCODE_CASES)
+      PPC_XX2_OPCODE_UNUSED_LIST(OPCODE_CASES)
       return static_cast<Opcode>(opcode);
     }
     opcode = extcode | BitField(10, 1);

src/diagnostics/ppc/disasm-ppc.cc

@@ -1295,12 +1295,6 @@ void Decoder::DecodeExt5(Instruction* instr) {
 }
 
 void Decoder::DecodeExt6(Instruction* instr) {
-  switch (EXT6 | (instr->BitField(10, 2))) {
-    case XXBRQ: {
-      Format(instr, "xxbrq  'Xt, 'Xb");
-      return;
-    }
-  }
   switch (EXT6 | (instr->BitField(10, 1))) {
     case XXSPLTIB: {
       Format(instr, "xxspltib  'Xt, 'IMM8");
@@ -1315,6 +1309,16 @@ void Decoder::DecodeExt6(Instruction* instr) {
   }
     PPC_XX3_OPCODE_LIST(DECODE_XX3_INSTRUCTIONS)
 #undef DECODE_XX3_INSTRUCTIONS
+  }
+  // Some encodings have integers hard coded in the middle, handle those first.
+  switch (EXT6 | (instr->BitField(20, 16)) | (instr->BitField(10, 2))) {
+#define DECODE_XX2_B_INSTRUCTIONS(name, opcode_name, opcode_value) \
+  case opcode_name: {                                              \
+    Format(instr, #name " 'Xt, 'Xb");                              \
+    return;                                                        \
+  }
+    PPC_XX2_OPCODE_B_FORM_LIST(DECODE_XX2_B_INSTRUCTIONS)
+#undef DECODE_XX2_B_INSTRUCTIONS
   }
   switch (EXT6 | (instr->BitField(10, 2))) {
 #define DECODE_XX2_A_INSTRUCTIONS(name, opcode_name, opcode_value) \
@@ -1323,8 +1327,8 @@ void Decoder::DecodeExt6(Instruction* instr) {
     return;                                                        \
   }
     PPC_XX2_OPCODE_A_FORM_LIST(DECODE_XX2_A_INSTRUCTIONS)
-  }
 #undef DECODE_XX2_A_INSTRUCTIONS
+  }
   Unknown(instr);  // not used by V8
 }