1. 18 Oct, 2017 1 commit
  2. 13 Oct, 2017 2 commits
  3. 14 Sep, 2017 1 commit
  4. 09 Sep, 2017 1 commit
    • Anisha Rohra's avatar
      s390/PPC: Make Register et al. real classes · 0b491c89
      Anisha Rohra authored
      Port 9e995e12
      Port 408f252b
      
        Up to now, each architecture defined all Register types as structs,
        with lots of redundancy. An often found comment noted that they cannot
        be classes due to initialization order problems. As these problems are
        gone with C++11 constexpr constants, I now tried making Registers
        classes again.
        All register types now inherit from RegisterBase, which provides a
        default set of methods and named constructors (like ::from_code,
        code(), bit(), is_valid(), ...).
        This design allows to guarantee an interesting property: Each register
        is either valid, or it's the no_reg register. There are no other
        invalid registers. This is guaranteed statically by the constexpr
        constructor, and dynamically by ::from_code.
      
        I decided to disallow the default constructor completely, so instead of
        "Register reg;" you now need "Register reg = no_reg;". This makes
        explicit how the Register is initialized.
      
        I did this change to the x64, ia32, arm, arm64, mips and mips64 ports.
        Overall, code got much more compact and more safe. In theory, it should
        also increase performance (since the is_valid() check is simpler), but
        this is probably not measurable.
      
      R=bjaideep@ca.ibm.com, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com
      BUG=
      LOG=N
      
      Change-Id: I2e87efc8790290c64fd6c0a2d093326710b30ed3
      Reviewed-on: https://chromium-review.googlesource.com/658065Reviewed-by: 's avatarJaideep Bajwa <bjaideep@ca.ibm.com>
      Commit-Queue: Jaideep Bajwa <bjaideep@ca.ibm.com>
      Cr-Commit-Position: refs/heads/master@{#47933}
      0b491c89
  5. 07 Sep, 2017 1 commit
  6. 16 Aug, 2017 1 commit
  7. 01 Aug, 2017 1 commit
  8. 26 Jul, 2017 1 commit
    • Jaideep Bajwa's avatar
      PPC/s390: Move TF parts of MacroAssembler into new TurboAssembler. · 2b23e892
      Jaideep Bajwa authored
      Port dfdcaf43
      Port 2e1f5567
      
      Original Commit Message:
      
          This CL introduces TurboAssembler, a super-class of Assembler and sub-class
          of MacroAssembler. TurboAssembler contains all the functionality that is used
          by Turbofan and previously was part of MacroAssembler. TurboAssembler has
          access to the isolate but, in contrast to MacroAssembler, does not expect to
          be running on the main thread.
      
      R=neis@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com
      BUG=v8:6048
      LOG=N
      
      Change-Id: I3f51771afefe46410db7cda2625472d78c87f8c6
      Reviewed-on: https://chromium-review.googlesource.com/583584Reviewed-by: 's avatarGeorg Neis <neis@chromium.org>
      Commit-Queue: Jaideep Bajwa <bjaideep@ca.ibm.com>
      Cr-Commit-Position: refs/heads/master@{#46900}
      2b23e892
  9. 24 Jul, 2017 2 commits
  10. 29 Jun, 2017 1 commit
  11. 23 Jun, 2017 1 commit
  12. 08 Jun, 2017 1 commit
    • sampsong's avatar
      PPC/s390: [compiler] Delay allocation of code-embedded heap numbers. · ae947e26
      sampsong authored
      Port 659e8f7b
      
      Original Commit Message:
      
          Instead of allocating and embedding certain heap numbers into the code
          during code assembly, emit dummies but record the allocation requests.
          Later then, in Assembler::GetCode, allocate the heap numbers and patch
          the code by replacing the dummies with the actual objects. The
          RelocInfos for the embedded objects are already recorded correctly when
          emitting the dummies.
      
      R=neis@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, bjaideep@ca.ibm.com, michael_dawson@ca.ibm.com
      BUG=v8:6048
      LOG=N
      
      Review-Url: https://codereview.chromium.org/2929843002
      Cr-Commit-Position: refs/heads/master@{#45793}
      ae947e26
  13. 28 Apr, 2017 1 commit
  14. 17 Mar, 2017 1 commit
    • neis's avatar
      Disentangle assembler from isolate. · 94b088ca
      neis authored
      This is a first step towards moving Turbofan code generation off the main thread.
      
      Summary of the changes:
      - AssemblerBase no longer has a pointer to the isolate. Instead, its
        constructor receives the few things that it needs from the isolate (on most
        architectures this is just the serializer_enabled flag).
      - RelocInfo no longer has a pointer to the isolate. Instead, the functions
        that need it take it as an argument.  (There are currently still a few that
        implicitly access the isolate through a HeapObject.)
      - The MacroAssembler now explicitly holds a pointer to the isolate (before, it
        used to get it from the Assembler).
      - The jit_cookie also moved from AssemblerBase to the MacroAssemblers, since
        it's not used at all in the Assemblers.
      - A few architectures implemented parts of the Assembler with the help
        of a Codepatcher that is based on MacroAssembler.  Since the Assembler no
        longer has the isolate, but the MacroAssembler still needs it, this doesn't
        work anymore.  Instead, these Assemblers now use a new PatchingAssembler.
      
      BUG=v8:6048
      
      Review-Url: https://codereview.chromium.org/2732273003
      Cr-Commit-Position: refs/heads/master@{#43890}
      94b088ca
  15. 10 Mar, 2017 1 commit
  16. 08 Mar, 2017 1 commit
    • bjaideep's avatar
      PPC/s390: [assembler] Make register definitions constexpr · e7be85da
      bjaideep authored
      Port e82b7ccd
      
      Original Commit Message:
      
          I originally needed this for the initialization of a constexpr array in
          the wasm lazy compile builtin, but since it's a bigger change, I now
          split it off as this separate CL.
          The style guide recommends constexpr over const. I thus apply the
          constexprificaton over all headers that I touched anyway.
      
          I also remove the ARM64_DEFINE_REG_STATICS hack. It was introduced when
          merging in arm64 support more than three years ago, and I don't see the
          purpose for this.
          Also, some #defines can now be constexpr definitions, which was not
          possible before according to the comment.
      
      R=clemensh@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com
      BUG=
      LOG=N
      
      Review-Url: https://codereview.chromium.org/2733323003
      Cr-Commit-Position: refs/heads/master@{#43678}
      e7be85da
  17. 01 Mar, 2017 1 commit
  18. 21 Feb, 2017 1 commit
    • bbudge's avatar
      [V8] Implement SIMD Boolean vector types to allow mask registers. · 9fe0b4c7
      bbudge authored
      - Adds new machine types SimdBool4/8/16 for the different boolean vector types.
      - Adds a kSimdMaskRegisters flag for each platform. These are all false for now.
      - Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle
        opcodes from the Boolean types. These are unlikely to be well supported natively,
        and can be synthesized using Select.
      - Changes the signature of Relational opcodes to return boolean vectors.
      - Changes the signature of Select opcodes to take boolean vectors.
      - Updates the ARM implementation of Relational and Select opcodes.
      
      LOG=N
      BUG=v8:4124
      
      Review-Url: https://codereview.chromium.org/2700813002
      Cr-Commit-Position: refs/heads/master@{#43348}
      9fe0b4c7
  19. 17 Feb, 2017 1 commit
  20. 13 Feb, 2017 1 commit
  21. 09 Feb, 2017 2 commits
  22. 08 Feb, 2017 1 commit
  23. 03 Feb, 2017 1 commit
  24. 25 Jan, 2017 1 commit
    • jyan's avatar
      s390: TF Codegen Optimization · f7a3ede0
      jyan authored
      List of items:
        1. Avoid zero-extending for subsequent 32-bit operations if current operation does not change upper 32-bit or does zero-extending.
        2. Match complex address mode for binary operation where possible (eg. use Add R,MEM).
        3. Detect instruction forms in selector. Eg. kAllowRRR, kAllowRM
        4. Optimize sequence for Int32MulWithOverflow, Int32Div, etc.
        5. Remove Not32/Not64 which is the same as XOR
      
      R=bjaideep@ca.ibm.com, joransiu@ca.ibm.com
      BUG=
      
      Review-Url: https://codereview.chromium.org/2649113007
      Cr-Commit-Position: refs/heads/master@{#42669}
      f7a3ede0
  25. 22 Dec, 2016 1 commit
    • joransiu's avatar
      S390: Optimize allocate sequence · 0ddb3645
      joransiu authored
      Improve the S390 allocate sequence by:
      - Keeping allocation limit in memory, and leverage compare RX-instr.
      - Prefetching subsequent cache lines from allocation top.
      - Optimizing object tagging with LA
      - Optimizing increment for Fast-Allocate with ASI/AGSI
      
      R=jyan@ca.ibm.com, michael_dawson@ca.ibm.com, bjaideep@ca.ibm.com
      BUG=
      
      Review-Url: https://codereview.chromium.org/2601563002
      Cr-Commit-Position: refs/heads/master@{#41933}
      0ddb3645
  26. 20 Dec, 2016 1 commit
  27. 19 Dec, 2016 1 commit
  28. 16 Dec, 2016 1 commit
  29. 24 Nov, 2016 1 commit
  30. 22 Nov, 2016 1 commit
  31. 14 Nov, 2016 1 commit
    • tebbi's avatar
      This CL enables precise source positions for all V8 compilers. It merges... · c3a6ca68
      tebbi authored
      This CL enables precise source positions for all V8 compilers. It merges compiler::SourcePosition and internal::SourcePosition to a single class used throughout the codebase. The new internal::SourcePosition instances store an id identifying an inlined function in addition to a script offset.
      SourcePosition::InliningId() refers to a the new table DeoptimizationInputData::InliningPositions(), which provides the following data for every inlining id:
       - The inlined SharedFunctionInfo as an offset into DeoptimizationInfo::LiteralArray
       - The SourcePosition of the inlining. Recursively, this yields the full inlining stack.
      Before the Code object is created, the same information can be found in CompilationInfo::inlined_functions().
      
      If SourcePosition::InliningId() is SourcePosition::kNotInlined, it refers to the outer (non-inlined) function.
      So every SourcePosition has full information about its inlining stack, as long as the corresponding Code object is known. The internal represenation of a source position is a positive 64bit integer.
      
      All compilers create now appropriate source positions for inlined functions. In the case of Turbofan, this required using AstGraphBuilderWithPositions for inlined functions too. So this class is now moved to a header file.
      
      At the moment, the additional information in source positions is only used in --trace-deopt and --code-comments. The profiler needs to be updated, at the moment it gets the correct script offsets from the deopt info, but the wrong script id from the reconstructed deopt stack, which can lead to wrong outputs. This should be resolved by making the profiler use the new inlining information for deopts.
      
      I activated the inlined deoptimization tests in test-cpu-profiler.cc for Turbofan, changing them to a case where the deopt stack and the inlining position agree. It is currently still broken for other cases.
      
      The following additional changes were necessary:
       - The source position table (internal::SourcePositionTableBuilder etc.) supports now 64bit source positions. Encoding source positions in a single 64bit int together with the difference encoding in the source position table results in very little overhead for the inlining id, since only 12% of the source positions in Octane have a changed inlining id.
       - The class HPositionInfo was effectively dead code and is now removed.
       - SourcePosition has new printing and information facilities, including computing a full inlining stack.
       - I had to rename compiler/source-position.{h,cc} to compiler/compiler-source-position-table.{h,cc} to avoid clashes with the new src/source-position.cc file.
       - I wrote the new wrapper PodArray for ByteArray. It is a template working with any POD-type. This is used in DeoptimizationInputData::InliningPositions().
       - I removed HInlinedFunctionInfo and HGraph::inlined_function_infos, because they were only used for the now obsolete Crankshaft inlining ids.
       - Crankshaft managed a list of inlined functions in Lithium: LChunk::inlined_functions. This is an analog structure to CompilationInfo::inlined_functions. So I removed LChunk::inlined_functions and made Crankshaft use CompilationInfo::inlined_functions instead, because this was necessary to register the offsets into the literal array in a uniform way. This is a safe change because LChunk::inlined_functions has no other uses and the functions in CompilationInfo::inlined_functions have a strictly longer lifespan, being created earlier (in Hydrogen already).
      
      BUG=v8:5432
      
      Review-Url: https://codereview.chromium.org/2451853002
      Cr-Commit-Position: refs/heads/master@{#40975}
      c3a6ca68
  32. 22 Aug, 2016 1 commit
  33. 15 Aug, 2016 1 commit
  34. 09 Aug, 2016 1 commit
  35. 08 Aug, 2016 1 commit
    • jyan's avatar
      S390: Decouple Add/Sub/Neg to 32/64 Bit Op · dc884581
      jyan authored
      1. Decouple kS390_Add/Sub/Neg to
           kS390_Add32/Sub32/Neg32/Add64/Sub64/Neg64
      2. Nuke kS390_Add/SubWithOverflow32
      3. Add Support for Load-On-Condition to optimize AssembleArchBoolean
      
      R=joransiu@ca.ibm.com, michael_dawson@ca.ibm.com, mbrandy@us.ibm.com, bjaideep@ca.ibm.com
      BUG=
      
      Review-Url: https://codereview.chromium.org/2220313002
      Cr-Commit-Position: refs/heads/master@{#38443}
      dc884581
  36. 29 Jul, 2016 1 commit
  37. 19 Jul, 2016 1 commit