PPC/s390: Implement VisitFloat32Neg/VisitFloat64Neg and instr lcebr for s390

Implemented instruction selector functions VisitFloat32Neg/VisitFloat64Neg
for s390 and ppc. For s390 implemented instruction lcebr to load complement
for floatregisters.

R=joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com, mbrandy@us.ibm.com

BUG=
LOG=N

Review-Url: https://codereview.chromium.org/2226103002
Cr-Commit-Position: refs/heads/master@{#38466}

src/compiler/ppc/instruction-selector-ppc.cc

@@ -1426,9 +1426,13 @@ void InstructionSelector::VisitFloat64RoundTiesEven(Node* node) {
   UNREACHABLE();
 }
 
-void InstructionSelector::VisitFloat32Neg(Node* node) { UNREACHABLE(); }
+void InstructionSelector::VisitFloat32Neg(Node* node) {
+  VisitRR(this, kPPC_NegDouble, node);
+}
 
-void InstructionSelector::VisitFloat64Neg(Node* node) { UNREACHABLE(); }
+void InstructionSelector::VisitFloat64Neg(Node* node) {
+  VisitRR(this, kPPC_NegDouble, node);
+}
 
 void InstructionSelector::VisitInt32AddWithOverflow(Node* node) {
   if (Node* ovf = NodeProperties::FindProjection(node, 1)) {

src/compiler/s390/code-generator-s390.cc

@@ -1453,6 +1453,9 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ fidbra(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
                 v8::internal::Assembler::FIDBRA_ROUND_TO_NEAREST_AWAY_FROM_0);
       break;
+    case kS390_NegFloat:
+      ASSEMBLE_FLOAT_UNOP(lcebr);
+      break;
     case kS390_NegDouble:
       ASSEMBLE_FLOAT_UNOP(lcdbr);
       break;

src/compiler/s390/instruction-codes-s390.h

@@ -67,6 +67,7 @@ namespace compiler {
   V(S390_Neg32)                    \
   V(S390_Neg64)                    \
   V(S390_NegDouble)                \
+  V(S390_NegFloat)                 \
   V(S390_SqrtFloat)                \
   V(S390_FloorFloat)               \
   V(S390_CeilFloat)                \

src/compiler/s390/instruction-scheduler-s390.cc

@@ -68,6 +68,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kS390_Neg32:
     case kS390_Neg64:
     case kS390_NegDouble:
+    case kS390_NegFloat:
     case kS390_SqrtFloat:
     case kS390_FloorFloat:
     case kS390_CeilFloat:

src/compiler/s390/instruction-selector-s390.cc

@@ -1279,9 +1279,13 @@ void InstructionSelector::VisitFloat64RoundTiesEven(Node* node) {
   UNREACHABLE();
 }
 
-void InstructionSelector::VisitFloat32Neg(Node* node) { UNREACHABLE(); }
+void InstructionSelector::VisitFloat32Neg(Node* node) {
+  VisitRR(this, kS390_NegFloat, node);
+}
 
-void InstructionSelector::VisitFloat64Neg(Node* node) { UNREACHABLE(); }
+void InstructionSelector::VisitFloat64Neg(Node* node) {
+  VisitRR(this, kS390_NegDouble, node);
+}
 
 void InstructionSelector::VisitInt32AddWithOverflow(Node* node) {
   if (Node* ovf = NodeProperties::FindProjection(node, 1)) {

src/s390/assembler-s390.cc

@@ -2781,6 +2781,12 @@ void Assembler::lcdbr(DoubleRegister r1, DoubleRegister r2) {
            Register::from_code(r2.code()));
 }
 
+// Load Complement Register-Register (LB)
+void Assembler::lcebr(DoubleRegister r1, DoubleRegister r2) {
+  rre_form(LCEBR, Register::from_code(r1.code()),
+           Register::from_code(r2.code()));
+}
+
 // Load Positive Register-Register (LB)
 void Assembler::lpebr(DoubleRegister r1, DoubleRegister r2) {
   rre_form(LPEBR, Register::from_code(r1.code()),

src/s390/assembler-s390.h

@@ -1181,6 +1181,7 @@ class Assembler : public AssemblerBase {
   void sqdb(DoubleRegister r1, const MemOperand& opnd);
   void sqdbr(DoubleRegister r1, DoubleRegister r2);
   void lcdbr(DoubleRegister r1, DoubleRegister r2);
+  void lcebr(DoubleRegister r1, DoubleRegister r2);
   void ldeb(DoubleRegister r1, const MemOperand& opnd);
 
   enum FIDBRA_MASK3 {

src/s390/disasm-s390.cc

@@ -1000,6 +1000,9 @@ bool Decoder::DecodeFourByte(Instruction* instr) {
     case LCDBR:
       Format(instr, "lcdbr\t'f5,'f6");
       break;
+    case LCEBR:
+      Format(instr, "lcebr\t'f5,'f6");
+      break;
     case STH:
       Format(instr, "sth\t'r1,'d1('r2d,'r3)");
       break;

src/s390/simulator-s390.cc

@@ -4154,6 +4154,7 @@ bool Simulator::DecodeFourByteFloatingPoint(Instruction* instr) {
     case CFEBR:
     case CEFBR:
     case LCDBR:
+    case LCEBR:
     case LPDBR:
     case LPEBR: {
       RREInstruction* rreInstr = reinterpret_cast<RREInstruction*>(instr);
@@ -4260,6 +4261,18 @@ bool Simulator::DecodeFourByteFloatingPoint(Instruction* instr) {
         } else if (r2_val > 0) {
           condition_reg_ = CC_GT;
         }
+      } else if (op == LCEBR) {
+        fr1_val = -fr2_val;
+        set_d_register_from_float32(r1, fr1_val);
+        if (fr2_val != fr2_val) {  // input is NaN
+          condition_reg_ = CC_OF;
+        } else if (fr2_val == 0) {
+          condition_reg_ = CC_EQ;
+        } else if (fr2_val < 0) {
+          condition_reg_ = CC_LT;
+        } else if (fr2_val > 0) {
+          condition_reg_ = CC_GT;
+        }
       } else if (op == LPDBR) {
         r1_val = std::fabs(r2_val);
         set_d_register_from_double(r1, r1_val);
@@ -8505,9 +8518,22 @@ EVALUATE(LTEBR) {
 }
 
 EVALUATE(LCEBR) {
-  UNIMPLEMENTED();
-  USE(instr);
-  return 0;
+  DCHECK_OPCODE(LCEBR);
+  DECODE_RRE_INSTRUCTION(r1, r2);
+  float fr1_val = get_float32_from_d_register(r1);
+  float fr2_val = get_float32_from_d_register(r2);
+  fr1_val = -fr2_val;
+  set_d_register_from_float32(r1, fr1_val);
+  if (fr2_val != fr2_val) {  // input is NaN
+    condition_reg_ = CC_OF;
+  } else if (fr2_val == 0) {
+    condition_reg_ = CC_EQ;
+  } else if (fr2_val < 0) {
+    condition_reg_ = CC_LT;
+  } else if (fr2_val > 0) {
+    condition_reg_ = CC_GT;
+  }
+  return length;
 }
 
 EVALUATE(LDEBR) {