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Commit 4675c975 authored by sampsong's avatar sampsong Committed by Commit bot
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Use S390X_RX_A_OPCODE_LIST macro to declare rx format assembler function 

BUG=

R=jyan@ca.ibm.com, joransiu@ca.ibm.com, bjaideep@ca.ibm.com

Review-Url: https://codereview.chromium.org/2667353005
Cr-Commit-Position: refs/heads/master@{#42933}
parent 325b87ba
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Showing with 38 additions and 229 deletions
src/s390/assembler-s390.cc
View file @ 4675c975
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src/s390/assembler-s390.h
View file @ 4675c975
......@@ -702,6 +702,37 @@ class Assembler : public AssemblerBase {
getfield<uint32_t, 4, 24, 28>(f3) | getfield<uint32_t, 4, 28, 32>(f4));
}
#define DECLARE_S390_RX_INSTRUCTIONS(name, op_name, op_value) \
template <class R1> \
inline void name(R1 r1, Register x2, Register b2, Disp d2) { \
rx_format(op_name, r1.code(), x2.code(), b2.code(), d2); \
} \
template <class R1> \
inline void name(R1 r1, const MemOperand& opnd) { \
name(r1, opnd.getIndexRegister(), \
opnd.getBaseRegister(), opnd.getDisplacement()); \
}
inline void rx_format(Opcode opcode, int f1, int f2, int f3, int f4) {
DCHECK(is_uint8(opcode));
DCHECK(is_uint12(f4));
emit4bytes(getfield<uint32_t, 4, 0, 8>(opcode) |
getfield<uint32_t, 4, 8, 12>(f1) |
getfield<uint32_t, 4, 12, 16>(f2) |
getfield<uint32_t, 4, 16, 20>(f3) |
getfield<uint32_t, 4, 20, 32>(f4));
}
S390_RX_A_OPCODE_LIST(DECLARE_S390_RX_INSTRUCTIONS)
void bc(Condition cond, const MemOperand& opnd) {
bc(cond, opnd.getIndexRegister(),
opnd.getBaseRegister(), opnd.getDisplacement());
}
void bc(Condition cond, Register x2, Register b2, Disp d2) {
rx_format(BC, cond, x2.code(), b2.code(), d2);
}
#undef DECLARE_S390_RX_INSTRUCTIONS
// Helper for unconditional branch to Label with update to save register
void b(Register r, Label* l) {
int32_t halfwords = branch_offset(l) / 2;
......@@ -790,10 +821,6 @@ class Assembler : public AssemblerBase {
#define RR2_FORM(name) void name(Condition m1, Register r2)
#define RX_FORM(name) \
void name(Register r1, Register x2, Register b2, Disp d2); \
void name(Register r1, const MemOperand& opnd)
#define RI1_FORM(name) void name(Register r, const Operand& i)
#define RI2_FORM(name) void name(Condition m, const Operand& i)
......@@ -957,21 +984,16 @@ class Assembler : public AssemblerBase {
}
// S390 instruction sets
RX_FORM(bc);
RX_FORM(cd);
RXE_FORM(cdb);
RXE_FORM(ceb);
RXE_FORM(ddb);
SS1_FORM(ed);
RX_FORM(ex);
RRF2_FORM(fidbr);
RX_FORM(ic_z);
RXY_FORM(icy);
RI1_FORM(iihh);
RI1_FORM(iihl);
RI1_FORM(iilh);
RI1_FORM(iill);
RX_FORM(le_z);
RXY_FORM(ley);
RSY1_FORM(loc);
RXY_FORM(lrv);
......@@ -994,7 +1016,6 @@ class Assembler : public AssemblerBase {
RXE_FORM(sdb);
RXY_FORM(slgf);
RS1_FORM(srdl);
RX_FORM(ste);
RXY_FORM(stey);
RXY_FORM(strv);
RXY_FORM(strvh);
......@@ -1004,17 +1025,14 @@ class Assembler : public AssemblerBase {
S_FORM(ts);
// Load Address Instructions
void la(Register r, const MemOperand& opnd);
void lay(Register r, const MemOperand& opnd);
void larl(Register r, Label* l);
// Load Instructions
void lb(Register r, const MemOperand& src);
void lgb(Register r, const MemOperand& src);
void lh(Register r, const MemOperand& src);
void lhy(Register r, const MemOperand& src);
void lgh(Register r, const MemOperand& src);
void l(Register r, const MemOperand& src);
void ly(Register r, const MemOperand& src);
void lg(Register r, const MemOperand& src);
void lgf(Register r, const MemOperand& src);
......@@ -1044,11 +1062,8 @@ class Assembler : public AssemblerBase {
void locg(Condition m3, Register r1, const MemOperand& src);
// Store Instructions
void st(Register r, const MemOperand& src);
void stc(Register r, const MemOperand& src);
void stcy(Register r, const MemOperand& src);
void stg(Register r, const MemOperand& src);
void sth(Register r, const MemOperand& src);
void sthy(Register r, const MemOperand& src);
void sty(Register r, const MemOperand& src);
......@@ -1058,16 +1073,13 @@ class Assembler : public AssemblerBase {
void stmg(Register r1, Register r2, const MemOperand& src);
// Compare Instructions
void c(Register r, const MemOperand& opnd);
void cy(Register r, const MemOperand& opnd);
void cg(Register r, const MemOperand& opnd);
void ch(Register r, const MemOperand& opnd);
void chy(Register r, const MemOperand& opnd);
void chi(Register r, const Operand& opnd);
void cghi(Register r, const Operand& opnd);
// Compare Logical Instructions
void cl(Register r, const MemOperand& opnd);
void cly(Register r, const MemOperand& opnd);
void clg(Register r, const MemOperand& opnd);
void cli(const MemOperand& mem, const Operand& imm);
......@@ -1131,7 +1143,6 @@ class Assembler : public AssemblerBase {
void mvc(const MemOperand& opnd1, const MemOperand& opnd2, uint32_t length);
// Branch Instructions
void bct(Register r, const MemOperand& opnd);
void bctg(Register r, const MemOperand& opnd);
void bras(Register r, const Operand& opnd);
void brc(Condition c, const Operand& opnd);
......@@ -1139,9 +1150,7 @@ class Assembler : public AssemblerBase {
void brctg(Register r1, const Operand& opnd);
// 32-bit Add Instructions
void a(Register r1, const MemOperand& opnd);
void ay(Register r1, const MemOperand& opnd);
void ah(Register r1, const MemOperand& opnd);
void ahy(Register r1, const MemOperand& opnd);
void ahi(Register r1, const Operand& opnd);
void ahik(Register r1, Register r3, const Operand& opnd);
......@@ -1157,7 +1166,6 @@ class Assembler : public AssemblerBase {
void agsi(const MemOperand&, const Operand&);
// 32-bit Add Logical Instructions
void al_z(Register r1, const MemOperand& opnd);
void aly(Register r1, const MemOperand& opnd);
void alrk(Register r1, Register r2, Register r3);
......@@ -1166,9 +1174,7 @@ class Assembler : public AssemblerBase {
void algrk(Register r1, Register r2, Register r3);
// 32-bit Subtract Instructions
void s(Register r1, const MemOperand& opnd);
void sy(Register r1, const MemOperand& opnd);
void sh(Register r1, const MemOperand& opnd);
void shy(Register r1, const MemOperand& opnd);
void srk(Register r1, Register r2, Register r3);
......@@ -1178,7 +1184,6 @@ class Assembler : public AssemblerBase {
void sgrk(Register r1, Register r2, Register r3);
// 32-bit Subtract Logical Instructions
void sl(Register r1, const MemOperand& opnd);
void sly(Register r1, const MemOperand& opnd);
void slrk(Register r1, Register r2, Register r3);
......@@ -1187,12 +1192,9 @@ class Assembler : public AssemblerBase {
void slgrk(Register r1, Register r2, Register r3);
// 32-bit Multiply Instructions
void m(Register r1, const MemOperand& opnd);
void mfy(Register r1, const MemOperand& opnd);
void ml(Register r1, const MemOperand& opnd);
void ms(Register r1, const MemOperand& opnd);
void msy(Register r1, const MemOperand& opnd);
void mh(Register r1, const MemOperand& opnd);
void mhy(Register r1, const MemOperand& opnd);
void mhi(Register r1, const Operand& opnd);
......@@ -1202,21 +1204,17 @@ class Assembler : public AssemblerBase {
void msg(Register r1, const MemOperand& opnd);
// 32-bit Divide Instructions
void d(Register r1, const MemOperand& opnd);
void dl(Register r1, const MemOperand& opnd);
// Bitwise Instructions (AND / OR / XOR)
void n(Register r1, const MemOperand& opnd);
void ny(Register r1, const MemOperand& opnd);
void nrk(Register r1, Register r2, Register r3);
void ng(Register r1, const MemOperand& opnd);
void ngrk(Register r1, Register r2, Register r3);
void o(Register r1, const MemOperand& opnd);
void oy(Register r1, const MemOperand& opnd);
void ork(Register r1, Register r2, Register r3);
void og(Register r1, const MemOperand& opnd);
void ogrk(Register r1, Register r2, Register r3);
void x(Register r1, const MemOperand& opnd);
void xy(Register r1, const MemOperand& opnd);
void xrk(Register r1, Register r2, Register r3);
void xg(Register r1, const MemOperand& opnd);
......@@ -1224,13 +1222,9 @@ class Assembler : public AssemblerBase {
void xc(const MemOperand& opnd1, const MemOperand& opnd2, Length length);
// Floating Point Load / Store Instructions
void ld(DoubleRegister r1, const MemOperand& opnd);
void ldy(DoubleRegister r1, const MemOperand& opnd);
void le_z(DoubleRegister r1, const MemOperand& opnd);
void ley(DoubleRegister r1, const MemOperand& opnd);
void std(DoubleRegister r1, const MemOperand& opnd);
void stdy(DoubleRegister r1, const MemOperand& opnd);
void ste(DoubleRegister r1, const MemOperand& opnd);
void stey(DoubleRegister r1, const MemOperand& opnd);
// Floating <-> Fixed Point Conversion Instructions
......@@ -1449,11 +1443,6 @@ class Assembler : public AssemblerBase {
inline void rr2_form(uint8_t op, Condition m1, Register r2);
inline void rx_form(Opcode op, Register r1, Register x2, Register b2,
Disp d2);
inline void rx_form(Opcode op, DoubleRegister r1, Register x2, Register b2,
Disp d2);
inline void ri_form(Opcode op, Register r1, const Operand& i2);
inline void ri_form(Opcode op, Condition m1, const Operand& i2);
......
src/s390/constants-s390.h
View file @ 4675c975
......@@ -1142,7 +1142,7 @@ typedef uint64_t SixByteInstr;
V(ex, EX, 0x44) /* type = RX_A EXECUTE */ \
V(bal, BAL, 0x45) /* type = RX_A BRANCH AND LINK */ \
V(bct, BCT, 0x46) /* type = RX_A BRANCH ON COUNT (32) */ \
V(bc, BC, 0x47) /* type = RX_A BRANCH ON CONDITION */ \
V(lh, LH, 0x48) /* type = RX_A LOAD HALFWORD (32<-16) */ \
V(ch, CH, 0x49) /* type = RX_A COMPARE HALFWORD (32<-16) */ \
V(ah, AH, 0x4A) /* type = RX_A ADD HALFWORD (32<-16) */ \
V(sh, SH, 0x4B) /* type = RX_A SUBTRACT HALFWORD (32<-16) */ \
......@@ -1162,7 +1162,7 @@ typedef uint64_t SixByteInstr;
V(s, S, 0x5B) /* type = RX_A SUBTRACT (32) */ \
V(m, M, 0x5C) /* type = RX_A MULTIPLY (64<-32) */ \
V(d, D, 0x5D) /* type = RX_A DIVIDE (32<-64) */ \
V(al, AL, 0x5E) /* type = RX_A ADD LOGICAL (32) */ \
V(al_z, AL, 0x5E) /* type = RX_A ADD LOGICAL (32) */ \
V(sl, SL, 0x5F) /* type = RX_A SUBTRACT LOGICAL (32) */ \
V(std, STD, 0x60) /* type = RX_A STORE (long) */ \
V(mxd, MXD, 0x67) /* type = RX_A MULTIPLY (long to extended HFP) */ \
......@@ -1176,7 +1176,7 @@ typedef uint64_t SixByteInstr;
V(sw, SW, 0x6F) /* type = RX_A SUBTRACT UNNORMALIZED (long HFP) */ \
V(ste, STE, 0x70) /* type = RX_A STORE (short) */ \
V(ms, MS, 0x71) /* type = RX_A MULTIPLY SINGLE (32) */ \
V(le, LE, 0x78) /* type = RX_A LOAD (short) */ \
V(le_z, LE, 0x78) /* type = RX_A LOAD (short) */ \
V(ce, CE, 0x79) /* type = RX_A COMPARE (short HFP) */ \
V(ae, AE, 0x7A) /* type = RX_A ADD NORMALIZED (short HFP) */ \
V(se, SE, 0x7B) /* type = RX_A SUBTRACT NORMALIZED (short HFP) */ \
......@@ -1186,10 +1186,11 @@ typedef uint64_t SixByteInstr;
V(au, AU, 0x7E) /* type = RX_A ADD UNNORMALIZED (short HFP) */ \
V(su, SU, 0x7F) /* type = RX_A SUBTRACT UNNORMALIZED (short HFP) */ \
V(ssm, SSM, 0x80) /* type = RX_A SET SYSTEM MASK */ \
V(lra, LRA, 0xB1) /* type = RX_A LOAD REAL ADDRESS (32) */
V(lra, LRA, 0xB1) /* type = RX_A LOAD REAL ADDRESS (32) */ \
V(sth, STH, 0x40) /* type = RX_A STORE HALFWORD (16) */
#define S390_RX_B_OPCODE_LIST(V) \
V(lh, LH, 0x48) /* type = RX_B LOAD HALFWORD (32<-16) */
V(bc, BC, 0x47) /* type = RX_B BRANCH ON CONDITION */
#define S390_RIE_A_OPCODE_LIST(V) \
V(cgit, CGIT, 0xEC70) /* type = RIE_A COMPARE IMMEDIATE AND TRAP (64<-16) */ \
......@@ -1585,8 +1586,7 @@ typedef uint64_t SixByteInstr;
V(mer, MER, 0x3C) /* type = RR MULTIPLY (short to long HFP) */ \
V(der, DER, 0x3D) /* type = RR DIVIDE (short HFP) */ \
V(aur, AUR, 0x3E) /* type = RR ADD UNNORMALIZED (short HFP) */ \
V(sur, SUR, 0x3F) /* type = RR SUBTRACT UNNORMALIZED (short HFP) */ \
V(sth, STH, 0x40) /* type = RR STORE HALFWORD (16) */
V(sur, SUR, 0x3F) /* type = RR SUBTRACT UNNORMALIZED (short HFP) */
#define S390_RIE_F_OPCODE_LIST(V) \
V(risblg, RISBLG, \
......
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