Commit 11536212 authored by jyan's avatar jyan Committed by Commit bot

s390: Allow larger Operands/Displacements/Offsets in s390

R=joransiu@ca.ibm.com, michael_dawson@ca.ibm.com, mbrandy@us.ibm.com, bjaideep@ca.ibm.com
BUG=

Review-Url: https://codereview.chromium.org/2244373002
Cr-Commit-Position: refs/heads/master@{#38640}
parent 0f40fb20
......@@ -71,12 +71,19 @@ class S390OperandConverter final : public InstructionOperandConverter {
switch (AddressingModeField::decode(instr_->opcode())) {
case kMode_None:
break;
case kMode_MR:
*first_index += 1;
return MemOperand(InputRegister(index + 0), 0);
case kMode_MRI:
*first_index += 2;
return MemOperand(InputRegister(index + 0), InputInt32(index + 1));
case kMode_MRR:
*first_index += 2;
return MemOperand(InputRegister(index + 0), InputRegister(index + 1));
case kMode_MRRI:
*first_index += 3;
return MemOperand(InputRegister(index + 0), InputRegister(index + 1),
InputInt32(index + 2));
}
UNREACHABLE();
return MemOperand(r0);
......
......@@ -166,8 +166,10 @@ namespace compiler {
// MRI = [register + immediate]
// MRR = [register + register]
#define TARGET_ADDRESSING_MODE_LIST(V) \
V(MRI) /* [%r0 + K] */ \
V(MRR) /* [%r0 + %r1] */
V(MR) /* [%r0 ] */ \
V(MRI) /* [%r0 + K] */ \
V(MRR) /* [%r0 + %r1 ] */ \
V(MRRI) /* [%r0 + %r1 + K] */
} // namespace compiler
} // namespace internal
......
......@@ -1920,7 +1920,7 @@ void Assembler::agf(Register r1, const MemOperand& opnd) {
// Add Immediate (64)
void Assembler::agfi(Register r1, const Operand& opnd) {
ril_form(ALFI, r1, opnd);
ril_form(AGFI, r1, opnd);
}
// Add Register-Register (64<-32)
......@@ -2646,6 +2646,11 @@ void Assembler::iill(Register r1, const Operand& opnd) {
ri_form(IILL, r1, opnd);
}
// Load Immediate 32->64
void Assembler::lgfi(Register r1, const Operand& opnd) {
ril_form(LGFI, r1, opnd);
}
// GPR <-> FPR Instructions
// Floating point instructions
......
......@@ -778,6 +778,7 @@ class Assembler : public AssemblerBase {
RI1_FORM(iihh);
RI1_FORM(iihl);
RIL1_FORM(iilf);
RIL1_FORM(lgfi);
RI1_FORM(iilh);
RI1_FORM(iill);
RRE_FORM(lcgr);
......
......@@ -1094,6 +1094,9 @@ bool Decoder::DecodeSixByte(Instruction* instr) {
case IIHF:
Format(instr, "iihf\t'r1,'i7");
break;
case LGFI:
Format(instr, "lgfi\t'r1,'i7");
break;
case IILF:
Format(instr, "iilf\t'r1,'i7");
break;
......
......@@ -7837,9 +7837,10 @@ EVALUATE(LARL) {
}
EVALUATE(LGFI) {
UNIMPLEMENTED();
USE(instr);
return 0;
DCHECK_OPCODE(LGFI);
DECODE_RIL_A_INSTRUCTION(r1, imm);
set_register(r1, static_cast<int64_t>(static_cast<int32_t>(imm)));
return length;
}
EVALUATE(BRASL) {
......@@ -10499,7 +10500,7 @@ EVALUATE(POPCNT_Z) {
}
EVALUATE(LOCGR) {
DCHECK_OPCODE(LOCR);
DCHECK_OPCODE(LOCGR);
DECODE_RRF_C_INSTRUCTION(r1, r2, m3);
if (TestConditionCode(m3)) {
set_register(r1, get_register(r2));
......
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