assembler-x64.cc 112 KB
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// Copyright 2012 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
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#include "src/x64/assembler-x64.h"

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#include <cstring>

#if V8_TARGET_ARCH_X64

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#if V8_LIBC_MSVCRT
#include <intrin.h>  // _xgetbv()
#endif
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#if V8_OS_MACOSX
#include <sys/sysctl.h>
#endif
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#include "src/assembler-inl.h"
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#include "src/base/bits.h"
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#include "src/base/cpu.h"
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#include "src/code-stubs.h"
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#include "src/macro-assembler.h"
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#include "src/v8.h"
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namespace v8 {
namespace internal {
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// -----------------------------------------------------------------------------
// Implementation of CpuFeatures
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namespace {

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#if !V8_LIBC_MSVCRT

V8_INLINE uint64_t _xgetbv(unsigned int xcr) {
  unsigned eax, edx;
  // Check xgetbv; this uses a .byte sequence instead of the instruction
  // directly because older assemblers do not include support for xgetbv and
  // there is no easy way to conditionally compile based on the assembler
  // used.
  __asm__ volatile(".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c"(xcr));
  return static_cast<uint64_t>(eax) | (static_cast<uint64_t>(edx) << 32);
}

#define _XCR_XFEATURE_ENABLED_MASK 0

#endif  // !V8_LIBC_MSVCRT


bool OSHasAVXSupport() {
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#if V8_OS_MACOSX
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  // Mac OS X up to 10.9 has a bug where AVX transitions were indeed being
  // caused by ISRs, so we detect that here and disable AVX in that case.
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  char buffer[128];
  size_t buffer_size = arraysize(buffer);
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  int ctl_name[] = {CTL_KERN, KERN_OSRELEASE};
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  if (sysctl(ctl_name, 2, buffer, &buffer_size, nullptr, 0) != 0) {
    V8_Fatal(__FILE__, __LINE__, "V8 failed to get kernel version");
  }
  // The buffer now contains a string of the form XX.YY.ZZ, where
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  // XX is the major kernel version component.
  char* period_pos = strchr(buffer, '.');
  DCHECK_NOT_NULL(period_pos);
  *period_pos = '\0';
  long kernel_version_major = strtol(buffer, nullptr, 10);  // NOLINT
  if (kernel_version_major <= 13) return false;
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#endif  // V8_OS_MACOSX
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  // Check whether OS claims to support AVX.
  uint64_t feature_mask = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
  return (feature_mask & 0x6) == 0x6;
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}

}  // namespace


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void CpuFeatures::ProbeImpl(bool cross_compile) {
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  base::CPU cpu;
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  CHECK(cpu.has_sse2());  // SSE2 support is mandatory.
  CHECK(cpu.has_cmov());  // CMOV support is mandatory.
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  // Only use statically determined features for cross compile (snapshot).
  if (cross_compile) return;
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  if (cpu.has_sse41() && FLAG_enable_sse4_1) supported_ |= 1u << SSE4_1;
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  if (cpu.has_ssse3() && FLAG_enable_ssse3) supported_ |= 1u << SSSE3;
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  if (cpu.has_sse3() && FLAG_enable_sse3) supported_ |= 1u << SSE3;
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  // SAHF is not generally available in long mode.
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  if (cpu.has_sahf() && FLAG_enable_sahf) supported_ |= 1u << SAHF;
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  if (cpu.has_avx() && FLAG_enable_avx && cpu.has_osxsave() &&
      OSHasAVXSupport()) {
    supported_ |= 1u << AVX;
  }
  if (cpu.has_fma3() && FLAG_enable_fma3 && cpu.has_osxsave() &&
      OSHasAVXSupport()) {
    supported_ |= 1u << FMA3;
  }
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  if (cpu.has_bmi1() && FLAG_enable_bmi1) supported_ |= 1u << BMI1;
  if (cpu.has_bmi2() && FLAG_enable_bmi2) supported_ |= 1u << BMI2;
  if (cpu.has_lzcnt() && FLAG_enable_lzcnt) supported_ |= 1u << LZCNT;
  if (cpu.has_popcnt() && FLAG_enable_popcnt) supported_ |= 1u << POPCNT;
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  if (strcmp(FLAG_mcpu, "auto") == 0) {
    if (cpu.is_atom()) supported_ |= 1u << ATOM;
  } else if (strcmp(FLAG_mcpu, "atom") == 0) {
    supported_ |= 1u << ATOM;
  }
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}

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void CpuFeatures::PrintTarget() { }
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void CpuFeatures::PrintFeatures() {
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  printf(
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      "SSE3=%d SSSE3=%d SSE4_1=%d SAHF=%d AVX=%d FMA3=%d BMI1=%d BMI2=%d "
      "LZCNT=%d "
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      "POPCNT=%d ATOM=%d\n",
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      CpuFeatures::IsSupported(SSE3), CpuFeatures::IsSupported(SSSE3),
      CpuFeatures::IsSupported(SSE4_1), CpuFeatures::IsSupported(SAHF),
      CpuFeatures::IsSupported(AVX), CpuFeatures::IsSupported(FMA3),
      CpuFeatures::IsSupported(BMI1), CpuFeatures::IsSupported(BMI2),
      CpuFeatures::IsSupported(LZCNT), CpuFeatures::IsSupported(POPCNT),
      CpuFeatures::IsSupported(ATOM));
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}
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// -----------------------------------------------------------------------------
// Implementation of RelocInfo

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Address RelocInfo::embedded_address() const { return Memory::Address_at(pc_); }
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uint32_t RelocInfo::embedded_size() const { return Memory::uint32_at(pc_); }
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void RelocInfo::set_embedded_address(Isolate* isolate, Address address,
                                     ICacheFlushMode icache_flush_mode) {
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  Memory::Address_at(pc_) = address;
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  if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
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    Assembler::FlushICache(isolate, pc_, sizeof(Address));
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  }
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}
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void RelocInfo::set_embedded_size(Isolate* isolate, uint32_t size,
                                  ICacheFlushMode icache_flush_mode) {
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  Memory::uint32_at(pc_) = size;
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  if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
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    Assembler::FlushICache(isolate, pc_, sizeof(uint32_t));
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  }
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}

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// -----------------------------------------------------------------------------
// Implementation of Operand

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Operand::Operand(Register base, int32_t disp) : rex_(0) {
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  len_ = 1;
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  if (base == rsp || base == r12) {
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    // SIB byte is needed to encode (rsp + offset) or (r12 + offset).
    set_sib(times_1, rsp, base);
  }

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  if (disp == 0 && base != rbp && base != r13) {
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    set_modrm(0, base);
  } else if (is_int8(disp)) {
    set_modrm(1, base);
    set_disp8(disp);
  } else {
    set_modrm(2, base);
    set_disp32(disp);
  }
}


Operand::Operand(Register base,
                 Register index,
                 ScaleFactor scale,
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                 int32_t disp) : rex_(0) {
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  DCHECK(index != rsp);
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  len_ = 1;
  set_sib(scale, index, base);
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  if (disp == 0 && base != rbp && base != r13) {
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    // This call to set_modrm doesn't overwrite the REX.B (or REX.X) bits
    // possibly set by set_sib.
    set_modrm(0, rsp);
  } else if (is_int8(disp)) {
    set_modrm(1, rsp);
    set_disp8(disp);
  } else {
    set_modrm(2, rsp);
    set_disp32(disp);
  }
}


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Operand::Operand(Register index,
                 ScaleFactor scale,
                 int32_t disp) : rex_(0) {
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  DCHECK(index != rsp);
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  len_ = 1;
  set_modrm(0, rsp);
  set_sib(scale, index, rbp);
  set_disp32(disp);
}


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Operand::Operand(Label* label) : rex_(0), len_(1) {
  DCHECK_NOT_NULL(label);
  set_modrm(0, rbp);
  set_disp64(reinterpret_cast<intptr_t>(label));
}


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Operand::Operand(const Operand& operand, int32_t offset) {
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  DCHECK_GE(operand.len_, 1);
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  // Operand encodes REX ModR/M [SIB] [Disp].
  byte modrm = operand.buf_[0];
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  DCHECK_LT(modrm, 0xC0);  // Disallow mode 3 (register target).
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  bool has_sib = ((modrm & 0x07) == 0x04);
  byte mode = modrm & 0xC0;
  int disp_offset = has_sib ? 2 : 1;
  int base_reg = (has_sib ? operand.buf_[1] : modrm) & 0x07;
  // Mode 0 with rbp/r13 as ModR/M or SIB base register always has a 32-bit
  // displacement.
  bool is_baseless = (mode == 0) && (base_reg == 0x05);  // No base or RIP base.
  int32_t disp_value = 0;
  if (mode == 0x80 || is_baseless) {
    // Mode 2 or mode 0 with rbp/r13 as base: Word displacement.
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    disp_value = *bit_cast<const int32_t*>(&operand.buf_[disp_offset]);
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  } else if (mode == 0x40) {
    // Mode 1: Byte displacement.
    disp_value = static_cast<signed char>(operand.buf_[disp_offset]);
  }

  // Write new operand with same registers, but with modified displacement.
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  DCHECK(offset >= 0 ? disp_value + offset > disp_value
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                     : disp_value + offset < disp_value);  // No overflow.
  disp_value += offset;
  rex_ = operand.rex_;
  if (!is_int8(disp_value) || is_baseless) {
    // Need 32 bits of displacement, mode 2 or mode 1 with register rbp/r13.
    buf_[0] = (modrm & 0x3f) | (is_baseless ? 0x00 : 0x80);
    len_ = disp_offset + 4;
    Memory::int32_at(&buf_[disp_offset]) = disp_value;
  } else if (disp_value != 0 || (base_reg == 0x05)) {
    // Need 8 bits of displacement.
    buf_[0] = (modrm & 0x3f) | 0x40;  // Mode 1.
    len_ = disp_offset + 1;
    buf_[disp_offset] = static_cast<byte>(disp_value);
  } else {
    // Need no displacement.
    buf_[0] = (modrm & 0x3f);  // Mode 0.
    len_ = disp_offset;
  }
  if (has_sib) {
    buf_[1] = operand.buf_[1];
  }
}

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bool Operand::AddressUsesRegister(Register reg) const {
  int code = reg.code();
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  DCHECK_NE(buf_[0] & 0xC0, 0xC0);  // Always a memory operand.
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  // Start with only low three bits of base register. Initial decoding doesn't
  // distinguish on the REX.B bit.
  int base_code = buf_[0] & 0x07;
  if (base_code == rsp.code()) {
    // SIB byte present in buf_[1].
    // Check the index register from the SIB byte + REX.X prefix.
    int index_code = ((buf_[1] >> 3) & 0x07) | ((rex_ & 0x02) << 2);
    // Index code (including REX.X) of 0x04 (rsp) means no index register.
    if (index_code != rsp.code() && index_code == code) return true;
    // Add REX.B to get the full base register code.
    base_code = (buf_[1] & 0x07) | ((rex_ & 0x01) << 3);
    // A base register of 0x05 (rbp) with mod = 0 means no base register.
    if (base_code == rbp.code() && ((buf_[0] & 0xC0) == 0)) return false;
    return code == base_code;
  } else {
    // A base register with low bits of 0x05 (rbp or r13) and mod = 0 means
    // no base register.
    if (base_code == rbp.code() && ((buf_[0] & 0xC0) == 0)) return false;
    base_code |= ((rex_ & 0x01) << 3);
    return code == base_code;
  }
}

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void Assembler::AllocateAndInstallRequestedHeapObjects(Isolate* isolate) {
  for (auto& request : heap_object_requests_) {
    Address pc = buffer_ + request.offset();
    switch (request.kind()) {
      case HeapObjectRequest::kHeapNumber: {
        Handle<HeapNumber> object = isolate->factory()->NewHeapNumber(
            request.heap_number(), IMMUTABLE, TENURED);
        Memory::Object_Handle_at(pc) = object;
        break;
      }
      case HeapObjectRequest::kCodeStub: {
        request.code_stub()->set_isolate(isolate);
        code_targets_[Memory::int32_at(pc)] = request.code_stub()->GetCode();
        break;
      }
    }
  }
}

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// -----------------------------------------------------------------------------
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// Implementation of Assembler.
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Assembler::Assembler(IsolateData isolate_data, void* buffer, int buffer_size)
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    : AssemblerBase(isolate_data, buffer, buffer_size) {
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// Clear the buffer in debug mode unless it was provided by the
// caller in which case we can't be sure it's okay to overwrite
// existing code in it.
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#ifdef DEBUG
  if (own_buffer_) {
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    memset(buffer_, 0xCC, buffer_size_);  // int3
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  }
#endif

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  code_targets_.reserve(100);
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  reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
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}

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void Assembler::GetCode(Isolate* isolate, CodeDesc* desc) {
  // At this point overflow() may be true, but the gap ensures
  // that we are still not overlapping instructions and relocation info.
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  DCHECK(pc_ <= reloc_info_writer.pos());  // No overlap.
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  AllocateAndInstallRequestedHeapObjects(isolate);
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  // Set up code descriptor.
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  desc->buffer = buffer_;
  desc->buffer_size = buffer_size_;
  desc->instr_size = pc_offset();
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  DCHECK_GT(desc->instr_size, 0);  // Zero-size code objects upset the system.
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  desc->reloc_size =
      static_cast<int>((buffer_ + buffer_size_) - reloc_info_writer.pos());
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  desc->origin = this;
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  desc->constant_pool_size = 0;
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  desc->unwinding_info_size = 0;
  desc->unwinding_info = nullptr;
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  // Collection stage
  auto jump_opt = jump_optimization_info();
  if (jump_opt && jump_opt->is_collecting()) {
    auto& bitmap = jump_opt->farjmp_bitmap();
    int num = static_cast<int>(farjmp_positions_.size());
    if (num && bitmap.empty()) {
      bool can_opt = false;

      bitmap.resize((num + 31) / 32, 0);
      for (int i = 0; i < num; i++) {
        int disp_pos = farjmp_positions_[i];
        int disp = long_at(disp_pos);
        if (is_int8(disp)) {
          bitmap[i / 32] |= 1 << (i & 31);
          can_opt = true;
        }
      }
      if (can_opt) {
        jump_opt->set_optimizable();
      }
    }
  }
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}


void Assembler::Align(int m) {
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  DCHECK(base::bits::IsPowerOfTwo(m));
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  int delta = (m - (pc_offset() & (m - 1))) & (m - 1);
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  Nop(delta);
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}

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void Assembler::CodeTargetAlign() {
  Align(16);  // Preferred alignment of jump targets on x64.
}


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bool Assembler::IsNop(Address addr) {
  Address a = addr;
  while (*a == 0x66) a++;
  if (*a == 0x90) return true;
  if (a[0] == 0xf && a[1] == 0x1f) return true;
  return false;
}


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void Assembler::bind_to(Label* L, int pos) {
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  DCHECK(!L->is_bound());  // Label may only be bound once.
  DCHECK(0 <= pos && pos <= pc_offset());  // Position must be valid.
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  if (L->is_linked()) {
    int current = L->pos();
    int next = long_at(current);
    while (next != current) {
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      if (current >= 4 && long_at(current - 4) == 0) {
        // Absolute address.
        intptr_t imm64 = reinterpret_cast<intptr_t>(buffer_ + pos);
        *reinterpret_cast<intptr_t*>(addr_at(current - 4)) = imm64;
        internal_reference_positions_.push_back(current - 4);
      } else {
        // Relative address, relative to point after address.
        int imm32 = pos - (current + sizeof(int32_t));
        long_at_put(current, imm32);
      }
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      current = next;
      next = long_at(next);
    }
    // Fix up last fixup on linked list.
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    if (current >= 4 && long_at(current - 4) == 0) {
      // Absolute address.
      intptr_t imm64 = reinterpret_cast<intptr_t>(buffer_ + pos);
      *reinterpret_cast<intptr_t*>(addr_at(current - 4)) = imm64;
      internal_reference_positions_.push_back(current - 4);
    } else {
      // Relative address, relative to point after address.
      int imm32 = pos - (current + sizeof(int32_t));
      long_at_put(current, imm32);
    }
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  }
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  while (L->is_near_linked()) {
    int fixup_pos = L->near_link_pos();
    int offset_to_next =
        static_cast<int>(*reinterpret_cast<int8_t*>(addr_at(fixup_pos)));
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    DCHECK_LE(offset_to_next, 0);
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    int disp = pos - (fixup_pos + sizeof(int8_t));
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    CHECK(is_int8(disp));
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    set_byte_at(fixup_pos, disp);
    if (offset_to_next < 0) {
      L->link_to(fixup_pos + offset_to_next, Label::kNear);
    } else {
      L->UnuseNear();
    }
  }
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  // Optimization stage
  auto jump_opt = jump_optimization_info();
  if (jump_opt && jump_opt->is_optimizing()) {
    auto it = label_farjmp_maps_.find(L);
    if (it != label_farjmp_maps_.end()) {
      auto& pos_vector = it->second;
      for (auto fixup_pos : pos_vector) {
        int disp = pos - (fixup_pos + sizeof(int8_t));
        CHECK(is_int8(disp));
        set_byte_at(fixup_pos, disp);
      }
      label_farjmp_maps_.erase(it);
    }
  }
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  L->bind_to(pos);
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}

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void Assembler::bind(Label* L) {
  bind_to(L, pc_offset());
}

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void Assembler::record_farjmp_position(Label* L, int pos) {
  auto& pos_vector = label_farjmp_maps_[L];
  pos_vector.push_back(pos);
}

bool Assembler::is_optimizable_farjmp(int idx) {
  if (predictable_code_size()) return false;

  auto jump_opt = jump_optimization_info();
  CHECK(jump_opt->is_optimizing());

  auto& bitmap = jump_opt->farjmp_bitmap();
  CHECK(idx < static_cast<int>(bitmap.size() * 32));
  return !!(bitmap[idx / 32] & (1 << (idx & 31)));
}
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void Assembler::GrowBuffer() {
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  DCHECK(buffer_overflow());
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  if (!own_buffer_) FATAL("external code buffer is too small");
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  // Compute new buffer size.
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  CodeDesc desc;  // the new buffer
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  desc.buffer_size = 2 * buffer_size_;

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  // Some internal data structures overflow for very large buffers,
  // they must ensure that kMaximalBufferSize is not too large.
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  if (desc.buffer_size > kMaximalBufferSize) {
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    V8::FatalProcessOutOfMemory("Assembler::GrowBuffer");
  }
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  // Set up new buffer.
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  desc.buffer = NewArray<byte>(desc.buffer_size);
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  desc.origin = this;
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  desc.instr_size = pc_offset();
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  desc.reloc_size =
      static_cast<int>((buffer_ + buffer_size_) - (reloc_info_writer.pos()));
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  // Clear the buffer in debug mode. Use 'int3' instructions to make
  // sure to get into problems if we ever run uninitialized code.
#ifdef DEBUG
  memset(desc.buffer, 0xCC, desc.buffer_size);
#endif
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  // Copy the data.
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  intptr_t pc_delta = desc.buffer - buffer_;
  intptr_t rc_delta = (desc.buffer + desc.buffer_size) -
      (buffer_ + buffer_size_);
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  MemMove(desc.buffer, buffer_, desc.instr_size);
  MemMove(rc_delta + reloc_info_writer.pos(), reloc_info_writer.pos(),
          desc.reloc_size);
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  // Switch buffers.
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  DeleteArray(buffer_);
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  buffer_ = desc.buffer;
  buffer_size_ = desc.buffer_size;
  pc_ += pc_delta;
  reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
                               reloc_info_writer.last_pc() + pc_delta);

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  // Relocate internal references.
  for (auto pos : internal_reference_positions_) {
    intptr_t* p = reinterpret_cast<intptr_t*>(buffer_ + pos);
    *p += pc_delta;
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  }
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  DCHECK(!buffer_overflow());
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}


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void Assembler::emit_operand(int code, const Operand& adr) {
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  DCHECK(is_uint3(code));
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  const unsigned length = adr.len_;
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  DCHECK_GT(length, 0);
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  // Emit updated ModR/M byte containing the given register.
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  DCHECK_EQ(adr.buf_[0] & 0x38, 0);
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  *pc_++ = adr.buf_[0] | code << 3;

  // Recognize RIP relative addressing.
  if (adr.buf_[0] == 5) {
    DCHECK_EQ(9u, length);
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    Label* label = *bit_cast<Label* const*>(&adr.buf_[1]);
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    if (label->is_bound()) {
      int offset = label->pos() - pc_offset() - sizeof(int32_t);
      DCHECK_GE(0, offset);
      emitl(offset);
    } else if (label->is_linked()) {
      emitl(label->pos());
      label->link_to(pc_offset() - sizeof(int32_t));
    } else {
      DCHECK(label->is_unused());
      int32_t current = pc_offset();
      emitl(current);
      label->link_to(current);
    }
  } else {
    // Emit the rest of the encoded operand.
    for (unsigned i = 1; i < length; i++) *pc_++ = adr.buf_[i];
  }
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}


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// Assembler Instruction implementations.
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void Assembler::arithmetic_op(byte opcode,
                              Register reg,
                              const Operand& op,
                              int size) {
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  EnsureSpace ensure_space(this);
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  emit_rex(reg, op, size);
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  emit(opcode);
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  emit_operand(reg, op);
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}


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void Assembler::arithmetic_op(byte opcode,
                              Register reg,
                              Register rm_reg,
                              int size) {
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  EnsureSpace ensure_space(this);
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  DCHECK_EQ(opcode & 0xC6, 2);
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  if (rm_reg.low_bits() == 4)  {  // Forces SIB byte.
    // Swap reg and rm_reg and change opcode operand order.
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    emit_rex(rm_reg, reg, size);
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    emit(opcode ^ 0x02);
    emit_modrm(rm_reg, reg);
  } else {
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    emit_rex(reg, rm_reg, size);
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    emit(opcode);
    emit_modrm(reg, rm_reg);
  }
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}

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void Assembler::arithmetic_op_16(byte opcode, Register reg, Register rm_reg) {
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  EnsureSpace ensure_space(this);
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  DCHECK_EQ(opcode & 0xC6, 2);
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  if (rm_reg.low_bits() == 4) {  // Forces SIB byte.
    // Swap reg and rm_reg and change opcode operand order.
    emit(0x66);
    emit_optional_rex_32(rm_reg, reg);
    emit(opcode ^ 0x02);
    emit_modrm(rm_reg, reg);
  } else {
    emit(0x66);
    emit_optional_rex_32(reg, rm_reg);
    emit(opcode);
    emit_modrm(reg, rm_reg);
  }
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}


void Assembler::arithmetic_op_16(byte opcode,
                                 Register reg,
                                 const Operand& rm_reg) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(reg, rm_reg);
  emit(opcode);
  emit_operand(reg, rm_reg);
}


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void Assembler::arithmetic_op_8(byte opcode, Register reg, const Operand& op) {
  EnsureSpace ensure_space(this);
  if (!reg.is_byte_register()) {
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    emit_rex_32(reg, op);
  } else {
    emit_optional_rex_32(reg, op);
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  }
  emit(opcode);
  emit_operand(reg, op);
}


void Assembler::arithmetic_op_8(byte opcode, Register reg, Register rm_reg) {
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  EnsureSpace ensure_space(this);
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  DCHECK_EQ(opcode & 0xC6, 2);
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  if (rm_reg.low_bits() == 4)  {  // Forces SIB byte.
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    // Swap reg and rm_reg and change opcode operand order.
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    if (!rm_reg.is_byte_register() || !reg.is_byte_register()) {
      // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
      emit_rex_32(rm_reg, reg);
    }
    emit(opcode ^ 0x02);
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    emit_modrm(rm_reg, reg);
  } else {
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    if (!reg.is_byte_register() || !rm_reg.is_byte_register()) {
      // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
      emit_rex_32(reg, rm_reg);
    }
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    emit(opcode);
    emit_modrm(reg, rm_reg);
  }
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}


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void Assembler::immediate_arithmetic_op(byte subcode,
                                        Register dst,
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                                        Immediate src,
                                        int size) {
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  EnsureSpace ensure_space(this);
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  emit_rex(dst, size);
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  if (is_int8(src.value_) && RelocInfo::IsNone(src.rmode_)) {
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    emit(0x83);
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    emit_modrm(subcode, dst);
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    emit(src.value_);
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  } else if (dst == rax) {
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    emit(0x05 | (subcode << 3));
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    emit(src);
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  } else {
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    emit(0x81);
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    emit_modrm(subcode, dst);
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    emit(src);
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  }
}

void Assembler::immediate_arithmetic_op(byte subcode,
                                        const Operand& dst,
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                                        Immediate src,
                                        int size) {
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  EnsureSpace ensure_space(this);
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  emit_rex(dst, size);
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  if (is_int8(src.value_) && RelocInfo::IsNone(src.rmode_)) {
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    emit(0x83);
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    emit_operand(subcode, dst);
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    emit(src.value_);
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  } else {
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    emit(0x81);
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    emit_operand(subcode, dst);
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    emit(src);
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  }
}

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void Assembler::immediate_arithmetic_op_16(byte subcode,
                                           Register dst,
                                           Immediate src) {
  EnsureSpace ensure_space(this);
  emit(0x66);  // Operand size override prefix.
  emit_optional_rex_32(dst);
  if (is_int8(src.value_)) {
    emit(0x83);
    emit_modrm(subcode, dst);
    emit(src.value_);
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  } else if (dst == rax) {
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    emit(0x05 | (subcode << 3));
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    emitw(src.value_);
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  } else {
    emit(0x81);
    emit_modrm(subcode, dst);
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    emitw(src.value_);
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  }
}


void Assembler::immediate_arithmetic_op_16(byte subcode,
                                           const Operand& dst,
                                           Immediate src) {
  EnsureSpace ensure_space(this);
  emit(0x66);  // Operand size override prefix.
  emit_optional_rex_32(dst);
  if (is_int8(src.value_)) {
    emit(0x83);
    emit_operand(subcode, dst);
    emit(src.value_);
  } else {
    emit(0x81);
    emit_operand(subcode, dst);
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    emitw(src.value_);
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  }
}


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void Assembler::immediate_arithmetic_op_8(byte subcode,
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                                          const Operand& dst,
                                          Immediate src) {
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  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst);
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  DCHECK(is_int8(src.value_) || is_uint8(src.value_));
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  emit(0x80);
  emit_operand(subcode, dst);
  emit(src.value_);
}


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void Assembler::immediate_arithmetic_op_8(byte subcode,
                                          Register dst,
                                          Immediate src) {
  EnsureSpace ensure_space(this);
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  if (!dst.is_byte_register()) {
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    // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
    emit_rex_32(dst);
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  }
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  DCHECK(is_int8(src.value_) || is_uint8(src.value_));
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  emit(0x80);
  emit_modrm(subcode, dst);
  emit(src.value_);
}


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void Assembler::shift(Register dst,
                      Immediate shift_amount,
                      int subcode,
                      int size) {
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  EnsureSpace ensure_space(this);
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  DCHECK(size == kInt64Size ? is_uint6(shift_amount.value_)
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                            : is_uint5(shift_amount.value_));
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  if (shift_amount.value_ == 1) {
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    emit_rex(dst, size);
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    emit(0xD1);
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    emit_modrm(subcode, dst);
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  } else {
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    emit_rex(dst, size);
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    emit(0xC1);
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    emit_modrm(subcode, dst);
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    emit(shift_amount.value_);
  }
}


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void Assembler::shift(Operand dst, Immediate shift_amount, int subcode,
                      int size) {
  EnsureSpace ensure_space(this);
  DCHECK(size == kInt64Size ? is_uint6(shift_amount.value_)
                            : is_uint5(shift_amount.value_));
  if (shift_amount.value_ == 1) {
    emit_rex(dst, size);
    emit(0xD1);
    emit_operand(subcode, dst);
  } else {
    emit_rex(dst, size);
    emit(0xC1);
    emit_operand(subcode, dst);
    emit(shift_amount.value_);
  }
}


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void Assembler::shift(Register dst, int subcode, int size) {
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  EnsureSpace ensure_space(this);
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  emit_rex(dst, size);
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  emit(0xD3);
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  emit_modrm(subcode, dst);
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}


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void Assembler::shift(Operand dst, int subcode, int size) {
  EnsureSpace ensure_space(this);
  emit_rex(dst, size);
  emit(0xD3);
  emit_operand(subcode, dst);
}


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void Assembler::bt(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
  emit_rex_64(src, dst);
  emit(0x0F);
  emit(0xA3);
  emit_operand(src, dst);
}


void Assembler::bts(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
  emit_rex_64(src, dst);
  emit(0x0F);
  emit(0xAB);
  emit_operand(src, dst);
}


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void Assembler::bsrl(Register dst, Register src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xBD);
  emit_modrm(dst, src);
}


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void Assembler::bsrl(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xBD);
  emit_operand(dst, src);
}


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void Assembler::bsrq(Register dst, Register src) {
  EnsureSpace ensure_space(this);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0xBD);
  emit_modrm(dst, src);
}


void Assembler::bsrq(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0xBD);
  emit_operand(dst, src);
}


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void Assembler::bsfl(Register dst, Register src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xBC);
  emit_modrm(dst, src);
}


void Assembler::bsfl(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xBC);
  emit_operand(dst, src);
}


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void Assembler::bsfq(Register dst, Register src) {
  EnsureSpace ensure_space(this);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0xBC);
  emit_modrm(dst, src);
}


void Assembler::bsfq(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0xBC);
  emit_operand(dst, src);
}

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void Assembler::pshufw(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x70);
  emit(0xC0 | (dst.low_bits() << 3) | src.low_bits());
  emit(shuffle);
}

void Assembler::pshufw(XMMRegister dst, const Operand& src, uint8_t shuffle) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x70);
  emit_operand(dst.code(), src);
  emit(shuffle);
}
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void Assembler::call(Label* L) {
  EnsureSpace ensure_space(this);
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  // 1110 1000 #32-bit disp.
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  emit(0xE8);
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  if (L->is_bound()) {
    int offset = L->pos() - pc_offset() - sizeof(int32_t);
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    DCHECK_LE(offset, 0);
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    emitl(offset);
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  } else if (L->is_linked()) {
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    emitl(L->pos());
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    L->link_to(pc_offset() - sizeof(int32_t));
  } else {
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    DCHECK(L->is_unused());
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    int32_t current = pc_offset();
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    emitl(current);
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    L->link_to(current);
  }
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}


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void Assembler::call(Address entry, RelocInfo::Mode rmode) {
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  DCHECK(RelocInfo::IsRuntimeEntry(rmode));
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  EnsureSpace ensure_space(this);
  // 1110 1000 #32-bit disp.
  emit(0xE8);
  emit_runtime_entry(entry, rmode);
}

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void Assembler::call(CodeStub* stub) {
  EnsureSpace ensure_space(this);
  // 1110 1000 #32-bit disp.
  emit(0xE8);
  RequestHeapObject(HeapObjectRequest(stub));
  emit_code_target(Handle<Code>(), RelocInfo::CODE_TARGET);
}

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void Assembler::call(Handle<Code> target, RelocInfo::Mode rmode) {
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  EnsureSpace ensure_space(this);
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  // 1110 1000 #32-bit disp.
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  emit(0xE8);
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  emit_code_target(target, rmode);
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}


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void Assembler::call(Register adr) {
  EnsureSpace ensure_space(this);
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  // Opcode: FF /2 r64.
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  emit_optional_rex_32(adr);
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  emit(0xFF);
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  emit_modrm(0x2, adr);
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}

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void Assembler::call(const Operand& op) {
  EnsureSpace ensure_space(this);
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  // Opcode: FF /2 m64.
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  emit_optional_rex_32(op);
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  emit(0xFF);
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  emit_operand(0x2, op);
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}


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// Calls directly to the given address using a relative offset.
// Should only ever be used in Code objects for calls within the
// same Code object. Should not be used when generating new code (use labels),
// but only when patching existing code.
void Assembler::call(Address target) {
  EnsureSpace ensure_space(this);
  // 1110 1000 #32-bit disp.
  emit(0xE8);
  Address source = pc_ + 4;
  intptr_t displacement = target - source;
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  DCHECK(is_int32(displacement));
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  emitl(static_cast<int32_t>(displacement));
}


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void Assembler::clc() {
  EnsureSpace ensure_space(this);
  emit(0xF8);
}

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void Assembler::cld() {
  EnsureSpace ensure_space(this);
  emit(0xFC);
}

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void Assembler::cdq() {
  EnsureSpace ensure_space(this);
  emit(0x99);
}


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void Assembler::cmovq(Condition cc, Register dst, Register src) {
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  if (cc == always) {
    movq(dst, src);
  } else if (cc == never) {
    return;
  }
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  // No need to check CpuInfo for CMOV support, it's a required part of the
  // 64-bit architecture.
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  DCHECK_GE(cc, 0);  // Use mov for unconditional moves.
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  EnsureSpace ensure_space(this);
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  // Opcode: REX.W 0f 40 + cc /r.
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  emit_rex_64(dst, src);
  emit(0x0f);
  emit(0x40 + cc);
  emit_modrm(dst, src);
}


void Assembler::cmovq(Condition cc, Register dst, const Operand& src) {
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  if (cc == always) {
    movq(dst, src);
  } else if (cc == never) {
    return;
  }
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  DCHECK_GE(cc, 0);
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  EnsureSpace ensure_space(this);
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  // Opcode: REX.W 0f 40 + cc /r.
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  emit_rex_64(dst, src);
  emit(0x0f);
  emit(0x40 + cc);
  emit_operand(dst, src);
}


void Assembler::cmovl(Condition cc, Register dst, Register src) {
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  if (cc == always) {
    movl(dst, src);
  } else if (cc == never) {
    return;
  }
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  DCHECK_GE(cc, 0);
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  EnsureSpace ensure_space(this);
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  // Opcode: 0f 40 + cc /r.
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  emit_optional_rex_32(dst, src);
  emit(0x0f);
  emit(0x40 + cc);
  emit_modrm(dst, src);
}


void Assembler::cmovl(Condition cc, Register dst, const Operand& src) {
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  if (cc == always) {
    movl(dst, src);
  } else if (cc == never) {
    return;
  }
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  DCHECK_GE(cc, 0);
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  EnsureSpace ensure_space(this);
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  // Opcode: 0f 40 + cc /r.
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  emit_optional_rex_32(dst, src);
  emit(0x0f);
  emit(0x40 + cc);
  emit_operand(dst, src);
}


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void Assembler::cmpb_al(Immediate imm8) {
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  DCHECK(is_int8(imm8.value_) || is_uint8(imm8.value_));
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  EnsureSpace ensure_space(this);
  emit(0x3c);
  emit(imm8.value_);
}

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void Assembler::lock() {
  EnsureSpace ensure_space(this);
  emit(0xf0);
}

void Assembler::cmpxchgb(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
  if (!src.is_byte_register()) {
    // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
    emit_rex_32(src, dst);
  } else {
    emit_optional_rex_32(src, dst);
  }
  emit(0x0f);
  emit(0xb0);
  emit_operand(src, dst);
}

void Assembler::cmpxchgw(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(src, dst);
  emit(0x0f);
  emit(0xb1);
  emit_operand(src, dst);
}

void Assembler::emit_cmpxchg(const Operand& dst, Register src, int size) {
  EnsureSpace ensure_space(this);
  emit_rex(src, dst, size);
  emit(0x0f);
  emit(0xb1);
  emit_operand(src, dst);
}
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void Assembler::cpuid() {
  EnsureSpace ensure_space(this);
  emit(0x0F);
  emit(0xA2);
}


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void Assembler::cqo() {
  EnsureSpace ensure_space(this);
  emit_rex_64();
  emit(0x99);
}


1129
void Assembler::emit_dec(Register dst, int size) {
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  EnsureSpace ensure_space(this);
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  emit_rex(dst, size);
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  emit(0xFF);
  emit_modrm(0x1, dst);
}


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void Assembler::emit_dec(const Operand& dst, int size) {
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  EnsureSpace ensure_space(this);
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  emit_rex(dst, size);
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  emit(0xFF);
  emit_operand(1, dst);
}


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void Assembler::decb(Register dst) {
  EnsureSpace ensure_space(this);
1147
  if (!dst.is_byte_register()) {
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    // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
    emit_rex_32(dst);
  }
  emit(0xFE);
  emit_modrm(0x1, dst);
}


void Assembler::decb(const Operand& dst) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst);
  emit(0xFE);
  emit_operand(1, dst);
}


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void Assembler::enter(Immediate size) {
  EnsureSpace ensure_space(this);
  emit(0xC8);
  emitw(size.value_);  // 16 bit operand, always.
  emit(0);
}


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void Assembler::hlt() {
  EnsureSpace ensure_space(this);
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  emit(0xF4);
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}


1178
void Assembler::emit_idiv(Register src, int size) {
1179
  EnsureSpace ensure_space(this);
1180
  emit_rex(src, size);
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  emit(0xF7);
  emit_modrm(0x7, src);
}


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void Assembler::emit_div(Register src, int size) {
  EnsureSpace ensure_space(this);
  emit_rex(src, size);
  emit(0xF7);
  emit_modrm(0x6, src);
}


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void Assembler::emit_imul(Register src, int size) {
1195
  EnsureSpace ensure_space(this);
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  emit_rex(src, size);
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  emit(0xF7);
  emit_modrm(0x5, src);
}


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void Assembler::emit_imul(const Operand& src, int size) {
  EnsureSpace ensure_space(this);
  emit_rex(src, size);
  emit(0xF7);
  emit_operand(0x5, src);
}


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void Assembler::emit_imul(Register dst, Register src, int size) {
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  EnsureSpace ensure_space(this);
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  emit_rex(dst, src, size);
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  emit(0x0F);
  emit(0xAF);
  emit_modrm(dst, src);
}


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void Assembler::emit_imul(Register dst, const Operand& src, int size) {
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  EnsureSpace ensure_space(this);
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  emit_rex(dst, src, size);
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  emit(0x0F);
  emit(0xAF);
  emit_operand(dst, src);
}


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void Assembler::emit_imul(Register dst, Register src, Immediate imm, int size) {
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  EnsureSpace ensure_space(this);
1230
  emit_rex(dst, src, size);
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  if (is_int8(imm.value_)) {
    emit(0x6B);
    emit_modrm(dst, src);
    emit(imm.value_);
  } else {
    emit(0x69);
    emit_modrm(dst, src);
    emitl(imm.value_);
  }
}


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void Assembler::emit_imul(Register dst, const Operand& src, Immediate imm,
                          int size) {
  EnsureSpace ensure_space(this);
  emit_rex(dst, src, size);
  if (is_int8(imm.value_)) {
    emit(0x6B);
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    emit_operand(dst, src);
    emit(imm.value_);
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  } else {
    emit(0x69);
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    emit_operand(dst, src);
    emitl(imm.value_);
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  }
}


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void Assembler::emit_inc(Register dst, int size) {
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  EnsureSpace ensure_space(this);
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  emit_rex(dst, size);
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  emit(0xFF);
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  emit_modrm(0x0, dst);
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}


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void Assembler::emit_inc(const Operand& dst, int size) {
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  EnsureSpace ensure_space(this);
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  emit_rex(dst, size);
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  emit(0xFF);
  emit_operand(0, dst);
}


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void Assembler::int3() {
  EnsureSpace ensure_space(this);
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  emit(0xCC);
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}


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void Assembler::j(Condition cc, Label* L, Label::Distance distance) {
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  if (cc == always) {
    jmp(L);
    return;
  } else if (cc == never) {
    return;
  }
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  EnsureSpace ensure_space(this);
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  DCHECK(is_uint4(cc));
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  if (L->is_bound()) {
    const int short_size = 2;
    const int long_size  = 6;
    int offs = L->pos() - pc_offset();
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    DCHECK_LE(offs, 0);
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    // Determine whether we can use 1-byte offsets for backwards branches,
    // which have a max range of 128 bytes.

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    // We also need to check predictable_code_size() flag here, because on x64,
    // when the full code generator recompiles code for debugging, some places
    // need to be padded out to a certain size. The debugger is keeping track of
    // how often it did this so that it can adjust return addresses on the
    // stack, but if the size of jump instructions can also change, that's not
    // enough and the calculated offsets would be incorrect.
    if (is_int8(offs - short_size) && !predictable_code_size()) {
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      // 0111 tttn #8-bit disp.
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      emit(0x70 | cc);
      emit((offs - short_size) & 0xFF);
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    } else {
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      // 0000 1111 1000 tttn #32-bit disp.
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      emit(0x0F);
      emit(0x80 | cc);
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      emitl(offs - long_size);
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    }
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  } else if (distance == Label::kNear) {
    // 0111 tttn #8-bit disp
    emit(0x70 | cc);
    byte disp = 0x00;
    if (L->is_near_linked()) {
      int offset = L->near_link_pos() - pc_offset();
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      DCHECK(is_int8(offset));
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      disp = static_cast<byte>(offset & 0xFF);
    }
    L->link_to(pc_offset(), Label::kNear);
    emit(disp);
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  } else {
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    auto jump_opt = jump_optimization_info();
    if (V8_UNLIKELY(jump_opt)) {
      if (jump_opt->is_optimizing() && is_optimizable_farjmp(farjmp_num_++)) {
        // 0111 tttn #8-bit disp
        emit(0x70 | cc);
        record_farjmp_position(L, pc_offset());
        emit(0);
        return;
      }
      if (jump_opt->is_collecting()) {
        farjmp_positions_.push_back(pc_offset() + 2);
      }
    }
    if (L->is_linked()) {
      // 0000 1111 1000 tttn #32-bit disp.
      emit(0x0F);
      emit(0x80 | cc);
      emitl(L->pos());
      L->link_to(pc_offset() - sizeof(int32_t));
    } else {
      DCHECK(L->is_unused());
      emit(0x0F);
      emit(0x80 | cc);
      int32_t current = pc_offset();
      emitl(current);
      L->link_to(current);
    }
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  }
}


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void Assembler::j(Condition cc, Address entry, RelocInfo::Mode rmode) {
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  DCHECK(RelocInfo::IsRuntimeEntry(rmode));
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  EnsureSpace ensure_space(this);
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  DCHECK(is_uint4(cc));
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  emit(0x0F);
  emit(0x80 | cc);
  emit_runtime_entry(entry, rmode);
}


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void Assembler::j(Condition cc,
                  Handle<Code> target,
                  RelocInfo::Mode rmode) {
  EnsureSpace ensure_space(this);
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  DCHECK(is_uint4(cc));
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  // 0000 1111 1000 tttn #32-bit disp.
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  emit(0x0F);
  emit(0x80 | cc);
  emit_code_target(target, rmode);
}


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void Assembler::jmp(Label* L, Label::Distance distance) {
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  EnsureSpace ensure_space(this);
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  const int short_size = sizeof(int8_t);
  const int long_size = sizeof(int32_t);
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  if (L->is_bound()) {
    int offs = L->pos() - pc_offset() - 1;
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    DCHECK_LE(offs, 0);
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    if (is_int8(offs - short_size) && !predictable_code_size()) {
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      // 1110 1011 #8-bit disp.
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      emit(0xEB);
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      emit((offs - short_size) & 0xFF);
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    } else {
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      // 1110 1001 #32-bit disp.
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      emit(0xE9);
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      emitl(offs - long_size);
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    }
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  } else if (distance == Label::kNear) {
    emit(0xEB);
    byte disp = 0x00;
    if (L->is_near_linked()) {
      int offset = L->near_link_pos() - pc_offset();
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      DCHECK(is_int8(offset));
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      disp = static_cast<byte>(offset & 0xFF);
    }
    L->link_to(pc_offset(), Label::kNear);
    emit(disp);
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  } else {
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    auto jump_opt = jump_optimization_info();
    if (V8_UNLIKELY(jump_opt)) {
      if (jump_opt->is_optimizing() && is_optimizable_farjmp(farjmp_num_++)) {
        emit(0xEB);
        record_farjmp_position(L, pc_offset());
        emit(0);
        return;
      }
      if (jump_opt->is_collecting()) {
        farjmp_positions_.push_back(pc_offset() + 1);
      }
    }
    if (L->is_linked()) {
      // 1110 1001 #32-bit disp.
      emit(0xE9);
      emitl(L->pos());
      L->link_to(pc_offset() - long_size);
    } else {
      // 1110 1001 #32-bit disp.
      DCHECK(L->is_unused());
      emit(0xE9);
      int32_t current = pc_offset();
      emitl(current);
      L->link_to(current);
    }
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  }
}


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void Assembler::jmp(Handle<Code> target, RelocInfo::Mode rmode) {
  EnsureSpace ensure_space(this);
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  // 1110 1001 #32-bit disp.
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  emit(0xE9);
  emit_code_target(target, rmode);
}


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void Assembler::jmp(Register target) {
  EnsureSpace ensure_space(this);
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  // Opcode FF/4 r64.
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  emit_optional_rex_32(target);
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  emit(0xFF);
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  emit_modrm(0x4, target);
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}


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void Assembler::jmp(const Operand& src) {
  EnsureSpace ensure_space(this);
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  // Opcode FF/4 m64.
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  emit_optional_rex_32(src);
  emit(0xFF);
  emit_operand(0x4, src);
}


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void Assembler::emit_lea(Register dst, const Operand& src, int size) {
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  EnsureSpace ensure_space(this);
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  emit_rex(dst, src, size);
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  emit(0x8D);
  emit_operand(dst, src);
}


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void Assembler::load_rax(void* value, RelocInfo::Mode mode) {
  EnsureSpace ensure_space(this);
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  if (kPointerSize == kInt64Size) {
    emit(0x48);  // REX.W
    emit(0xA1);
    emitp(value, mode);
  } else {
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    DCHECK_EQ(kPointerSize, kInt32Size);
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    emit(0xA1);
    emitp(value, mode);
    // In 64-bit mode, need to zero extend the operand to 8 bytes.
    // See 2.2.1.4 in Intel64 and IA32 Architectures Software
    // Developer's Manual Volume 2.
    emitl(0);
  }
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}


void Assembler::load_rax(ExternalReference ref) {
  load_rax(ref.address(), RelocInfo::EXTERNAL_REFERENCE);
}


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void Assembler::leave() {
  EnsureSpace ensure_space(this);
  emit(0xC9);
}


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void Assembler::movb(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
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  if (!dst.is_byte_register()) {
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    // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
    emit_rex_32(dst, src);
  } else {
    emit_optional_rex_32(dst, src);
  }
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  emit(0x8A);
  emit_operand(dst, src);
}

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void Assembler::movb(Register dst, Immediate imm) {
  EnsureSpace ensure_space(this);
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  if (!dst.is_byte_register()) {
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    // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
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    emit_rex_32(dst);
  }
  emit(0xB0 + dst.low_bits());
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  emit(imm.value_);
}

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void Assembler::movb(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
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  if (!src.is_byte_register()) {
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    // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
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    emit_rex_32(src, dst);
  } else {
    emit_optional_rex_32(src, dst);
  }
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  emit(0x88);
  emit_operand(src, dst);
}

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void Assembler::movb(const Operand& dst, Immediate imm) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst);
  emit(0xC6);
  emit_operand(0x0, dst);
  emit(static_cast<byte>(imm.value_));
}


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void Assembler::movw(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x8B);
  emit_operand(dst, src);
}


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void Assembler::movw(const Operand& dst, Register src) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(src, dst);
  emit(0x89);
  emit_operand(src, dst);
}

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void Assembler::movw(const Operand& dst, Immediate imm) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst);
  emit(0xC7);
  emit_operand(0x0, dst);
  emit(static_cast<byte>(imm.value_ & 0xff));
  emit(static_cast<byte>(imm.value_ >> 8));
}


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void Assembler::emit_mov(Register dst, const Operand& src, int size) {
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  EnsureSpace ensure_space(this);
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  emit_rex(dst, src, size);
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  emit(0x8B);
  emit_operand(dst, src);
}


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void Assembler::emit_mov(Register dst, Register src, int size) {
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  EnsureSpace ensure_space(this);
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  if (src.low_bits() == 4) {
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    emit_rex(src, dst, size);
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    emit(0x89);
    emit_modrm(src, dst);
  } else {
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    emit_rex(dst, src, size);
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    emit(0x8B);
    emit_modrm(dst, src);
  }
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}


1595
void Assembler::emit_mov(const Operand& dst, Register src, int size) {
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  EnsureSpace ensure_space(this);
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  emit_rex(src, dst, size);
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  emit(0x89);
  emit_operand(src, dst);
}


1603
void Assembler::emit_mov(Register dst, Immediate value, int size) {
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  EnsureSpace ensure_space(this);
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  emit_rex(dst, size);
  if (size == kInt64Size) {
    emit(0xC7);
    emit_modrm(0x0, dst);
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  } else {
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    DCHECK_EQ(size, kInt32Size);
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    emit(0xB8 + dst.low_bits());
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  }
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  emit(value);
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}

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void Assembler::emit_mov(const Operand& dst, Immediate value, int size) {
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  EnsureSpace ensure_space(this);
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  emit_rex(dst, size);
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  emit(0xC7);
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  emit_operand(0x0, dst);
  emit(value);
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}


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void Assembler::movp(Register dst, void* value, RelocInfo::Mode rmode) {
  EnsureSpace ensure_space(this);
  emit_rex(dst, kPointerSize);
  emit(0xB8 | dst.low_bits());
  emitp(value, rmode);
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}

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void Assembler::movp_heap_number(Register dst, double value) {
  EnsureSpace ensure_space(this);
  emit_rex(dst, kPointerSize);
  emit(0xB8 | dst.low_bits());
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  RequestHeapObject(HeapObjectRequest(value));
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  emitp(nullptr, RelocInfo::EMBEDDED_OBJECT);
}

1641
void Assembler::movq(Register dst, int64_t value, RelocInfo::Mode rmode) {
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  EnsureSpace ensure_space(this);
  emit_rex_64(dst);
  emit(0xB8 | dst.low_bits());
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  if (!RelocInfo::IsNone(rmode)) {
    RecordRelocInfo(rmode, value);
  }
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  emitq(value);
}

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void Assembler::movq(Register dst, uint64_t value, RelocInfo::Mode rmode) {
  movq(dst, static_cast<int64_t>(value), rmode);
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}

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// Loads the ip-relative location of the src label into the target location
// (as a 32-bit offset sign extended to 64-bit).
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void Assembler::movl(const Operand& dst, Label* src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst);
  emit(0xC7);
  emit_operand(0, dst);
  if (src->is_bound()) {
    int offset = src->pos() - pc_offset() - sizeof(int32_t);
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    DCHECK_LE(offset, 0);
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    emitl(offset);
  } else if (src->is_linked()) {
    emitl(src->pos());
    src->link_to(pc_offset() - sizeof(int32_t));
  } else {
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    DCHECK(src->is_unused());
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    int32_t current = pc_offset();
    emitl(current);
    src->link_to(current);
  }
}


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void Assembler::movsxbl(Register dst, Register src) {
  EnsureSpace ensure_space(this);
  if (!src.is_byte_register()) {
    // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
    emit_rex_32(dst, src);
  } else {
    emit_optional_rex_32(dst, src);
  }
  emit(0x0F);
  emit(0xBE);
  emit_modrm(dst, src);
}


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void Assembler::movsxbl(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xBE);
  emit_operand(dst, src);
}


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void Assembler::movsxbq(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
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  emit_rex_64(dst, src);
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  emit(0x0F);
  emit(0xBE);
  emit_operand(dst, src);
}

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void Assembler::movsxbq(Register dst, Register src) {
  EnsureSpace ensure_space(this);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0xBE);
  emit_modrm(dst, src);
}
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void Assembler::movsxwl(Register dst, Register src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xBF);
  emit_modrm(dst, src);
}


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void Assembler::movsxwl(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xBF);
  emit_operand(dst, src);
}


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void Assembler::movsxwq(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0xBF);
  emit_operand(dst, src);
}

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void Assembler::movsxwq(Register dst, Register src) {
  EnsureSpace ensure_space(this);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0xBF);
  emit_modrm(dst, src);
}
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void Assembler::movsxlq(Register dst, Register src) {
  EnsureSpace ensure_space(this);
  emit_rex_64(dst, src);
  emit(0x63);
  emit_modrm(dst, src);
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}


void Assembler::movsxlq(Register dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_rex_64(dst, src);
  emit(0x63);
  emit_operand(dst, src);
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}


1767
void Assembler::emit_movzxb(Register dst, const Operand& src, int size) {
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  EnsureSpace ensure_space(this);
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  // 32 bit operations zero the top 32 bits of 64 bit registers.  Therefore
  // there is no need to make this a 64 bit operation.
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  emit_optional_rex_32(dst, src);
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  emit(0x0F);
  emit(0xB6);
  emit_operand(dst, src);
}


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void Assembler::emit_movzxb(Register dst, Register src, int size) {
  EnsureSpace ensure_space(this);
  // 32 bit operations zero the top 32 bits of 64 bit registers.  Therefore
  // there is no need to make this a 64 bit operation.
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  if (!src.is_byte_register()) {
    // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
    emit_rex_32(dst, src);
  } else {
    emit_optional_rex_32(dst, src);
  }
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  emit(0x0F);
  emit(0xB6);
  emit_modrm(dst, src);
}


1794
void Assembler::emit_movzxw(Register dst, const Operand& src, int size) {
1795
  EnsureSpace ensure_space(this);
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  // 32 bit operations zero the top 32 bits of 64 bit registers.  Therefore
  // there is no need to make this a 64 bit operation.
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  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xB7);
  emit_operand(dst, src);
}


1805
void Assembler::emit_movzxw(Register dst, Register src, int size) {
1806
  EnsureSpace ensure_space(this);
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  // 32 bit operations zero the top 32 bits of 64 bit registers.  Therefore
  // there is no need to make this a 64 bit operation.
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  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xB7);
  emit_modrm(dst, src);
}


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void Assembler::repmovsb() {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit(0xA4);
}


void Assembler::repmovsw() {
  EnsureSpace ensure_space(this);
  emit(0x66);  // Operand size override.
  emit(0xF3);
  emit(0xA4);
}


1831
void Assembler::emit_repmovs(int size) {
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  EnsureSpace ensure_space(this);
  emit(0xF3);
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  emit_rex(size);
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  emit(0xA5);
}


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void Assembler::mull(Register src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(src);
  emit(0xF7);
  emit_modrm(0x4, src);
}


void Assembler::mull(const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(src);
  emit(0xF7);
  emit_operand(0x4, src);
}


void Assembler::mulq(Register src) {
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  EnsureSpace ensure_space(this);
  emit_rex_64(src);
  emit(0xF7);
  emit_modrm(0x4, src);
}


1863
void Assembler::emit_neg(Register dst, int size) {
1864
  EnsureSpace ensure_space(this);
1865
  emit_rex(dst, size);
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  emit(0xF7);
  emit_modrm(0x3, dst);
}


1871
void Assembler::emit_neg(const Operand& dst, int size) {
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  EnsureSpace ensure_space(this);
  emit_rex_64(dst);
  emit(0xF7);
  emit_operand(3, dst);
}


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void Assembler::nop() {
  EnsureSpace ensure_space(this);
1881
  emit(0x90);
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}

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1885
void Assembler::emit_not(Register dst, int size) {
1886
  EnsureSpace ensure_space(this);
1887
  emit_rex(dst, size);
1888
  emit(0xF7);
1889
  emit_modrm(0x2, dst);
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}


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void Assembler::emit_not(const Operand& dst, int size) {
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  EnsureSpace ensure_space(this);
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  emit_rex(dst, size);
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  emit(0xF7);
  emit_operand(2, dst);
}


1901
void Assembler::Nop(int n) {
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  // The recommended muti-byte sequences of NOP instructions from the Intel 64
  // and IA-32 Architectures Software Developer's Manual.
  //
  // Length   Assembly                                Byte Sequence
  // 2 bytes  66 NOP                                  66 90H
  // 3 bytes  NOP DWORD ptr [EAX]                     0F 1F 00H
  // 4 bytes  NOP DWORD ptr [EAX + 00H]               0F 1F 40 00H
  // 5 bytes  NOP DWORD ptr [EAX + EAX*1 + 00H]       0F 1F 44 00 00H
  // 6 bytes  66 NOP DWORD ptr [EAX + EAX*1 + 00H]    66 0F 1F 44 00 00H
  // 7 bytes  NOP DWORD ptr [EAX + 00000000H]         0F 1F 80 00 00 00 00H
  // 8 bytes  NOP DWORD ptr [EAX + EAX*1 + 00000000H] 0F 1F 84 00 00 00 00 00H
  // 9 bytes  66 NOP DWORD ptr [EAX + EAX*1 +         66 0F 1F 84 00 00 00 00
  //          00000000H]                              00H

  EnsureSpace ensure_space(this);
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  while (n > 0) {
    switch (n) {
      case 2:
        emit(0x66);
      case 1:
        emit(0x90);
        return;
      case 3:
        emit(0x0f);
        emit(0x1f);
        emit(0x00);
        return;
      case 4:
        emit(0x0f);
        emit(0x1f);
        emit(0x40);
        emit(0x00);
        return;
      case 6:
        emit(0x66);
      case 5:
        emit(0x0f);
        emit(0x1f);
        emit(0x44);
        emit(0x00);
        emit(0x00);
        return;
      case 7:
        emit(0x0f);
        emit(0x1f);
        emit(0x80);
        emit(0x00);
        emit(0x00);
        emit(0x00);
        emit(0x00);
        return;
      default:
      case 11:
        emit(0x66);
        n--;
      case 10:
        emit(0x66);
        n--;
      case 9:
        emit(0x66);
        n--;
      case 8:
        emit(0x0f);
        emit(0x1f);
        emit(0x84);
        emit(0x00);
        emit(0x00);
        emit(0x00);
        emit(0x00);
        emit(0x00);
        n -= 8;
    }
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  }
}


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void Assembler::popq(Register dst) {
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  EnsureSpace ensure_space(this);
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  emit_optional_rex_32(dst);
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  emit(0x58 | dst.low_bits());
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}


1985
void Assembler::popq(const Operand& dst) {
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  EnsureSpace ensure_space(this);
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  emit_optional_rex_32(dst);
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  emit(0x8F);
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  emit_operand(0, dst);
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}


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void Assembler::popfq() {
  EnsureSpace ensure_space(this);
  emit(0x9D);
}


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void Assembler::pushq(Register src) {
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  EnsureSpace ensure_space(this);
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  emit_optional_rex_32(src);
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  emit(0x50 | src.low_bits());
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}


2006
void Assembler::pushq(const Operand& src) {
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  EnsureSpace ensure_space(this);
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  emit_optional_rex_32(src);
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  emit(0xFF);
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  emit_operand(6, src);
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}


2014
void Assembler::pushq(Immediate value) {
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  EnsureSpace ensure_space(this);
  if (is_int8(value.value_)) {
    emit(0x6A);
    emit(value.value_);  // Emit low byte of value.
  } else {
    emit(0x68);
    emitl(value.value_);
  }
}


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void Assembler::pushq_imm32(int32_t imm32) {
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  EnsureSpace ensure_space(this);
  emit(0x68);
  emitl(imm32);
}


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void Assembler::pushfq() {
  EnsureSpace ensure_space(this);
  emit(0x9C);
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}

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void Assembler::ret(int imm16) {
  EnsureSpace ensure_space(this);
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  DCHECK(is_uint16(imm16));
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  if (imm16 == 0) {
2043
    emit(0xC3);
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  } else {
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    emit(0xC2);
    emit(imm16 & 0xFF);
    emit((imm16 >> 8) & 0xFF);
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  }
}

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void Assembler::ud2() {
  EnsureSpace ensure_space(this);
  emit(0x0F);
  emit(0x0B);
}


2059
void Assembler::setcc(Condition cc, Register reg) {
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  if (cc > last_condition) {
    movb(reg, Immediate(cc == always ? 1 : 0));
    return;
  }
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  EnsureSpace ensure_space(this);
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  DCHECK(is_uint4(cc));
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  if (!reg.is_byte_register()) {
    // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
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    emit_rex_32(reg);
  }
  emit(0x0F);
  emit(0x90 | cc);
  emit_modrm(0x0, reg);
}


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void Assembler::shld(Register dst, Register src) {
  EnsureSpace ensure_space(this);
  emit_rex_64(src, dst);
  emit(0x0F);
  emit(0xA5);
  emit_modrm(src, dst);
}


void Assembler::shrd(Register dst, Register src) {
  EnsureSpace ensure_space(this);
  emit_rex_64(src, dst);
  emit(0x0F);
  emit(0xAD);
  emit_modrm(src, dst);
}

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void Assembler::xchgb(Register reg, const Operand& op) {
  EnsureSpace ensure_space(this);
  if (!reg.is_byte_register()) {
    // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
    emit_rex_32(reg, op);
  } else {
    emit_optional_rex_32(reg, op);
  }
  emit(0x86);
  emit_operand(reg, op);
}

void Assembler::xchgw(Register reg, const Operand& op) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(reg, op);
  emit(0x87);
  emit_operand(reg, op);
}
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void Assembler::emit_xchg(Register dst, Register src, int size) {
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  EnsureSpace ensure_space(this);
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  if (src == rax || dst == rax) {  // Single-byte encoding
    Register other = src == rax ? dst : src;
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    emit_rex(other, size);
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    emit(0x90 | other.low_bits());
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  } else if (dst.low_bits() == 4) {
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    emit_rex(dst, src, size);
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    emit(0x87);
    emit_modrm(dst, src);
  } else {
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    emit_rex(src, dst, size);
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    emit(0x87);
    emit_modrm(src, dst);
  }
}


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void Assembler::emit_xchg(Register dst, const Operand& src, int size) {
  EnsureSpace ensure_space(this);
  emit_rex(dst, src, size);
  emit(0x87);
  emit_operand(dst, src);
}


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void Assembler::store_rax(void* dst, RelocInfo::Mode mode) {
  EnsureSpace ensure_space(this);
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  if (kPointerSize == kInt64Size) {
    emit(0x48);  // REX.W
    emit(0xA3);
    emitp(dst, mode);
  } else {
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    DCHECK_EQ(kPointerSize, kInt32Size);
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    emit(0xA3);
    emitp(dst, mode);
    // In 64-bit mode, need to zero extend the operand to 8 bytes.
    // See 2.2.1.4 in Intel64 and IA32 Architectures Software
    // Developer's Manual Volume 2.
    emitl(0);
  }
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lrn@chromium.org committed
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}


void Assembler::store_rax(ExternalReference ref) {
  store_rax(ref.address(), RelocInfo::EXTERNAL_REFERENCE);
}


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void Assembler::testb(Register dst, Register src) {
  EnsureSpace ensure_space(this);
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  emit_test(dst, src, sizeof(int8_t));
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}

2167
void Assembler::testb(Register reg, Immediate mask) {
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  DCHECK(is_int8(mask.value_) || is_uint8(mask.value_));
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  emit_test(reg, mask, sizeof(int8_t));
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}

void Assembler::testb(const Operand& op, Immediate mask) {
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  DCHECK(is_int8(mask.value_) || is_uint8(mask.value_));
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  emit_test(op, mask, sizeof(int8_t));
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}


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void Assembler::testb(const Operand& op, Register reg) {
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  emit_test(op, reg, sizeof(int8_t));
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}

2182
void Assembler::testw(Register dst, Register src) {
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  emit_test(dst, src, sizeof(uint16_t));
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}

void Assembler::testw(Register reg, Immediate mask) {
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  emit_test(reg, mask, sizeof(int16_t));
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}

void Assembler::testw(const Operand& op, Immediate mask) {
2191
  emit_test(op, mask, sizeof(int16_t));
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}

void Assembler::testw(const Operand& op, Register reg) {
2195
  emit_test(op, reg, sizeof(int16_t));
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}
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void Assembler::emit_test(Register dst, Register src, int size) {
2199
  EnsureSpace ensure_space(this);
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  if (src.low_bits() == 4) std::swap(dst, src);
  if (size == sizeof(int16_t)) {
    emit(0x66);
    size = sizeof(int32_t);
  }
  bool byte_operand = size == sizeof(int8_t);
  if (byte_operand) {
    size = sizeof(int32_t);
    if (!src.is_byte_register() || !dst.is_byte_register()) {
      emit_rex_32(dst, src);
    }
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  } else {
2212
    emit_rex(dst, src, size);
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  }
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  emit(byte_operand ? 0x84 : 0x85);
  emit_modrm(dst, src);
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}


2219
void Assembler::emit_test(Register reg, Immediate mask, int size) {
2220
  if (is_uint8(mask.value_)) {
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    size = sizeof(int8_t);
  } else if (is_uint16(mask.value_)) {
    size = sizeof(int16_t);
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  }
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  EnsureSpace ensure_space(this);
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  bool half_word = size == sizeof(int16_t);
  if (half_word) {
    emit(0x66);
    size = sizeof(int32_t);
  }
  bool byte_operand = size == sizeof(int8_t);
  if (byte_operand) {
    size = sizeof(int32_t);
    if (!reg.is_byte_register()) emit_rex_32(reg);
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  } else {
2236
    emit_rex(reg, size);
2237
  }
2238
  if (reg == rax) {
2239 2240 2241
    emit(byte_operand ? 0xA8 : 0xA9);
  } else {
    emit(byte_operand ? 0xF6 : 0xF7);
2242
    emit_modrm(0x0, reg);
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  }
  if (byte_operand) {
    emit(mask.value_);
  } else if (half_word) {
    emitw(mask.value_);
  } else {
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    emit(mask);
  }
}

2253
void Assembler::emit_test(const Operand& op, Immediate mask, int size) {
2254
  if (is_uint8(mask.value_)) {
2255 2256 2257
    size = sizeof(int8_t);
  } else if (is_uint16(mask.value_)) {
    size = sizeof(int16_t);
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  }
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  EnsureSpace ensure_space(this);
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  bool half_word = size == sizeof(int16_t);
  if (half_word) {
    emit(0x66);
    size = sizeof(int32_t);
  }
  bool byte_operand = size == sizeof(int8_t);
  if (byte_operand) {
    size = sizeof(int32_t);
  }
2269
  emit_rex(rax, op, size);
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  emit(byte_operand ? 0xF6 : 0xF7);
2271
  emit_operand(rax, op);  // Operation code 0
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  if (byte_operand) {
    emit(mask.value_);
  } else if (half_word) {
    emitw(mask.value_);
  } else {
    emit(mask);
  }
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}

2281
void Assembler::emit_test(const Operand& op, Register reg, int size) {
2282
  EnsureSpace ensure_space(this);
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  if (size == sizeof(int16_t)) {
    emit(0x66);
    size = sizeof(int32_t);
  }
  bool byte_operand = size == sizeof(int8_t);
  if (byte_operand) {
    size = sizeof(int32_t);
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    if (!reg.is_byte_register()) {
      // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
      emit_rex_32(reg, op);
    } else {
      emit_optional_rex_32(reg, op);
    }
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  } else {
    emit_rex(reg, op, size);
  }
  emit(byte_operand ? 0x84 : 0x85);
2300 2301 2302 2303
  emit_operand(reg, op);
}


2304
// FPU instructions.
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void Assembler::fld(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xD9, 0xC0, i);
}


void Assembler::fld1() {
  EnsureSpace ensure_space(this);
  emit(0xD9);
  emit(0xE8);
}


void Assembler::fldz() {
  EnsureSpace ensure_space(this);
  emit(0xD9);
  emit(0xEE);
}


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void Assembler::fldpi() {
  EnsureSpace ensure_space(this);
  emit(0xD9);
  emit(0xEB);
}


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void Assembler::fldln2() {
  EnsureSpace ensure_space(this);
  emit(0xD9);
  emit(0xED);
}


2341 2342
void Assembler::fld_s(const Operand& adr) {
  EnsureSpace ensure_space(this);
2343
  emit_optional_rex_32(adr);
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  emit(0xD9);
  emit_operand(0, adr);
}


void Assembler::fld_d(const Operand& adr) {
  EnsureSpace ensure_space(this);
2351
  emit_optional_rex_32(adr);
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  emit(0xDD);
  emit_operand(0, adr);
}


void Assembler::fstp_s(const Operand& adr) {
  EnsureSpace ensure_space(this);
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  emit_optional_rex_32(adr);
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  emit(0xD9);
  emit_operand(3, adr);
}


void Assembler::fstp_d(const Operand& adr) {
  EnsureSpace ensure_space(this);
2367
  emit_optional_rex_32(adr);
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  emit(0xDD);
  emit_operand(3, adr);
}


2373
void Assembler::fstp(int index) {
2374
  DCHECK(is_uint3(index));
2375 2376 2377 2378 2379
  EnsureSpace ensure_space(this);
  emit_farith(0xDD, 0xD8, index);
}


2380 2381
void Assembler::fild_s(const Operand& adr) {
  EnsureSpace ensure_space(this);
2382
  emit_optional_rex_32(adr);
2383 2384 2385 2386 2387 2388 2389
  emit(0xDB);
  emit_operand(0, adr);
}


void Assembler::fild_d(const Operand& adr) {
  EnsureSpace ensure_space(this);
2390
  emit_optional_rex_32(adr);
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  emit(0xDF);
  emit_operand(5, adr);
}


void Assembler::fistp_s(const Operand& adr) {
  EnsureSpace ensure_space(this);
2398
  emit_optional_rex_32(adr);
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  emit(0xDB);
  emit_operand(3, adr);
}


void Assembler::fisttp_s(const Operand& adr) {
2405
  DCHECK(IsEnabled(SSE3));
2406
  EnsureSpace ensure_space(this);
2407
  emit_optional_rex_32(adr);
2408 2409 2410 2411 2412
  emit(0xDB);
  emit_operand(1, adr);
}


2413
void Assembler::fisttp_d(const Operand& adr) {
2414
  DCHECK(IsEnabled(SSE3));
2415 2416 2417 2418 2419 2420 2421
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(adr);
  emit(0xDD);
  emit_operand(1, adr);
}


2422 2423
void Assembler::fist_s(const Operand& adr) {
  EnsureSpace ensure_space(this);
2424
  emit_optional_rex_32(adr);
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  emit(0xDB);
  emit_operand(2, adr);
}


void Assembler::fistp_d(const Operand& adr) {
  EnsureSpace ensure_space(this);
2432
  emit_optional_rex_32(adr);
2433
  emit(0xDF);
2434
  emit_operand(7, adr);
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}


void Assembler::fabs() {
  EnsureSpace ensure_space(this);
  emit(0xD9);
  emit(0xE1);
}


void Assembler::fchs() {
  EnsureSpace ensure_space(this);
  emit(0xD9);
  emit(0xE0);
}


void Assembler::fcos() {
  EnsureSpace ensure_space(this);
  emit(0xD9);
  emit(0xFF);
}


void Assembler::fsin() {
  EnsureSpace ensure_space(this);
  emit(0xD9);
  emit(0xFE);
}


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void Assembler::fptan() {
  EnsureSpace ensure_space(this);
  emit(0xD9);
  emit(0xF2);
}


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void Assembler::fyl2x() {
  EnsureSpace ensure_space(this);
  emit(0xD9);
  emit(0xF1);
}


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void Assembler::f2xm1() {
  EnsureSpace ensure_space(this);
  emit(0xD9);
  emit(0xF0);
}


void Assembler::fscale() {
  EnsureSpace ensure_space(this);
  emit(0xD9);
  emit(0xFD);
}


void Assembler::fninit() {
  EnsureSpace ensure_space(this);
  emit(0xDB);
  emit(0xE3);
}


2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514
void Assembler::fadd(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDC, 0xC0, i);
}


void Assembler::fsub(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDC, 0xE8, i);
}


void Assembler::fisub_s(const Operand& adr) {
  EnsureSpace ensure_space(this);
2515
  emit_optional_rex_32(adr);
2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615
  emit(0xDA);
  emit_operand(4, adr);
}


void Assembler::fmul(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDC, 0xC8, i);
}


void Assembler::fdiv(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDC, 0xF8, i);
}


void Assembler::faddp(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDE, 0xC0, i);
}


void Assembler::fsubp(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDE, 0xE8, i);
}


void Assembler::fsubrp(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDE, 0xE0, i);
}


void Assembler::fmulp(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDE, 0xC8, i);
}


void Assembler::fdivp(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDE, 0xF8, i);
}


void Assembler::fprem() {
  EnsureSpace ensure_space(this);
  emit(0xD9);
  emit(0xF8);
}


void Assembler::fprem1() {
  EnsureSpace ensure_space(this);
  emit(0xD9);
  emit(0xF5);
}


void Assembler::fxch(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xD9, 0xC8, i);
}


void Assembler::fincstp() {
  EnsureSpace ensure_space(this);
  emit(0xD9);
  emit(0xF7);
}


void Assembler::ffree(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDD, 0xC0, i);
}


void Assembler::ftst() {
  EnsureSpace ensure_space(this);
  emit(0xD9);
  emit(0xE4);
}


void Assembler::fucomp(int i) {
  EnsureSpace ensure_space(this);
  emit_farith(0xDD, 0xE8, i);
}


void Assembler::fucompp() {
  EnsureSpace ensure_space(this);
  emit(0xDA);
  emit(0xE9);
}


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void Assembler::fucomi(int i) {
  EnsureSpace ensure_space(this);
  emit(0xDB);
  emit(0xE8 + i);
}


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void Assembler::fucomip() {
  EnsureSpace ensure_space(this);
  emit(0xDF);
  emit(0xE9);
}


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void Assembler::fcompp() {
  EnsureSpace ensure_space(this);
  emit(0xDE);
  emit(0xD9);
}


void Assembler::fnstsw_ax() {
  EnsureSpace ensure_space(this);
  emit(0xDF);
  emit(0xE0);
}


void Assembler::fwait() {
  EnsureSpace ensure_space(this);
  emit(0x9B);
}


void Assembler::frndint() {
  EnsureSpace ensure_space(this);
  emit(0xD9);
  emit(0xFC);
}


void Assembler::fnclex() {
  EnsureSpace ensure_space(this);
  emit(0xDB);
  emit(0xE2);
}


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void Assembler::sahf() {
  // TODO(X64): Test for presence. Not all 64-bit intel CPU's have sahf
  // in 64-bit mode. Test CpuID.
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  DCHECK(IsEnabled(SAHF));
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  EnsureSpace ensure_space(this);
  emit(0x9E);
}


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void Assembler::emit_farith(int b1, int b2, int i) {
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  DCHECK(is_uint8(b1) && is_uint8(b2));  // wrong opcode
  DCHECK(is_uint3(i));  // illegal stack offset
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  emit(b1);
  emit(b2 + i);
}

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// SSE operations.

void Assembler::andps(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x54);
  emit_sse_operand(dst, src);
}


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void Assembler::andps(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x54);
  emit_sse_operand(dst, src);
}


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void Assembler::orps(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x56);
  emit_sse_operand(dst, src);
}


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void Assembler::orps(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x56);
  emit_sse_operand(dst, src);
}


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void Assembler::xorps(XMMRegister dst, XMMRegister src) {
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  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x57);
  emit_sse_operand(dst, src);
}


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void Assembler::xorps(XMMRegister dst, const Operand& src) {
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  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x57);
  emit_sse_operand(dst, src);
}


void Assembler::addps(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x58);
  emit_sse_operand(dst, src);
}


void Assembler::addps(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x58);
  emit_sse_operand(dst, src);
}


void Assembler::subps(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5C);
  emit_sse_operand(dst, src);
}


void Assembler::subps(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5C);
  emit_sse_operand(dst, src);
}


void Assembler::mulps(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x59);
  emit_sse_operand(dst, src);
}


void Assembler::mulps(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x59);
  emit_sse_operand(dst, src);
}


void Assembler::divps(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5E);
  emit_sse_operand(dst, src);
}


void Assembler::divps(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5E);
  emit_sse_operand(dst, src);
}


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// SSE 2 operations.
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void Assembler::movd(XMMRegister dst, Register src) {
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  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x6E);
  emit_sse_operand(dst, src);
}


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void Assembler::movd(XMMRegister dst, const Operand& src) {
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  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x6E);
  emit_sse_operand(dst, src);
}


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void Assembler::movd(Register dst, XMMRegister src) {
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  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0x66);
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  emit_optional_rex_32(src, dst);
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  emit(0x0F);
  emit(0x7E);
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  emit_sse_operand(src, dst);
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}


void Assembler::movq(XMMRegister dst, Register src) {
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  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0x6E);
  emit_sse_operand(dst, src);
}


void Assembler::movq(Register dst, XMMRegister src) {
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  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0x66);
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  emit_rex_64(src, dst);
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  emit(0x0F);
  emit(0x7E);
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  emit_sse_operand(src, dst);
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}


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void Assembler::movq(XMMRegister dst, XMMRegister src) {
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  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  if (dst.low_bits() == 4) {
    // Avoid unnecessary SIB byte.
    emit(0xf3);
    emit_optional_rex_32(dst, src);
    emit(0x0F);
    emit(0x7e);
    emit_sse_operand(dst, src);
  } else {
    emit(0x66);
    emit_optional_rex_32(src, dst);
    emit(0x0F);
    emit(0xD6);
    emit_sse_operand(src, dst);
  }
}

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void Assembler::movdqa(const Operand& dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_rex_64(src, dst);
  emit(0x0F);
  emit(0x7F);
  emit_sse_operand(src, dst);
}


void Assembler::movdqa(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0x6F);
  emit_sse_operand(dst, src);
}


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void Assembler::movdqu(const Operand& dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_rex_64(src, dst);
  emit(0x0F);
  emit(0x7F);
  emit_sse_operand(src, dst);
}


void Assembler::movdqu(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0x6F);
  emit_sse_operand(dst, src);
}


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void Assembler::extractps(Register dst, XMMRegister src, byte imm8) {
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  DCHECK(IsEnabled(SSE4_1));
  DCHECK(is_uint8(imm8));
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  EnsureSpace ensure_space(this);
  emit(0x66);
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  emit_optional_rex_32(src, dst);
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  emit(0x0F);
  emit(0x3A);
  emit(0x17);
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  emit_sse_operand(src, dst);
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  emit(imm8);
}

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void Assembler::pextrb(Register dst, XMMRegister src, int8_t imm8) {
  DCHECK(IsEnabled(SSE4_1));
  DCHECK(is_uint8(imm8));
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(src, dst);
  emit(0x0F);
  emit(0x3A);
  emit(0x14);
  emit_sse_operand(src, dst);
  emit(imm8);
}

void Assembler::pextrb(const Operand& dst, XMMRegister src, int8_t imm8) {
  DCHECK(IsEnabled(SSE4_1));
  DCHECK(is_uint8(imm8));
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(src, dst);
  emit(0x0F);
  emit(0x3A);
  emit(0x14);
  emit_sse_operand(src, dst);
  emit(imm8);
}

void Assembler::pinsrw(XMMRegister dst, Register src, int8_t imm8) {
  DCHECK(is_uint8(imm8));
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xC4);
  emit_sse_operand(dst, src);
  emit(imm8);
}

void Assembler::pinsrw(XMMRegister dst, const Operand& src, int8_t imm8) {
  DCHECK(is_uint8(imm8));
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xC4);
  emit_sse_operand(dst, src);
  emit(imm8);
}

void Assembler::pextrw(Register dst, XMMRegister src, int8_t imm8) {
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  DCHECK(IsEnabled(SSE4_1));
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  DCHECK(is_uint8(imm8));
  EnsureSpace ensure_space(this);
  emit(0x66);
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  emit_optional_rex_32(src, dst);
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  emit(0x0F);
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  emit(0x3A);
  emit(0x15);
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  emit_sse_operand(src, dst);
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  emit(imm8);
}

void Assembler::pextrw(const Operand& dst, XMMRegister src, int8_t imm8) {
  DCHECK(IsEnabled(SSE4_1));
  DCHECK(is_uint8(imm8));
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(src, dst);
  emit(0x0F);
  emit(0x3A);
  emit(0x15);
  emit_sse_operand(src, dst);
  emit(imm8);
}
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void Assembler::pextrd(Register dst, XMMRegister src, int8_t imm8) {
  DCHECK(IsEnabled(SSE4_1));
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(src, dst);
  emit(0x0F);
  emit(0x3A);
  emit(0x16);
  emit_sse_operand(src, dst);
  emit(imm8);
}

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void Assembler::pextrd(const Operand& dst, XMMRegister src, int8_t imm8) {
  DCHECK(IsEnabled(SSE4_1));
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(src, dst);
  emit(0x0F);
  emit(0x3A);
  emit(0x16);
  emit_sse_operand(src, dst);
  emit(imm8);
}
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void Assembler::pinsrd(XMMRegister dst, Register src, int8_t imm8) {
  DCHECK(IsEnabled(SSE4_1));
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x3A);
  emit(0x22);
  emit_sse_operand(dst, src);
  emit(imm8);
}


void Assembler::pinsrd(XMMRegister dst, const Operand& src, int8_t imm8) {
  DCHECK(IsEnabled(SSE4_1));
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x3A);
  emit(0x22);
  emit_sse_operand(dst, src);
  emit(imm8);
}

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void Assembler::pinsrb(XMMRegister dst, Register src, int8_t imm8) {
  DCHECK(IsEnabled(SSE4_1));
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x3A);
  emit(0x20);
  emit_sse_operand(dst, src);
  emit(imm8);
}

void Assembler::pinsrb(XMMRegister dst, const Operand& src, int8_t imm8) {
  DCHECK(IsEnabled(SSE4_1));
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x3A);
  emit(0x20);
  emit_sse_operand(dst, src);
  emit(imm8);
}

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void Assembler::insertps(XMMRegister dst, XMMRegister src, byte imm8) {
  DCHECK(CpuFeatures::IsSupported(SSE4_1));
  DCHECK(is_uint8(imm8));
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x3A);
  emit(0x21);
  emit_sse_operand(dst, src);
  emit(imm8);
}
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void Assembler::movsd(const Operand& dst, XMMRegister src) {
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  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF2);  // double
  emit_optional_rex_32(src, dst);
  emit(0x0F);
  emit(0x11);  // store
  emit_sse_operand(src, dst);
}


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void Assembler::movsd(XMMRegister dst, XMMRegister src) {
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  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF2);  // double
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x10);  // load
  emit_sse_operand(dst, src);
}


void Assembler::movsd(XMMRegister dst, const Operand& src) {
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  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF2);  // double
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x10);  // load
  emit_sse_operand(dst, src);
}


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void Assembler::movaps(XMMRegister dst, XMMRegister src) {
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  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  if (src.low_bits() == 4) {
    // Try to avoid an unnecessary SIB byte.
    emit_optional_rex_32(src, dst);
    emit(0x0F);
    emit(0x29);
    emit_sse_operand(src, dst);
  } else {
    emit_optional_rex_32(dst, src);
    emit(0x0F);
    emit(0x28);
    emit_sse_operand(dst, src);
  }
}


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void Assembler::shufps(XMMRegister dst, XMMRegister src, byte imm8) {
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  DCHECK(is_uint8(imm8));
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  EnsureSpace ensure_space(this);
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  emit_optional_rex_32(dst, src);
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  emit(0x0F);
  emit(0xC6);
  emit_sse_operand(dst, src);
  emit(imm8);
}


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void Assembler::movapd(XMMRegister dst, XMMRegister src) {
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  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  if (src.low_bits() == 4) {
    // Try to avoid an unnecessary SIB byte.
    emit(0x66);
    emit_optional_rex_32(src, dst);
    emit(0x0F);
    emit(0x29);
    emit_sse_operand(src, dst);
  } else {
    emit(0x66);
    emit_optional_rex_32(dst, src);
    emit(0x0F);
    emit(0x28);
    emit_sse_operand(dst, src);
  }
}


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void Assembler::movupd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x10);
  emit_sse_operand(dst, src);
}

void Assembler::movupd(const Operand& dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(src, dst);
  emit(0x0F);
  emit(0x11);
  emit_sse_operand(src, dst);
}

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void Assembler::addss(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x58);
  emit_sse_operand(dst, src);
}


void Assembler::addss(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x58);
  emit_sse_operand(dst, src);
}


void Assembler::subss(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5C);
  emit_sse_operand(dst, src);
}


void Assembler::subss(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5C);
  emit_sse_operand(dst, src);
}


void Assembler::mulss(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x59);
  emit_sse_operand(dst, src);
}


void Assembler::mulss(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x59);
  emit_sse_operand(dst, src);
}


void Assembler::divss(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5E);
  emit_sse_operand(dst, src);
}


void Assembler::divss(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5E);
  emit_sse_operand(dst, src);
}


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void Assembler::maxss(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5F);
  emit_sse_operand(dst, src);
}


void Assembler::maxss(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5F);
  emit_sse_operand(dst, src);
}


void Assembler::minss(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5D);
  emit_sse_operand(dst, src);
}


void Assembler::minss(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5D);
  emit_sse_operand(dst, src);
}


void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x51);
  emit_sse_operand(dst, src);
}


void Assembler::sqrtss(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x51);
  emit_sse_operand(dst, src);
}


3341
void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
3342
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0f);
  emit(0x2e);
  emit_sse_operand(dst, src);
}


void Assembler::ucomiss(XMMRegister dst, const Operand& src) {
3352
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0f);
  emit(0x2e);
  emit_sse_operand(dst, src);
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}


void Assembler::movss(XMMRegister dst, XMMRegister src) {
  DCHECK(!IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit(0xF3);  // single
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x10);  // load
  emit_sse_operand(dst, src);
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}


3372
void Assembler::movss(XMMRegister dst, const Operand& src) {
3373
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF3);  // single
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x10);  // load
  emit_sse_operand(dst, src);
}


void Assembler::movss(const Operand& src, XMMRegister dst) {
3384
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF3);  // single
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x11);  // store
  emit_sse_operand(dst, src);
}


3394
void Assembler::psllq(XMMRegister reg, byte imm8) {
3395
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0x66);
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  emit_optional_rex_32(reg);
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  emit(0x0F);
  emit(0x73);
  emit_sse_operand(rsi, reg);  // rsi == 6
  emit(imm8);
}


3406
void Assembler::psrlq(XMMRegister reg, byte imm8) {
3407
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(reg);
  emit(0x0F);
  emit(0x73);
  emit_sse_operand(rdx, reg);  // rdx == 2
  emit(imm8);
}

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void Assembler::psllw(XMMRegister reg, byte imm8) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(reg);
  emit(0x0F);
  emit(0x71);
  emit_sse_operand(rsi, reg);  // rsi == 6
  emit(imm8);
}
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void Assembler::pslld(XMMRegister reg, byte imm8) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(reg);
  emit(0x0F);
  emit(0x72);
  emit_sse_operand(rsi, reg);  // rsi == 6
  emit(imm8);
}

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void Assembler::psrlw(XMMRegister reg, byte imm8) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(reg);
  emit(0x0F);
  emit(0x71);
  emit_sse_operand(rdx, reg);  // rdx == 2
  emit(imm8);
}
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void Assembler::psrld(XMMRegister reg, byte imm8) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(reg);
  emit(0x0F);
  emit(0x72);
  emit_sse_operand(rdx, reg);  // rdx == 2
  emit(imm8);
}

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void Assembler::psraw(XMMRegister reg, byte imm8) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(reg);
  emit(0x0F);
  emit(0x71);
  emit_sse_operand(rsp, reg);  // rsp == 4
  emit(imm8);
}

void Assembler::psrad(XMMRegister reg, byte imm8) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(reg);
  emit(0x0F);
  emit(0x72);
  emit_sse_operand(rsp, reg);  // rsp == 4
  emit(imm8);
}

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void Assembler::cmpps(XMMRegister dst, XMMRegister src, int8_t cmp) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xC2);
  emit_sse_operand(dst, src);
  emit(cmp);
}

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void Assembler::cmpps(XMMRegister dst, const Operand& src, int8_t cmp) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xC2);
  emit_sse_operand(dst, src);
  emit(cmp);
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}

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void Assembler::cmppd(XMMRegister dst, XMMRegister src, int8_t cmp) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x66);
  emit(0x0F);
  emit(0xC2);
  emit_sse_operand(dst, src);
  emit(cmp);
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}

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void Assembler::cmppd(XMMRegister dst, const Operand& src, int8_t cmp) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x66);
  emit(0x0F);
  emit(0xC2);
  emit_sse_operand(dst, src);
  emit(cmp);
3513
}
3514

3515
void Assembler::cvttss2si(Register dst, const Operand& src) {
3516
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x2C);
  emit_operand(dst, src);
}


3526
void Assembler::cvttss2si(Register dst, XMMRegister src) {
3527
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x2C);
  emit_sse_operand(dst, src);
}


3537
void Assembler::cvttsd2si(Register dst, const Operand& src) {
3538
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x2C);
  emit_operand(dst, src);
}


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void Assembler::cvttsd2si(Register dst, XMMRegister src) {
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  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x2C);
  emit_sse_operand(dst, src);
}


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void Assembler::cvttss2siq(Register dst, XMMRegister src) {
  DCHECK(!IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0x2C);
  emit_sse_operand(dst, src);
}


void Assembler::cvttss2siq(Register dst, const Operand& src) {
  DCHECK(!IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0x2C);
  emit_sse_operand(dst, src);
}


3581
void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
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  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0x2C);
  emit_sse_operand(dst, src);
}


3592
void Assembler::cvttsd2siq(Register dst, const Operand& src) {
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  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0x2C);
  emit_sse_operand(dst, src);
}


3603
void Assembler::cvtlsi2sd(XMMRegister dst, const Operand& src) {
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  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x2A);
  emit_sse_operand(dst, src);
}


void Assembler::cvtlsi2sd(XMMRegister dst, Register src) {
3615
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x2A);
  emit_sse_operand(dst, src);
}


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void Assembler::cvtlsi2ss(XMMRegister dst, const Operand& src) {
  DCHECK(!IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x2A);
  emit_sse_operand(dst, src);
}


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void Assembler::cvtlsi2ss(XMMRegister dst, Register src) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x2A);
  emit_sse_operand(dst, src);
}


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void Assembler::cvtqsi2ss(XMMRegister dst, const Operand& src) {
  DCHECK(!IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0x2A);
  emit_sse_operand(dst, src);
}


void Assembler::cvtqsi2ss(XMMRegister dst, Register src) {
  DCHECK(!IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0x2A);
  emit_sse_operand(dst, src);
}


3668
void Assembler::cvtqsi2sd(XMMRegister dst, const Operand& src) {
3669
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0x2A);
  emit_sse_operand(dst, src);
}


3679
void Assembler::cvtqsi2sd(XMMRegister dst, Register src) {
3680
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0x2A);
  emit_sse_operand(dst, src);
}


3690
void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
3691
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5A);
  emit_sse_operand(dst, src);
}


3701
void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) {
3702
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5A);
  emit_sse_operand(dst, src);
}


void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
3713
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5A);
  emit_sse_operand(dst, src);
}


3723
void Assembler::cvtsd2ss(XMMRegister dst, const Operand& src) {
3724
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5A);
  emit_sse_operand(dst, src);
}


3734
void Assembler::cvtsd2si(Register dst, XMMRegister src) {
3735
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x2D);
  emit_sse_operand(dst, src);
}


void Assembler::cvtsd2siq(Register dst, XMMRegister src) {
3746
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0x2D);
  emit_sse_operand(dst, src);
}


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void Assembler::addsd(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x58);
  emit_sse_operand(dst, src);
}


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void Assembler::addsd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x58);
  emit_sse_operand(dst, src);
}


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void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x59);
  emit_sse_operand(dst, src);
}


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void Assembler::mulsd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x59);
  emit_sse_operand(dst, src);
}


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void Assembler::subsd(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5C);
  emit_sse_operand(dst, src);
}


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void Assembler::subsd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5C);
  emit_sse_operand(dst, src);
}


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void Assembler::divsd(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5E);
  emit_sse_operand(dst, src);
}


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void Assembler::divsd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5E);
  emit_sse_operand(dst, src);
}


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void Assembler::maxsd(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5F);
  emit_sse_operand(dst, src);
}


void Assembler::maxsd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5F);
  emit_sse_operand(dst, src);
}


void Assembler::minsd(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5D);
  emit_sse_operand(dst, src);
}


void Assembler::minsd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5D);
  emit_sse_operand(dst, src);
}


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void Assembler::andpd(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x54);
  emit_sse_operand(dst, src);
}


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void Assembler::andpd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x54);
  emit_sse_operand(dst, src);
}


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void Assembler::orpd(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x56);
  emit_sse_operand(dst, src);
}


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void Assembler::orpd(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x56);
  emit_sse_operand(dst, src);
}


3916
void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
3917
  DCHECK(!IsEnabled(AVX));
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  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
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  emit(0x0F);
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  emit(0x57);
  emit_sse_operand(dst, src);
}


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void Assembler::xorpd(XMMRegister dst, const Operand& src) {
  DCHECK(!IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x57);
  emit_sse_operand(dst, src);
}


3938
void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
3939
  DCHECK(!IsEnabled(AVX));
3940 3941 3942 3943 3944 3945 3946 3947 3948
  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x51);
  emit_sse_operand(dst, src);
}


3949
void Assembler::sqrtsd(XMMRegister dst, const Operand& src) {
3950
  DCHECK(!IsEnabled(AVX));
3951 3952 3953 3954 3955 3956 3957 3958 3959
  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x51);
  emit_sse_operand(dst, src);
}


3960
void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
3961
  DCHECK(!IsEnabled(AVX));
3962 3963 3964 3965 3966 3967 3968 3969
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0f);
  emit(0x2e);
  emit_sse_operand(dst, src);
}

3970

3971
void Assembler::ucomisd(XMMRegister dst, const Operand& src) {
3972
  DCHECK(!IsEnabled(AVX));
3973 3974 3975 3976 3977 3978 3979 3980 3981
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0f);
  emit(0x2e);
  emit_sse_operand(dst, src);
}


3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992
void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xC2);
  emit_sse_operand(dst, src);
  emit(0x01);  // LT == 1
}


3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007
void Assembler::roundss(XMMRegister dst, XMMRegister src, RoundingMode mode) {
  DCHECK(!IsEnabled(AVX));
  DCHECK(IsEnabled(SSE4_1));
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0f);
  emit(0x3a);
  emit(0x0a);
  emit_sse_operand(dst, src);
  // Mask precision exception.
  emit(static_cast<byte>(mode) | 0x8);
}


4008
void Assembler::roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode) {
4009
  DCHECK(!IsEnabled(AVX));
4010
  DCHECK(IsEnabled(SSE4_1));
4011 4012 4013 4014 4015 4016 4017
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0f);
  emit(0x3a);
  emit(0x0b);
  emit_sse_operand(dst, src);
4018
  // Mask precision exception.
4019 4020 4021 4022
  emit(static_cast<byte>(mode) | 0x8);
}


4023 4024 4025 4026 4027 4028 4029 4030 4031
void Assembler::movmskpd(Register dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0f);
  emit(0x50);
  emit_sse_operand(dst, src);
}

4032

4033 4034 4035 4036 4037 4038 4039 4040 4041
void Assembler::movmskps(Register dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0f);
  emit(0x50);
  emit_sse_operand(dst, src);
}


4042 4043 4044 4045 4046 4047 4048 4049 4050
void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x62);
  emit_sse_operand(dst, src);
}

4051 4052 4053 4054 4055 4056 4057 4058
void Assembler::punpckldq(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x62);
  emit_sse_operand(dst, src);
}
4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069

void Assembler::punpckhdq(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x6A);
  emit_sse_operand(dst, src);
}


4070
// AVX instructions
4071 4072 4073 4074
void Assembler::vfmasd(byte op, XMMRegister dst, XMMRegister src1,
                       XMMRegister src2) {
  DCHECK(IsEnabled(FMA3));
  EnsureSpace ensure_space(this);
4075
  emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW1);
4076 4077 4078 4079 4080 4081 4082 4083 4084
  emit(op);
  emit_sse_operand(dst, src2);
}


void Assembler::vfmasd(byte op, XMMRegister dst, XMMRegister src1,
                       const Operand& src2) {
  DCHECK(IsEnabled(FMA3));
  EnsureSpace ensure_space(this);
4085
  emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW1);
4086 4087 4088 4089 4090 4091 4092 4093 4094
  emit(op);
  emit_sse_operand(dst, src2);
}


void Assembler::vfmass(byte op, XMMRegister dst, XMMRegister src1,
                       XMMRegister src2) {
  DCHECK(IsEnabled(FMA3));
  EnsureSpace ensure_space(this);
4095
  emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW0);
4096 4097 4098 4099 4100 4101 4102 4103 4104
  emit(op);
  emit_sse_operand(dst, src2);
}


void Assembler::vfmass(byte op, XMMRegister dst, XMMRegister src1,
                       const Operand& src2) {
  DCHECK(IsEnabled(FMA3));
  EnsureSpace ensure_space(this);
4105 4106 4107 4108 4109 4110
  emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW0);
  emit(op);
  emit_sse_operand(dst, src2);
}


4111 4112 4113
void Assembler::vmovd(XMMRegister dst, Register src) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
4114
  XMMRegister isrc = XMMRegister::from_code(src.code());
4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132
  emit_vex_prefix(dst, xmm0, isrc, kL128, k66, k0F, kW0);
  emit(0x6e);
  emit_sse_operand(dst, src);
}


void Assembler::vmovd(XMMRegister dst, const Operand& src) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(dst, xmm0, src, kL128, k66, k0F, kW0);
  emit(0x6e);
  emit_sse_operand(dst, src);
}


void Assembler::vmovd(Register dst, XMMRegister src) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
4133
  XMMRegister idst = XMMRegister::from_code(dst.code());
4134 4135 4136 4137 4138 4139 4140 4141 4142
  emit_vex_prefix(src, xmm0, idst, kL128, k66, k0F, kW0);
  emit(0x7e);
  emit_sse_operand(src, dst);
}


void Assembler::vmovq(XMMRegister dst, Register src) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
4143
  XMMRegister isrc = XMMRegister::from_code(src.code());
4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161
  emit_vex_prefix(dst, xmm0, isrc, kL128, k66, k0F, kW1);
  emit(0x6e);
  emit_sse_operand(dst, src);
}


void Assembler::vmovq(XMMRegister dst, const Operand& src) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(dst, xmm0, src, kL128, k66, k0F, kW1);
  emit(0x6e);
  emit_sse_operand(dst, src);
}


void Assembler::vmovq(Register dst, XMMRegister src) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
4162
  XMMRegister idst = XMMRegister::from_code(dst.code());
4163 4164 4165 4166 4167
  emit_vex_prefix(src, xmm0, idst, kL128, k66, k0F, kW1);
  emit(0x7e);
  emit_sse_operand(src, dst);
}

4168 4169 4170
void Assembler::vinstr(byte op, XMMRegister dst, XMMRegister src1,
                       XMMRegister src2, SIMDPrefix pp, LeadingOpcode m,
                       VexW w) {
4171 4172
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
4173
  emit_vex_prefix(dst, src1, src2, kLIG, pp, m, w);
4174 4175 4176 4177
  emit(op);
  emit_sse_operand(dst, src2);
}

4178 4179 4180
void Assembler::vinstr(byte op, XMMRegister dst, XMMRegister src1,
                       const Operand& src2, SIMDPrefix pp, LeadingOpcode m,
                       VexW w) {
4181 4182
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
4183
  emit_vex_prefix(dst, src1, src2, kLIG, pp, m, w);
4184 4185 4186 4187 4188
  emit(op);
  emit_sse_operand(dst, src2);
}


4189 4190 4191 4192 4193 4194 4195 4196 4197
void Assembler::vps(byte op, XMMRegister dst, XMMRegister src1,
                    XMMRegister src2) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(dst, src1, src2, kL128, kNone, k0F, kWIG);
  emit(op);
  emit_sse_operand(dst, src2);
}

4198

4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228
void Assembler::vps(byte op, XMMRegister dst, XMMRegister src1,
                    const Operand& src2) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(dst, src1, src2, kL128, kNone, k0F, kWIG);
  emit(op);
  emit_sse_operand(dst, src2);
}


void Assembler::vpd(byte op, XMMRegister dst, XMMRegister src1,
                    XMMRegister src2) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(dst, src1, src2, kL128, k66, k0F, kWIG);
  emit(op);
  emit_sse_operand(dst, src2);
}


void Assembler::vpd(byte op, XMMRegister dst, XMMRegister src1,
                    const Operand& src2) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(dst, src1, src2, kL128, k66, k0F, kWIG);
  emit(op);
  emit_sse_operand(dst, src2);
}


4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266
void Assembler::vucomiss(XMMRegister dst, XMMRegister src) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(dst, xmm0, src, kLIG, kNone, k0F, kWIG);
  emit(0x2e);
  emit_sse_operand(dst, src);
}


void Assembler::vucomiss(XMMRegister dst, const Operand& src) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(dst, xmm0, src, kLIG, kNone, k0F, kWIG);
  emit(0x2e);
  emit_sse_operand(dst, src);
}


void Assembler::vss(byte op, XMMRegister dst, XMMRegister src1,
                    XMMRegister src2) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(dst, src1, src2, kLIG, kF3, k0F, kWIG);
  emit(op);
  emit_sse_operand(dst, src2);
}


void Assembler::vss(byte op, XMMRegister dst, XMMRegister src1,
                    const Operand& src2) {
  DCHECK(IsEnabled(AVX));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(dst, src1, src2, kLIG, kF3, k0F, kWIG);
  emit(op);
  emit_sse_operand(dst, src2);
}


4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477
void Assembler::bmi1q(byte op, Register reg, Register vreg, Register rm) {
  DCHECK(IsEnabled(BMI1));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW1);
  emit(op);
  emit_modrm(reg, rm);
}


void Assembler::bmi1q(byte op, Register reg, Register vreg, const Operand& rm) {
  DCHECK(IsEnabled(BMI1));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW1);
  emit(op);
  emit_operand(reg, rm);
}


void Assembler::bmi1l(byte op, Register reg, Register vreg, Register rm) {
  DCHECK(IsEnabled(BMI1));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW0);
  emit(op);
  emit_modrm(reg, rm);
}


void Assembler::bmi1l(byte op, Register reg, Register vreg, const Operand& rm) {
  DCHECK(IsEnabled(BMI1));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW0);
  emit(op);
  emit_operand(reg, rm);
}


void Assembler::tzcntq(Register dst, Register src) {
  DCHECK(IsEnabled(BMI1));
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0xBC);
  emit_modrm(dst, src);
}


void Assembler::tzcntq(Register dst, const Operand& src) {
  DCHECK(IsEnabled(BMI1));
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0xBC);
  emit_operand(dst, src);
}


void Assembler::tzcntl(Register dst, Register src) {
  DCHECK(IsEnabled(BMI1));
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xBC);
  emit_modrm(dst, src);
}


void Assembler::tzcntl(Register dst, const Operand& src) {
  DCHECK(IsEnabled(BMI1));
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xBC);
  emit_operand(dst, src);
}


void Assembler::lzcntq(Register dst, Register src) {
  DCHECK(IsEnabled(LZCNT));
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0xBD);
  emit_modrm(dst, src);
}


void Assembler::lzcntq(Register dst, const Operand& src) {
  DCHECK(IsEnabled(LZCNT));
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0xBD);
  emit_operand(dst, src);
}


void Assembler::lzcntl(Register dst, Register src) {
  DCHECK(IsEnabled(LZCNT));
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xBD);
  emit_modrm(dst, src);
}


void Assembler::lzcntl(Register dst, const Operand& src) {
  DCHECK(IsEnabled(LZCNT));
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xBD);
  emit_operand(dst, src);
}


void Assembler::popcntq(Register dst, Register src) {
  DCHECK(IsEnabled(POPCNT));
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0xB8);
  emit_modrm(dst, src);
}


void Assembler::popcntq(Register dst, const Operand& src) {
  DCHECK(IsEnabled(POPCNT));
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_rex_64(dst, src);
  emit(0x0F);
  emit(0xB8);
  emit_operand(dst, src);
}


void Assembler::popcntl(Register dst, Register src) {
  DCHECK(IsEnabled(POPCNT));
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xB8);
  emit_modrm(dst, src);
}


void Assembler::popcntl(Register dst, const Operand& src) {
  DCHECK(IsEnabled(POPCNT));
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0xB8);
  emit_operand(dst, src);
}


void Assembler::bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg,
                      Register rm) {
  DCHECK(IsEnabled(BMI2));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(reg, vreg, rm, kLZ, pp, k0F38, kW1);
  emit(op);
  emit_modrm(reg, rm);
}


void Assembler::bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg,
                      const Operand& rm) {
  DCHECK(IsEnabled(BMI2));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(reg, vreg, rm, kLZ, pp, k0F38, kW1);
  emit(op);
  emit_operand(reg, rm);
}


void Assembler::bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg,
                      Register rm) {
  DCHECK(IsEnabled(BMI2));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(reg, vreg, rm, kLZ, pp, k0F38, kW0);
  emit(op);
  emit_modrm(reg, rm);
}


void Assembler::bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg,
                      const Operand& rm) {
  DCHECK(IsEnabled(BMI2));
  EnsureSpace ensure_space(this);
  emit_vex_prefix(reg, vreg, rm, kLZ, pp, k0F38, kW0);
  emit(op);
  emit_operand(reg, rm);
}


void Assembler::rorxq(Register dst, Register src, byte imm8) {
  DCHECK(IsEnabled(BMI2));
  DCHECK(is_uint8(imm8));
4478
  Register vreg = Register::from_code<0>();  // VEX.vvvv unused
4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489
  EnsureSpace ensure_space(this);
  emit_vex_prefix(dst, vreg, src, kLZ, kF2, k0F3A, kW1);
  emit(0xF0);
  emit_modrm(dst, src);
  emit(imm8);
}


void Assembler::rorxq(Register dst, const Operand& src, byte imm8) {
  DCHECK(IsEnabled(BMI2));
  DCHECK(is_uint8(imm8));
4490
  Register vreg = Register::from_code<0>();  // VEX.vvvv unused
4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501
  EnsureSpace ensure_space(this);
  emit_vex_prefix(dst, vreg, src, kLZ, kF2, k0F3A, kW1);
  emit(0xF0);
  emit_operand(dst, src);
  emit(imm8);
}


void Assembler::rorxl(Register dst, Register src, byte imm8) {
  DCHECK(IsEnabled(BMI2));
  DCHECK(is_uint8(imm8));
4502
  Register vreg = Register::from_code<0>();  // VEX.vvvv unused
4503 4504 4505 4506 4507 4508 4509 4510 4511 4512 4513
  EnsureSpace ensure_space(this);
  emit_vex_prefix(dst, vreg, src, kLZ, kF2, k0F3A, kW0);
  emit(0xF0);
  emit_modrm(dst, src);
  emit(imm8);
}


void Assembler::rorxl(Register dst, const Operand& src, byte imm8) {
  DCHECK(IsEnabled(BMI2));
  DCHECK(is_uint8(imm8));
4514
  Register vreg = Register::from_code<0>();  // VEX.vvvv unused
4515 4516 4517 4518 4519 4520 4521
  EnsureSpace ensure_space(this);
  emit_vex_prefix(dst, vreg, src, kLZ, kF2, k0F3A, kW0);
  emit(0xF0);
  emit_operand(dst, src);
  emit(imm8);
}

4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598 4599 4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649
void Assembler::minps(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5D);
  emit_sse_operand(dst, src);
}

void Assembler::minps(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5D);
  emit_sse_operand(dst, src);
}

void Assembler::maxps(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5F);
  emit_sse_operand(dst, src);
}

void Assembler::maxps(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5F);
  emit_sse_operand(dst, src);
}

void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x53);
  emit_sse_operand(dst, src);
}

void Assembler::rcpps(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x53);
  emit_sse_operand(dst, src);
}

void Assembler::rsqrtps(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x52);
  emit_sse_operand(dst, src);
}

void Assembler::rsqrtps(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x52);
  emit_sse_operand(dst, src);
}

void Assembler::sqrtps(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x51);
  emit_sse_operand(dst, src);
}

void Assembler::sqrtps(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x51);
  emit_sse_operand(dst, src);
}

void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5B);
  emit_sse_operand(dst, src);
}

void Assembler::cvtdq2ps(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x5B);
  emit_sse_operand(dst, src);
}

void Assembler::movups(XMMRegister dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  if (src.low_bits() == 4) {
    // Try to avoid an unnecessary SIB byte.
    emit_optional_rex_32(src, dst);
    emit(0x0F);
    emit(0x11);
    emit_sse_operand(src, dst);
  } else {
    emit_optional_rex_32(dst, src);
    emit(0x0F);
    emit(0x10);
    emit_sse_operand(dst, src);
  }
}

void Assembler::movups(XMMRegister dst, const Operand& src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x10);
  emit_sse_operand(dst, src);
}

void Assembler::movups(const Operand& dst, XMMRegister src) {
  EnsureSpace ensure_space(this);
  emit_optional_rex_32(src, dst);
  emit(0x0F);
  emit(0x11);
  emit_sse_operand(src, dst);
}

4650 4651
void Assembler::sse2_instr(XMMRegister dst, XMMRegister src, byte prefix,
                           byte escape, byte opcode) {
4652
  EnsureSpace ensure_space(this);
4653
  emit(prefix);
4654
  emit_optional_rex_32(dst, src);
4655 4656
  emit(escape);
  emit(opcode);
4657 4658 4659
  emit_sse_operand(dst, src);
}

4660 4661
void Assembler::sse2_instr(XMMRegister dst, const Operand& src, byte prefix,
                           byte escape, byte opcode) {
4662
  EnsureSpace ensure_space(this);
4663
  emit(prefix);
4664
  emit_optional_rex_32(dst, src);
4665 4666
  emit(escape);
  emit(opcode);
4667 4668 4669
  emit_sse_operand(dst, src);
}

4670 4671 4672
void Assembler::ssse3_instr(XMMRegister dst, XMMRegister src, byte prefix,
                            byte escape1, byte escape2, byte opcode) {
  DCHECK(IsEnabled(SSSE3));
4673
  EnsureSpace ensure_space(this);
4674
  emit(prefix);
4675
  emit_optional_rex_32(dst, src);
4676 4677 4678
  emit(escape1);
  emit(escape2);
  emit(opcode);
4679 4680 4681
  emit_sse_operand(dst, src);
}

4682 4683 4684
void Assembler::ssse3_instr(XMMRegister dst, const Operand& src, byte prefix,
                            byte escape1, byte escape2, byte opcode) {
  DCHECK(IsEnabled(SSSE3));
4685
  EnsureSpace ensure_space(this);
4686
  emit(prefix);
4687
  emit_optional_rex_32(dst, src);
4688 4689 4690
  emit(escape1);
  emit(escape2);
  emit(opcode);
4691 4692 4693
  emit_sse_operand(dst, src);
}

4694 4695
void Assembler::sse4_instr(XMMRegister dst, XMMRegister src, byte prefix,
                           byte escape1, byte escape2, byte opcode) {
4696 4697
  DCHECK(IsEnabled(SSE4_1));
  EnsureSpace ensure_space(this);
4698
  emit(prefix);
4699
  emit_optional_rex_32(dst, src);
4700 4701 4702
  emit(escape1);
  emit(escape2);
  emit(opcode);
4703 4704 4705
  emit_sse_operand(dst, src);
}

4706 4707 4708
void Assembler::sse4_instr(XMMRegister dst, const Operand& src, byte prefix,
                           byte escape1, byte escape2, byte opcode) {
  DCHECK(IsEnabled(SSE4_1));
4709
  EnsureSpace ensure_space(this);
4710
  emit(prefix);
4711
  emit_optional_rex_32(dst, src);
4712 4713 4714
  emit(escape1);
  emit(escape2);
  emit(opcode);
4715 4716 4717
  emit_sse_operand(dst, src);
}

4718 4719
void Assembler::lddqu(XMMRegister dst, const Operand& src) {
  DCHECK(IsEnabled(SSE3));
4720
  EnsureSpace ensure_space(this);
4721
  emit(0xF2);
4722 4723
  emit_optional_rex_32(dst, src);
  emit(0x0F);
4724
  emit(0xF0);
4725 4726 4727 4728 4729 4730 4731 4732 4733 4734 4735 4736 4737
  emit_sse_operand(dst, src);
}

void Assembler::psrldq(XMMRegister dst, uint8_t shift) {
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst);
  emit(0x0F);
  emit(0x73);
  emit_sse_operand(dst);
  emit(shift);
}

4738 4739 4740 4741 4742 4743 4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754 4755 4756 4757
void Assembler::pshufhw(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
  EnsureSpace ensure_space(this);
  emit(0xF3);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x70);
  emit_sse_operand(dst, src);
  emit(shuffle);
}

void Assembler::pshuflw(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
  EnsureSpace ensure_space(this);
  emit(0xF2);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x70);
  emit_sse_operand(dst, src);
  emit(shuffle);
}

4758
void Assembler::pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
4759 4760 4761 4762
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
4763
  emit(0x70);
4764
  emit_sse_operand(dst, src);
4765
  emit(shuffle);
4766 4767
}

4768
void Assembler::pshufd(XMMRegister dst, const Operand& src, uint8_t shuffle) {
4769 4770 4771 4772 4773 4774 4775 4776
  EnsureSpace ensure_space(this);
  emit(0x66);
  emit_optional_rex_32(dst, src);
  emit(0x0F);
  emit(0x70);
  emit_sse_operand(dst, src);
  emit(shuffle);
}
4777

4778
void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) {
4779
  Register ireg = Register::from_code(reg.code());
4780 4781 4782 4783
  emit_operand(ireg, adr);
}


4784
void Assembler::emit_sse_operand(Register reg, const Operand& adr) {
4785
  emit_operand(reg, adr);
4786 4787 4788
}


4789
void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
4790
  emit(0xC0 | (dst.low_bits() << 3) | src.low_bits());
4791 4792
}

4793

4794
void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
4795
  emit(0xC0 | (dst.low_bits() << 3) | src.low_bits());
4796 4797
}

4798

4799 4800
void Assembler::emit_sse_operand(Register dst, XMMRegister src) {
  emit(0xC0 | (dst.low_bits() << 3) | src.low_bits());
4801 4802 4803 4804
}

void Assembler::emit_sse_operand(XMMRegister dst) {
  emit(0xD8 | dst.low_bits());
4805 4806
}

4807 4808 4809 4810 4811 4812
void Assembler::db(uint8_t data) {
  EnsureSpace ensure_space(this);
  emit(data);
}


4813 4814 4815 4816 4817 4818
void Assembler::dd(uint32_t data) {
  EnsureSpace ensure_space(this);
  emitl(data);
}


4819 4820 4821 4822 4823 4824
void Assembler::dq(uint64_t data) {
  EnsureSpace ensure_space(this);
  emitq(data);
}


4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845
void Assembler::dq(Label* label) {
  EnsureSpace ensure_space(this);
  if (label->is_bound()) {
    internal_reference_positions_.push_back(pc_offset());
    emitp(buffer_ + label->pos(), RelocInfo::INTERNAL_REFERENCE);
  } else {
    RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE);
    emitl(0);  // Zero for the first 32bit marks it as 64bit absolute address.
    if (label->is_linked()) {
      emitl(label->pos());
      label->link_to(pc_offset() - sizeof(int32_t));
    } else {
      DCHECK(label->is_unused());
      int32_t current = pc_offset();
      emitl(current);
      label->link_to(current);
    }
  }
}


4846
// Relocation information implementations.
4847 4848

void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
4849
  DCHECK(!RelocInfo::IsNone(rmode));
4850 4851 4852 4853
  // Don't record external references unless the heap will be serialized.
  if (rmode == RelocInfo::EXTERNAL_REFERENCE &&
      !serializer_enabled() && !emit_debug_code()) {
    return;
4854
  }
4855
  RelocInfo rinfo(pc_, rmode, data, nullptr);
4856 4857 4858
  reloc_info_writer.Write(&rinfo);
}

4859
const int RelocInfo::kApplyMask = RelocInfo::kCodeTargetMask |
4860 4861
                                  1 << RelocInfo::RUNTIME_ENTRY |
                                  1 << RelocInfo::INTERNAL_REFERENCE;
4862 4863 4864 4865 4866 4867 4868 4869

bool RelocInfo::IsCodedSpecially() {
  // The deserializer needs to know whether a pointer is specially coded.  Being
  // specially coded on x64 means that it is a relative 32 bit address, as used
  // by branch instructions.
  return (1 << rmode_) & kApplyMask;
}

4870 4871 4872 4873 4874 4875

bool RelocInfo::IsInConstantPool() {
  return false;
}


4876 4877
}  // namespace internal
}  // namespace v8
4878 4879

#endif  // V8_TARGET_ARCH_X64