[x64] Implement vcvtqsi2sd AVX instruction.

BUG=v8:4406
LOG=N

Review URL: https://codereview.chromium.org/1413013003

Cr-Commit-Position: refs/heads/master@{#31538}

src/compiler/x64/code-generator-x64.cc

@@ -945,7 +945,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       } else {
         __ movl(kScratchRegister, i.InputOperand(0));
       }
-      __ cvtqsi2sd(i.OutputDoubleRegister(), kScratchRegister);
+      __ Cvtqsi2sd(i.OutputDoubleRegister(), kScratchRegister);
       break;
     case kSSEFloat64ExtractLowWord32:
       if (instr->InputAt(0)->IsDoubleStackSlot()) {

src/x64/assembler-x64.cc

@@ -3130,6 +3130,7 @@ void Assembler::cvtlsi2ss(XMMRegister dst, Register src) {
 
 
 void Assembler::cvtqsi2sd(XMMRegister dst, const Operand& src) {
+  DCHECK(!IsEnabled(AVX));
   EnsureSpace ensure_space(this);
   emit(0xF2);
   emit_rex_64(dst, src);
@@ -3140,6 +3141,7 @@ void Assembler::cvtqsi2sd(XMMRegister dst, const Operand& src) {
 
 
 void Assembler::cvtqsi2sd(XMMRegister dst, Register src) {
+  DCHECK(!IsEnabled(AVX));
   EnsureSpace ensure_space(this);
   emit(0xF2);
   emit_rex_64(dst, src);

src/x64/assembler-x64.h

@@ -1359,6 +1359,10 @@ class Assembler : public AssemblerBase {
   void vcvtlsi2sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
     vsd(0x2a, dst, src1, src2, kF2, k0F, kW0);
   }
+  void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, Register src2) {
+    XMMRegister isrc2 = {src2.code()};
+    vsd(0x2a, dst, src1, isrc2, kF2, k0F, kW1);
+  }
   void vcvttsd2si(Register dst, XMMRegister src) {
     XMMRegister idst = {dst.code()};
     vsd(0x2c, idst, xmm0, src, kF2, k0F, kW0);

src/x64/disasm-x64.cc

@@ -1042,8 +1042,8 @@ int DisassemblerX64::AVXInstruction(byte* data) {
         AppendToBuffer(",%s", NameOfXMMRegister(regop));
         break;
       case 0x2a:
-        AppendToBuffer("vcvtlsi2sd %s,%s,", NameOfXMMRegister(regop),
-                       NameOfXMMRegister(vvvv));
+        AppendToBuffer("%s %s,%s,", vex_w() ? "vcvtqsi2sd" : "vcvtlsi2sd",
+                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
         current += PrintRightOperand(current);
         break;
       case 0x2c:

src/x64/macro-assembler-x64.cc

@@ -851,6 +851,18 @@ void MacroAssembler::Cvtlsi2sd(XMMRegister dst, const Operand& src) {
 }
 
 
+void MacroAssembler::Cvtqsi2sd(XMMRegister dst, Register src) {
+  if (CpuFeatures::IsSupported(AVX)) {
+    CpuFeatureScope scope(this, AVX);
+    vxorpd(dst, dst, dst);
+    vcvtqsi2sd(dst, dst, src);
+  } else {
+    xorpd(dst, dst);
+    cvtqsi2sd(dst, src);
+  }
+}
+
+
 void MacroAssembler::Cvttsd2si(Register dst, XMMRegister src) {
   if (CpuFeatures::IsSupported(AVX)) {
     CpuFeatureScope scope(this, AVX);
@@ -3457,7 +3469,7 @@ void MacroAssembler::LoadUint32(XMMRegister dst,
     cmpq(src, Immediate(0xffffffff));
     Assert(below_equal, kInputGPRIsExpectedToHaveUpper32Cleared);
   }
-  cvtqsi2sd(dst, src);
+  Cvtqsi2sd(dst, src);
 }
 
 

src/x64/macro-assembler-x64.h

@@ -816,6 +816,7 @@ class MacroAssembler: public Assembler {
   // xorpd to clear the dst register before cvtsi2sd to solve this issue.
   void Cvtlsi2sd(XMMRegister dst, Register src);
   void Cvtlsi2sd(XMMRegister dst, const Operand& src);
+  void Cvtqsi2sd(XMMRegister dst, Register src);
 
   void Cvttsd2si(Register dst, XMMRegister src);
   void Cvttsd2si(Register dst, const Operand& src);

test/cctest/test-assembler-x64.cc

@@ -1494,12 +1494,27 @@ TEST(AssemblerX64AVX_sd) {
     __ vucomisd(xmm5, xmm6);
     __ j(not_equal, &exit);
 
+    // Test vcvtlsi2sd
+    __ movl(rax, Immediate(17));
     __ movl(rdx, Immediate(6));
+    __ movq(rcx, V8_UINT64_C(0x4018000000000000));  // 6.0
+    __ vmovq(xmm5, rcx);
     __ vcvtlsi2sd(xmm6, xmm6, rdx);
-    __ movl(Operand(rsp, 0), Immediate(5));
+    __ vucomisd(xmm5, xmm6);
+    __ j(not_equal, &exit);
+    __ movl(Operand(rsp, 0), rdx);
     __ vcvtlsi2sd(xmm7, xmm7, Operand(rsp, 0));
-    __ vsubsd(xmm7, xmm6, xmm7);  // xmm7 is 1.0
-    __ vmulsd(xmm1, xmm1, xmm7);
+    __ vucomisd(xmm5, xmm6);
+    __ j(not_equal, &exit);
+
+    // Test vcvtqsi2sd
+    __ movl(rax, Immediate(18));
+    __ movq(rdx, V8_UINT64_C(0x2000000000000000));  // 2 << 0x3c
+    __ movq(rcx, V8_UINT64_C(0x43c0000000000000));
+    __ vmovq(xmm5, rcx);
+    __ vcvtqsi2sd(xmm6, xmm6, rdx);
+    __ vucomisd(xmm5, xmm6);
+    __ j(not_equal, &exit);
 
     __ movq(rdx, V8_INT64_C(0x3ff0000000000000));  // 1.0
     __ vmovq(xmm7, rdx);

test/cctest/test-disasm-x64.cc

@@ -552,6 +552,7 @@ TEST(DisasmX64) {
       __ vcvtsd2ss(xmm9, xmm3, Operand(rbx, rcx, times_1, 10000));
       __ vcvtlsi2sd(xmm5, xmm9, rcx);
       __ vcvtlsi2sd(xmm9, xmm3, Operand(rbx, r9, times_4, 10000));
+      __ vcvtqsi2sd(xmm5, xmm9, r11);
       __ vcvttsd2si(r9, xmm6);
       __ vcvttsd2si(rax, Operand(rbx, r9, times_4, 10000));
       __ vcvttsd2siq(rdi, xmm9);