Commit 0872d08b authored by weiliang.lin's avatar weiliang.lin Committed by Commit bot

[x64]: add cmpps/cmppd instructions

BUG=

Review-Url: https://codereview.chromium.org/2170323002
Cr-Commit-Position: refs/heads/master@{#38307}
parent 4ffe9777
......@@ -3219,28 +3219,33 @@ void Assembler::cmpps(XMMRegister dst, XMMRegister src, int8_t cmp) {
emit(cmp);
}
void Assembler::cmpeqps(XMMRegister dst, XMMRegister src) {
cmpps(dst, src, 0x0);
}
void Assembler::cmpltps(XMMRegister dst, XMMRegister src) {
cmpps(dst, src, 0x1);
}
void Assembler::cmpleps(XMMRegister dst, XMMRegister src) {
cmpps(dst, src, 0x2);
}
void Assembler::cmpneqps(XMMRegister dst, XMMRegister src) {
cmpps(dst, src, 0x4);
void Assembler::cmpps(XMMRegister dst, const Operand& src, int8_t cmp) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0xC2);
emit_sse_operand(dst, src);
emit(cmp);
}
void Assembler::cmpnltps(XMMRegister dst, XMMRegister src) {
cmpps(dst, src, 0x5);
void Assembler::cmppd(XMMRegister dst, XMMRegister src, int8_t cmp) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x66);
emit(0x0F);
emit(0xC2);
emit_sse_operand(dst, src);
emit(cmp);
}
void Assembler::cmpnleps(XMMRegister dst, XMMRegister src) {
cmpps(dst, src, 0x6);
void Assembler::cmppd(XMMRegister dst, const Operand& src, int8_t cmp) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x66);
emit(0x0F);
emit(0xC2);
emit_sse_operand(dst, src);
emit(cmp);
}
void Assembler::cvttss2si(Register dst, const Operand& src) {
......
......@@ -1172,12 +1172,26 @@ class Assembler : public AssemblerBase {
void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
void cmpps(XMMRegister dst, XMMRegister src, int8_t cmp);
void cmpeqps(XMMRegister dst, XMMRegister src);
void cmpltps(XMMRegister dst, XMMRegister src);
void cmpleps(XMMRegister dst, XMMRegister src);
void cmpneqps(XMMRegister dst, XMMRegister src);
void cmpnltps(XMMRegister dst, XMMRegister src);
void cmpnleps(XMMRegister dst, XMMRegister src);
void cmpps(XMMRegister dst, const Operand& src, int8_t cmp);
void cmppd(XMMRegister dst, XMMRegister src, int8_t cmp);
void cmppd(XMMRegister dst, const Operand& src, int8_t cmp);
#define SSE_CMP_P(instr, imm8) \
void instr##ps(XMMRegister dst, XMMRegister src) { cmpps(dst, src, imm8); } \
void instr##ps(XMMRegister dst, const Operand& src) { \
cmpps(dst, src, imm8); \
} \
void instr##pd(XMMRegister dst, XMMRegister src) { cmppd(dst, src, imm8); } \
void instr##pd(XMMRegister dst, const Operand& src) { cmppd(dst, src, imm8); }
SSE_CMP_P(cmpeq, 0x0);
SSE_CMP_P(cmplt, 0x1);
SSE_CMP_P(cmple, 0x2);
SSE_CMP_P(cmpneq, 0x4);
SSE_CMP_P(cmpnlt, 0x5);
SSE_CMP_P(cmpnle, 0x6);
#undef SSE_CMP_P
void minps(XMMRegister dst, XMMRegister src);
void minps(XMMRegister dst, const Operand& src);
......@@ -1554,6 +1568,47 @@ class Assembler : public AssemblerBase {
XMMRegister idst = {dst.code()};
vpd(0x50, idst, xmm0, src);
}
void vcmpps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int8_t cmp) {
vps(0xC2, dst, src1, src2);
emit(cmp);
}
void vcmpps(XMMRegister dst, XMMRegister src1, const Operand& src2,
int8_t cmp) {
vps(0xC2, dst, src1, src2);
emit(cmp);
}
void vcmppd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int8_t cmp) {
vpd(0xC2, dst, src1, src2);
emit(cmp);
}
void vcmppd(XMMRegister dst, XMMRegister src1, const Operand& src2,
int8_t cmp) {
vpd(0xC2, dst, src1, src2);
emit(cmp);
}
#define AVX_CMP_P(instr, imm8) \
void instr##ps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vcmpps(dst, src1, src2, imm8); \
} \
void instr##ps(XMMRegister dst, XMMRegister src1, const Operand& src2) { \
vcmpps(dst, src1, src2, imm8); \
} \
void instr##pd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vcmppd(dst, src1, src2, imm8); \
} \
void instr##pd(XMMRegister dst, XMMRegister src1, const Operand& src2) { \
vcmppd(dst, src1, src2, imm8); \
}
AVX_CMP_P(vcmpeq, 0x0);
AVX_CMP_P(vcmplt, 0x1);
AVX_CMP_P(vcmple, 0x2);
AVX_CMP_P(vcmpneq, 0x4);
AVX_CMP_P(vcmpnlt, 0x5);
AVX_CMP_P(vcmpnle, 0x6);
#undef AVX_CMP_P
void vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
void vps(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
......
......@@ -1259,6 +1259,16 @@ int DisassemblerX64::AVXInstruction(byte* data) {
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xC2: {
AppendToBuffer("vcmpps %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
const char* const pseudo_op[] = {"eq", "lt", "le", "unord",
"neq", "nlt", "nle", "ord"};
AppendToBuffer(", (%s)", pseudo_op[*current]);
current += 1;
break;
}
default:
UnimplementedInstruction();
}
......@@ -1328,6 +1338,16 @@ int DisassemblerX64::AVXInstruction(byte* data) {
current += PrintRightOperand(current);
AppendToBuffer(",%s", NameOfXMMRegister(regop));
break;
case 0xC2: {
AppendToBuffer("vcmppd %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
const char* const pseudo_op[] = {"eq", "lt", "le", "unord",
"neq", "nlt", "nle", "ord"};
AppendToBuffer(", (%s)", pseudo_op[*current]);
current += 1;
break;
}
default:
UnimplementedInstruction();
}
......@@ -1680,11 +1700,19 @@ int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) {
mnemonic = "psubd";
} else if (opcode == 0xFE) {
mnemonic = "paddd";
} else if (opcode == 0xC2) {
mnemonic = "cmppd";
} else {
UnimplementedInstruction();
}
AppendToBuffer("%s %s,", mnemonic, NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
if (opcode == 0xC2) {
const char* const pseudo_op[] = {"eq", "lt", "le", "unord",
"neq", "nlt", "nle", "ord"};
AppendToBuffer(", (%s)", pseudo_op[*current]);
current += 1;
}
}
}
} else if (group_1_prefix_ == 0xF2) {
......@@ -1896,12 +1924,12 @@ int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) {
// cmpps xmm, xmm/m128, imm8
int mod, regop, rm;
get_modrm(*current, &mod, &regop, &rm);
const char* const pseudo_op[] = {"cmpeqps", "cmpltps", "cmpleps",
"cmpunordps", "cmpneqps", "cmpnltps",
"cmpnleps", "cmpordps"};
AppendToBuffer("%s %s,%s", pseudo_op[current[1]], NameOfXMMRegister(regop),
NameOfXMMRegister(rm));
current += 2;
const char* const pseudo_op[] = {"eq", "lt", "le", "unord",
"neq", "nlt", "nle", "ord"};
AppendToBuffer("cmpps %s, ", NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
AppendToBuffer(", %s", pseudo_op[*current]);
current += 1;
} else if (opcode == 0xC6) {
// shufps xmm, xmm/m128, imm8
int mod, regop, rm;
......
......@@ -961,6 +961,18 @@ class MacroAssembler: public Assembler {
AVX_OP2_XO(Andpd, andpd)
AVX_OP2_XO(Orpd, orpd)
AVX_OP2_XO(Xorpd, xorpd)
AVX_OP2_XO(Cmpeqps, cmpeqps)
AVX_OP2_XO(Cmpltps, cmpltps)
AVX_OP2_XO(Cmpleps, cmpleps)
AVX_OP2_XO(Cmpneqps, cmpneqps)
AVX_OP2_XO(Cmpnltps, cmpnltps)
AVX_OP2_XO(Cmpnleps, cmpnleps)
AVX_OP2_XO(Cmpeqpd, cmpeqpd)
AVX_OP2_XO(Cmpltpd, cmpltpd)
AVX_OP2_XO(Cmplepd, cmplepd)
AVX_OP2_XO(Cmpneqpd, cmpneqpd)
AVX_OP2_XO(Cmpnltpd, cmpnltpd)
AVX_OP2_XO(Cmpnlepd, cmpnlepd)
AVX_OP2_X(Pcmpeqd, pcmpeqd)
AVX_OP2_WITH_TYPE(Psllq, psllq, byte)
AVX_OP2_WITH_TYPE(Psrlq, psrlq, byte)
......
......@@ -500,12 +500,33 @@ TEST(DisasmX64) {
__ pinsrd(xmm5, Operand(rax, 4), 1);
__ cmpps(xmm5, xmm1, 1);
__ cmpps(xmm5, Operand(rbx, rcx, times_4, 10000), 1);
__ cmpeqps(xmm5, xmm1);
__ cmpeqps(xmm5, Operand(rbx, rcx, times_4, 10000));
__ cmpltps(xmm5, xmm1);
__ cmpltps(xmm5, Operand(rbx, rcx, times_4, 10000));
__ cmpleps(xmm5, xmm1);
__ cmpleps(xmm5, Operand(rbx, rcx, times_4, 10000));
__ cmpneqps(xmm5, xmm1);
__ cmpneqps(xmm5, Operand(rbx, rcx, times_4, 10000));
__ cmpnltps(xmm5, xmm1);
__ cmpnltps(xmm5, Operand(rbx, rcx, times_4, 10000));
__ cmpnleps(xmm5, xmm1);
__ cmpnleps(xmm5, Operand(rbx, rcx, times_4, 10000));
__ cmppd(xmm5, xmm1, 1);
__ cmppd(xmm5, Operand(rbx, rcx, times_4, 10000), 1);
__ cmpeqpd(xmm5, xmm1);
__ cmpeqpd(xmm5, Operand(rbx, rcx, times_4, 10000));
__ cmpltpd(xmm5, xmm1);
__ cmpltpd(xmm5, Operand(rbx, rcx, times_4, 10000));
__ cmplepd(xmm5, xmm1);
__ cmplepd(xmm5, Operand(rbx, rcx, times_4, 10000));
__ cmpneqpd(xmm5, xmm1);
__ cmpneqpd(xmm5, Operand(rbx, rcx, times_4, 10000));
__ cmpnltpd(xmm5, xmm1);
__ cmpnltpd(xmm5, Operand(rbx, rcx, times_4, 10000));
__ cmpnlepd(xmm5, xmm1);
__ cmpnlepd(xmm5, Operand(rbx, rcx, times_4, 10000));
__ minps(xmm5, xmm1);
__ minps(xmm5, Operand(rdx, 4));
......@@ -628,6 +649,35 @@ TEST(DisasmX64) {
__ vpcmpeqd(xmm15, xmm0, Operand(rbx, rcx, times_4, 10000));
__ vpsllq(xmm0, xmm15, 21);
__ vpsrlq(xmm15, xmm0, 21);
__ vcmpps(xmm5, xmm4, xmm1, 1);
__ vcmpps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000), 1);
__ vcmpeqps(xmm5, xmm4, xmm1);
__ vcmpeqps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpltps(xmm5, xmm4, xmm1);
__ vcmpltps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpleps(xmm5, xmm4, xmm1);
__ vcmpleps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpneqps(xmm5, xmm4, xmm1);
__ vcmpneqps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpnltps(xmm5, xmm4, xmm1);
__ vcmpnltps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpnleps(xmm5, xmm4, xmm1);
__ vcmpnleps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmppd(xmm5, xmm4, xmm1, 1);
__ vcmppd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000), 1);
__ vcmpeqpd(xmm5, xmm4, xmm1);
__ vcmpeqpd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpltpd(xmm5, xmm4, xmm1);
__ vcmpltpd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmplepd(xmm5, xmm4, xmm1);
__ vcmplepd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpneqpd(xmm5, xmm4, xmm1);
__ vcmpneqpd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpnltpd(xmm5, xmm4, xmm1);
__ vcmpnltpd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpnlepd(xmm5, xmm4, xmm1);
__ vcmpnlepd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
}
}
......
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