disasm-ia32.cc 97.1 KB
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// Copyright 2011 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
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#include <assert.h>
#include <stdarg.h>
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#include <stdio.h>
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#if V8_TARGET_ARCH_IA32
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#include "src/base/compiler-specific.h"
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#include "src/base/strings.h"
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#include "src/codegen/ia32/sse-instr.h"
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#include "src/diagnostics/disasm.h"
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namespace disasm {

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enum OperandOrder { UNSET_OP_ORDER = 0, REG_OPER_OP_ORDER, OPER_REG_OP_ORDER };
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//------------------------------------------------------------------
// Tables
//------------------------------------------------------------------
struct ByteMnemonic {
  int b;  // -1 terminates, otherwise must be in range (0..255)
  const char* mnem;
  OperandOrder op_order_;
};

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static const ByteMnemonic two_operands_instr[] = {
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    {0x01, "add", OPER_REG_OP_ORDER},  {0x03, "add", REG_OPER_OP_ORDER},
    {0x09, "or", OPER_REG_OP_ORDER},   {0x0B, "or", REG_OPER_OP_ORDER},
    {0x13, "adc", REG_OPER_OP_ORDER},  {0x1B, "sbb", REG_OPER_OP_ORDER},
    {0x21, "and", OPER_REG_OP_ORDER},  {0x23, "and", REG_OPER_OP_ORDER},
    {0x29, "sub", OPER_REG_OP_ORDER},  {0x2A, "subb", REG_OPER_OP_ORDER},
    {0x2B, "sub", REG_OPER_OP_ORDER},  {0x31, "xor", OPER_REG_OP_ORDER},
    {0x33, "xor", REG_OPER_OP_ORDER},  {0x38, "cmpb", OPER_REG_OP_ORDER},
    {0x39, "cmp", OPER_REG_OP_ORDER},  {0x3A, "cmpb", REG_OPER_OP_ORDER},
    {0x3B, "cmp", REG_OPER_OP_ORDER},  {0x84, "test_b", REG_OPER_OP_ORDER},
    {0x85, "test", REG_OPER_OP_ORDER}, {0x86, "xchg_b", REG_OPER_OP_ORDER},
    {0x87, "xchg", REG_OPER_OP_ORDER}, {0x8A, "mov_b", REG_OPER_OP_ORDER},
    {0x8B, "mov", REG_OPER_OP_ORDER},  {0x8D, "lea", REG_OPER_OP_ORDER},
    {-1, "", UNSET_OP_ORDER}};
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static const ByteMnemonic zero_operands_instr[] = {
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    {0xC3, "ret", UNSET_OP_ORDER},   {0xC9, "leave", UNSET_OP_ORDER},
    {0x90, "nop", UNSET_OP_ORDER},   {0xF4, "hlt", UNSET_OP_ORDER},
    {0xCC, "int3", UNSET_OP_ORDER},  {0x60, "pushad", UNSET_OP_ORDER},
    {0x61, "popad", UNSET_OP_ORDER}, {0x9C, "pushfd", UNSET_OP_ORDER},
    {0x9D, "popfd", UNSET_OP_ORDER}, {0x9E, "sahf", UNSET_OP_ORDER},
    {0x99, "cdq", UNSET_OP_ORDER},   {0x9B, "fwait", UNSET_OP_ORDER},
    {0xFC, "cld", UNSET_OP_ORDER},   {0xAB, "stos", UNSET_OP_ORDER},
    {-1, "", UNSET_OP_ORDER}};
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static const ByteMnemonic call_jump_instr[] = {{0xE8, "call", UNSET_OP_ORDER},
                                               {0xE9, "jmp", UNSET_OP_ORDER},
                                               {-1, "", UNSET_OP_ORDER}};
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static const ByteMnemonic short_immediate_instr[] = {
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    {0x05, "add", UNSET_OP_ORDER}, {0x0D, "or", UNSET_OP_ORDER},
    {0x15, "adc", UNSET_OP_ORDER}, {0x25, "and", UNSET_OP_ORDER},
    {0x2D, "sub", UNSET_OP_ORDER}, {0x35, "xor", UNSET_OP_ORDER},
    {0x3D, "cmp", UNSET_OP_ORDER}, {-1, "", UNSET_OP_ORDER}};
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// Generally we don't want to generate these because they are subject to partial
// register stalls.  They are included for completeness and because the cmp
// variant is used by the RecordWrite stub.  Because it does not update the
// register it is not subject to partial register stalls.
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static ByteMnemonic byte_immediate_instr[] = {{0x0C, "or", UNSET_OP_ORDER},
                                              {0x24, "and", UNSET_OP_ORDER},
                                              {0x34, "xor", UNSET_OP_ORDER},
                                              {0x3C, "cmp", UNSET_OP_ORDER},
                                              {-1, "", UNSET_OP_ORDER}};
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static const char* const jump_conditional_mnem[] = {
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    /*0*/ "jo",  "jno", "jc",  "jnc",
    /*4*/ "jz",  "jnz", "jna", "ja",
    /*8*/ "js",  "jns", "jpe", "jpo",
    /*12*/ "jl", "jnl", "jng", "jg"};
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static const char* const set_conditional_mnem[] = {
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    /*0*/ "seto",  "setno", "setc",  "setnc",
    /*4*/ "setz",  "setnz", "setna", "seta",
    /*8*/ "sets",  "setns", "setpe", "setpo",
    /*12*/ "setl", "setnl", "setng", "setg"};
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static const char* const conditional_move_mnem[] = {
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    /*0*/ "cmovo",  "cmovno", "cmovc",  "cmovnc",
    /*4*/ "cmovz",  "cmovnz", "cmovna", "cmova",
    /*8*/ "cmovs",  "cmovns", "cmovpe", "cmovpo",
    /*12*/ "cmovl", "cmovnl", "cmovng", "cmovg"};
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enum InstructionType {
  NO_INSTR,
  ZERO_OPERANDS_INSTR,
  TWO_OPERANDS_INSTR,
  JUMP_CONDITIONAL_SHORT_INSTR,
  REGISTER_INSTR,
  MOVE_REG_INSTR,
  CALL_JUMP_INSTR,
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  SHORT_IMMEDIATE_INSTR,
  BYTE_IMMEDIATE_INSTR
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};

struct InstructionDesc {
  const char* mnem;
  InstructionType type;
  OperandOrder op_order_;
};

class InstructionTable {
 public:
  InstructionTable();
  const InstructionDesc& Get(byte x) const { return instructions_[x]; }
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  static InstructionTable* get_instance() {
    static InstructionTable table;
    return &table;
  }
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 private:
  InstructionDesc instructions_[256];
  void Clear();
  void Init();
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  void CopyTable(const ByteMnemonic bm[], InstructionType type);
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  void SetTableRange(InstructionType type, byte start, byte end,
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                     const char* mnem);
  void AddJumpConditionalShort();
};

InstructionTable::InstructionTable() {
  Clear();
  Init();
}

void InstructionTable::Clear() {
  for (int i = 0; i < 256; i++) {
    instructions_[i].mnem = "";
    instructions_[i].type = NO_INSTR;
    instructions_[i].op_order_ = UNSET_OP_ORDER;
  }
}

void InstructionTable::Init() {
  CopyTable(two_operands_instr, TWO_OPERANDS_INSTR);
  CopyTable(zero_operands_instr, ZERO_OPERANDS_INSTR);
  CopyTable(call_jump_instr, CALL_JUMP_INSTR);
  CopyTable(short_immediate_instr, SHORT_IMMEDIATE_INSTR);
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  CopyTable(byte_immediate_instr, BYTE_IMMEDIATE_INSTR);
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  AddJumpConditionalShort();
  SetTableRange(REGISTER_INSTR, 0x40, 0x47, "inc");
  SetTableRange(REGISTER_INSTR, 0x48, 0x4F, "dec");
  SetTableRange(REGISTER_INSTR, 0x50, 0x57, "push");
  SetTableRange(REGISTER_INSTR, 0x58, 0x5F, "pop");
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  SetTableRange(REGISTER_INSTR, 0x91, 0x97, "xchg eax,");  // 0x90 is nop.
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  SetTableRange(MOVE_REG_INSTR, 0xB8, 0xBF, "mov");
}

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void InstructionTable::CopyTable(const ByteMnemonic bm[],
                                 InstructionType type) {
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  for (int i = 0; bm[i].b >= 0; i++) {
    InstructionDesc* id = &instructions_[bm[i].b];
    id->mnem = bm[i].mnem;
    id->op_order_ = bm[i].op_order_;
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    DCHECK_EQ(NO_INSTR, id->type);  // Information not already entered.
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    id->type = type;
  }
}

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void InstructionTable::SetTableRange(InstructionType type, byte start, byte end,
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                                     const char* mnem) {
  for (byte b = start; b <= end; b++) {
    InstructionDesc* id = &instructions_[b];
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    DCHECK_EQ(NO_INSTR, id->type);  // Information not already entered.
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    id->mnem = mnem;
    id->type = type;
  }
}

void InstructionTable::AddJumpConditionalShort() {
  for (byte b = 0x70; b <= 0x7F; b++) {
    InstructionDesc* id = &instructions_[b];
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    DCHECK_EQ(NO_INSTR, id->type);  // Information not already entered.
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    id->mnem = jump_conditional_mnem[b & 0x0F];
    id->type = JUMP_CONDITIONAL_SHORT_INSTR;
  }
}

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namespace {
int8_t Imm8(const uint8_t* data) {
  return *reinterpret_cast<const int8_t*>(data);
}
uint8_t Imm8_U(const uint8_t* data) {
  return *reinterpret_cast<const uint8_t*>(data);
}
int16_t Imm16(const uint8_t* data) {
  return *reinterpret_cast<const int16_t*>(data);
}
uint16_t Imm16_U(const uint8_t* data) {
  return *reinterpret_cast<const uint16_t*>(data);
}
int32_t Imm32(const uint8_t* data) {
  return *reinterpret_cast<const int32_t*>(data);
}
}  // namespace

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// The IA32 disassembler implementation.
class DisassemblerIA32 {
 public:
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  DisassemblerIA32(
      const NameConverter& converter,
      Disassembler::UnimplementedOpcodeAction unimplemented_opcode_action)
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      : converter_(converter),
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        vex_byte0_(0),
        vex_byte1_(0),
        vex_byte2_(0),
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        instruction_table_(InstructionTable::get_instance()),
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        tmp_buffer_pos_(0),
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        unimplemented_opcode_action_(unimplemented_opcode_action) {
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    tmp_buffer_[0] = '\0';
  }

  virtual ~DisassemblerIA32() {}

  // Writes one disassembled instruction into 'buffer' (0-terminated).
  // Returns the length of the disassembled machine instruction in bytes.
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  int InstructionDecode(v8::base::Vector<char> buffer, byte* instruction);
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 private:
  const NameConverter& converter_;
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  byte vex_byte0_;  // 0xC4 or 0xC5
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  byte vex_byte1_;
  byte vex_byte2_;  // only for 3 bytes vex prefix
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  InstructionTable* instruction_table_;
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  v8::base::EmbeddedVector<char, 128> tmp_buffer_;
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  unsigned int tmp_buffer_pos_;
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  Disassembler::UnimplementedOpcodeAction unimplemented_opcode_action_;
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  enum {
    eax = 0,
    ecx = 1,
    edx = 2,
    ebx = 3,
    esp = 4,
    ebp = 5,
    esi = 6,
    edi = 7
  };

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  enum ShiftOpcodeExtension {
    kROL = 0,
    kROR = 1,
    kRCL = 2,
    kRCR = 3,
    kSHL = 4,
    KSHR = 5,
    kSAR = 7
  };

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  bool vex_128() {
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    DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
    byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
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    return (checked & 4) == 0;
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  }

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  bool vex_none() {
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    DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
    byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
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    return (checked & 3) == 0;
  }

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  bool vex_66() {
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    DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
    byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
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    return (checked & 3) == 1;
  }

  bool vex_f3() {
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    DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
    byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
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    return (checked & 3) == 2;
  }

  bool vex_f2() {
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    DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
    byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
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    return (checked & 3) == 3;
  }

  bool vex_w() {
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    if (vex_byte0_ == 0xC5) return false;
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    return (vex_byte2_ & 0x80) != 0;
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  }

  bool vex_0f() {
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    if (vex_byte0_ == 0xC5) return true;
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    return (vex_byte1_ & 3) == 1;
  }

  bool vex_0f38() {
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    if (vex_byte0_ == 0xC5) return false;
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    return (vex_byte1_ & 3) == 2;
  }

  bool vex_0f3a() {
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    if (vex_byte0_ == 0xC5) return false;
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    return (vex_byte1_ & 3) == 3;
  }

  int vex_vreg() {
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    DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
    byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
    return ~(checked >> 3) & 0xF;
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  }

  char float_size_code() { return "sd"[vex_w()]; }
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  const char* NameOfCPURegister(int reg) const {
    return converter_.NameOfCPURegister(reg);
  }

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  const char* NameOfByteCPURegister(int reg) const {
    return converter_.NameOfByteCPURegister(reg);
  }

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  const char* NameOfXMMRegister(int reg) const {
    return converter_.NameOfXMMRegister(reg);
  }

  const char* NameOfAddress(byte* addr) const {
    return converter_.NameOfAddress(addr);
  }

  // Disassembler helper functions.
  static void get_modrm(byte data, int* mod, int* regop, int* rm) {
    *mod = (data >> 6) & 3;
    *regop = (data & 0x38) >> 3;
    *rm = data & 7;
  }

  static void get_sib(byte data, int* scale, int* index, int* base) {
    *scale = (data >> 6) & 3;
    *index = (data >> 3) & 7;
    *base = data & 7;
  }

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  using RegisterNameMapping = const char* (DisassemblerIA32::*)(int reg) const;
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  int PrintRightOperandHelper(byte* modrmp, RegisterNameMapping register_name);
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  int PrintRightOperand(byte* modrmp);
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  int PrintRightByteOperand(byte* modrmp);
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  int PrintRightXMMOperand(byte* modrmp);
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  int PrintOperands(const char* mnem, OperandOrder op_order, byte* data);
  int PrintImmediateOp(byte* data);
  int F7Instruction(byte* data);
  int D1D3C1Instruction(byte* data);
  int JumpShort(byte* data);
  int JumpConditional(byte* data, const char* comment);
  int JumpConditionalShort(byte* data, const char* comment);
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  int SetCC(byte* data);
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  int CMov(byte* data);
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  int FPUInstruction(byte* data);
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  int MemoryFPUInstruction(int escape_opcode, int regop, byte* modrm_start);
  int RegisterFPUInstruction(int escape_opcode, byte modrm_byte);
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  int AVXInstruction(byte* data);
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  PRINTF_FORMAT(2, 3) void AppendToBuffer(const char* format, ...);
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  void UnimplementedInstruction() {
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    if (unimplemented_opcode_action_ ==
        Disassembler::kAbortOnUnimplementedOpcode) {
      FATAL("Unimplemented instruction in disassembler");
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    } else {
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      AppendToBuffer("'Unimplemented instruction'");
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    }
  }
};

void DisassemblerIA32::AppendToBuffer(const char* format, ...) {
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  v8::base::Vector<char> buf = tmp_buffer_ + tmp_buffer_pos_;
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  va_list args;
  va_start(args, format);
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  int result = v8::base::VSNPrintF(buf, format, args);
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  va_end(args);
  tmp_buffer_pos_ += result;
}

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int DisassemblerIA32::PrintRightOperandHelper(
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    byte* modrmp, RegisterNameMapping direct_register_name) {
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  int mod, regop, rm;
  get_modrm(*modrmp, &mod, &regop, &rm);
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  RegisterNameMapping register_name =
      (mod == 3) ? direct_register_name : &DisassemblerIA32::NameOfCPURegister;
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  switch (mod) {
    case 0:
      if (rm == ebp) {
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        AppendToBuffer("[0x%x]", Imm32(modrmp + 1));
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        return 5;
      } else if (rm == esp) {
        byte sib = *(modrmp + 1);
        int scale, index, base;
        get_sib(sib, &scale, &index, &base);
        if (index == esp && base == esp && scale == 0 /*times_1*/) {
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          AppendToBuffer("[%s]", (this->*register_name)(rm));
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          return 2;
        } else if (base == ebp) {
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          int32_t disp = Imm32(modrmp + 2);
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          AppendToBuffer("[%s*%d%s0x%x]", (this->*register_name)(index),
                         1 << scale, disp < 0 ? "-" : "+",
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                         disp < 0 ? -disp : disp);
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          return 6;
        } else if (index != esp && base != ebp) {
          // [base+index*scale]
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          AppendToBuffer("[%s+%s*%d]", (this->*register_name)(base),
                         (this->*register_name)(index), 1 << scale);
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          return 2;
        } else {
          UnimplementedInstruction();
          return 1;
        }
      } else {
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        AppendToBuffer("[%s]", (this->*register_name)(rm));
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        return 1;
      }
      break;
    case 1:  // fall through
    case 2:
      if (rm == esp) {
        byte sib = *(modrmp + 1);
        int scale, index, base;
        get_sib(sib, &scale, &index, &base);
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        int disp = mod == 2 ? Imm32(modrmp + 2) : Imm8(modrmp + 2);
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        if (index == base && index == rm /*esp*/ && scale == 0 /*times_1*/) {
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          AppendToBuffer("[%s%s0x%x]", (this->*register_name)(rm),
                         disp < 0 ? "-" : "+", disp < 0 ? -disp : disp);
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        } else {
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          AppendToBuffer("[%s+%s*%d%s0x%x]", (this->*register_name)(base),
                         (this->*register_name)(index), 1 << scale,
                         disp < 0 ? "-" : "+", disp < 0 ? -disp : disp);
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        }
        return mod == 2 ? 6 : 3;
      } else {
        // No sib.
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        int disp = mod == 2 ? Imm32(modrmp + 1) : Imm8(modrmp + 1);
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        AppendToBuffer("[%s%s0x%x]", (this->*register_name)(rm),
                       disp < 0 ? "-" : "+", disp < 0 ? -disp : disp);
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        return mod == 2 ? 5 : 2;
      }
      break;
    case 3:
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      AppendToBuffer("%s", (this->*register_name)(rm));
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      return 1;
    default:
      UnimplementedInstruction();
      return 1;
  }
  UNREACHABLE();
}

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int DisassemblerIA32::PrintRightOperand(byte* modrmp) {
  return PrintRightOperandHelper(modrmp, &DisassemblerIA32::NameOfCPURegister);
}

int DisassemblerIA32::PrintRightByteOperand(byte* modrmp) {
  return PrintRightOperandHelper(modrmp,
                                 &DisassemblerIA32::NameOfByteCPURegister);
}

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int DisassemblerIA32::PrintRightXMMOperand(byte* modrmp) {
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  return PrintRightOperandHelper(modrmp, &DisassemblerIA32::NameOfXMMRegister);
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}

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// Returns number of bytes used including the current *data.
// Writes instruction's mnemonic, left and right operands to 'tmp_buffer_'.
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int DisassemblerIA32::PrintOperands(const char* mnem, OperandOrder op_order,
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                                    byte* data) {
  byte modrm = *data;
  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
  int advance = 0;
  switch (op_order) {
    case REG_OPER_OP_ORDER: {
      AppendToBuffer("%s %s,", mnem, NameOfCPURegister(regop));
      advance = PrintRightOperand(data);
      break;
    }
    case OPER_REG_OP_ORDER: {
      AppendToBuffer("%s ", mnem);
      advance = PrintRightOperand(data);
      AppendToBuffer(",%s", NameOfCPURegister(regop));
      break;
    }
    default:
      UNREACHABLE();
  }
  return advance;
}

// Returns number of bytes used by machine instruction, including *data byte.
// Writes immediate instructions to 'tmp_buffer_'.
int DisassemblerIA32::PrintImmediateOp(byte* data) {
  bool sign_extension_bit = (*data & 0x02) != 0;
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  byte modrm = *(data + 1);
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  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
  const char* mnem = "Imm???";
  switch (regop) {
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    case 0:
      mnem = "add";
      break;
    case 1:
      mnem = "or";
      break;
    case 2:
      mnem = "adc";
      break;
    case 4:
      mnem = "and";
      break;
    case 5:
      mnem = "sub";
      break;
    case 6:
      mnem = "xor";
      break;
    case 7:
      mnem = "cmp";
      break;
    default:
      UnimplementedInstruction();
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  }
  AppendToBuffer("%s ", mnem);
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  int count = PrintRightOperand(data + 1);
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  if (sign_extension_bit) {
    AppendToBuffer(",0x%x", *(data + 1 + count));
    return 1 + count + 1 /*int8*/;
  } else {
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    AppendToBuffer(",0x%x", Imm32(data + 1 + count));
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    return 1 + count + 4 /*int32_t*/;
  }
}

// Returns number of bytes used, including *data.
int DisassemblerIA32::F7Instruction(byte* data) {
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  DCHECK_EQ(0xF7, *data);
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  byte modrm = *++data;
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  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
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  const char* mnem = nullptr;
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  switch (regop) {
    case 0:
      mnem = "test";
      break;
    case 2:
      mnem = "not";
      break;
    case 3:
      mnem = "neg";
      break;
    case 4:
      mnem = "mul";
      break;
    case 5:
      mnem = "imul";
      break;
    case 6:
      mnem = "div";
      break;
    case 7:
      mnem = "idiv";
      break;
    default:
      UnimplementedInstruction();
  }
  AppendToBuffer("%s ", mnem);
  int count = PrintRightOperand(data);
  if (regop == 0) {
575
    AppendToBuffer(",0x%x", Imm32(data + count));
576
    count += 4;
577
  }
578
  return 1 + count;
579 580 581 582
}

int DisassemblerIA32::D1D3C1Instruction(byte* data) {
  byte op = *data;
583
  DCHECK(op == 0xD1 || op == 0xD3 || op == 0xC1);
584
  byte modrm = *++data;
585 586 587
  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
  int imm8 = -1;
588
  const char* mnem = nullptr;
589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618
  switch (regop) {
    case kROL:
      mnem = "rol";
      break;
    case kROR:
      mnem = "ror";
      break;
    case kRCL:
      mnem = "rcl";
      break;
    case kRCR:
      mnem = "rcr";
      break;
    case kSHL:
      mnem = "shl";
      break;
    case KSHR:
      mnem = "shr";
      break;
    case kSAR:
      mnem = "sar";
      break;
    default:
      UnimplementedInstruction();
  }
  AppendToBuffer("%s ", mnem);
  int count = PrintRightOperand(data);
  if (op == 0xD1) {
    imm8 = 1;
  } else if (op == 0xC1) {
619
    imm8 = *(data + 1);
620 621 622 623 624 625
    count++;
  } else if (op == 0xD3) {
    // Shift/rotate by cl.
  }
  if (imm8 >= 0) {
    AppendToBuffer(",%d", imm8);
626
  } else {
627
    AppendToBuffer(",cl");
628
  }
629
  return 1 + count;
630 631 632 633
}

// Returns number of bytes used, including *data.
int DisassemblerIA32::JumpShort(byte* data) {
634
  DCHECK_EQ(0xEB, *data);
635
  byte b = *(data + 1);
636 637 638 639 640 641 642
  byte* dest = data + static_cast<int8_t>(b) + 2;
  AppendToBuffer("jmp %s", NameOfAddress(dest));
  return 2;
}

// Returns number of bytes used, including *data.
int DisassemblerIA32::JumpConditional(byte* data, const char* comment) {
643
  DCHECK_EQ(0x0F, *data);
644
  byte cond = *(data + 1) & 0x0F;
645
  byte* dest = data + Imm32(data + 2) + 6;
646 647
  const char* mnem = jump_conditional_mnem[cond];
  AppendToBuffer("%s %s", mnem, NameOfAddress(dest));
648
  if (comment != nullptr) {
649 650 651 652 653 654 655 656
    AppendToBuffer(", %s", comment);
  }
  return 6;  // includes 0x0F
}

// Returns number of bytes used, including *data.
int DisassemblerIA32::JumpConditionalShort(byte* data, const char* comment) {
  byte cond = *data & 0x0F;
657
  byte b = *(data + 1);
658 659 660
  byte* dest = data + static_cast<int8_t>(b) + 2;
  const char* mnem = jump_conditional_mnem[cond];
  AppendToBuffer("%s %s", mnem, NameOfAddress(dest));
661
  if (comment != nullptr) {
662 663 664 665 666
    AppendToBuffer(", %s", comment);
  }
  return 2;
}

667 668
// Returns number of bytes used, including *data.
int DisassemblerIA32::SetCC(byte* data) {
669
  DCHECK_EQ(0x0F, *data);
670
  byte cond = *(data + 1) & 0x0F;
671 672
  const char* mnem = set_conditional_mnem[cond];
  AppendToBuffer("%s ", mnem);
673
  PrintRightByteOperand(data + 2);
674
  return 3;  // Includes 0x0F.
675 676
}

677 678
// Returns number of bytes used, including *data.
int DisassemblerIA32::CMov(byte* data) {
679
  DCHECK_EQ(0x0F, *data);
680 681 682 683 684 685
  byte cond = *(data + 1) & 0x0F;
  const char* mnem = conditional_move_mnem[cond];
  int op_size = PrintOperands(mnem, REG_OPER_OP_ORDER, data + 2);
  return 2 + op_size;  // includes 0x0F
}

686
const char* sf_str[4] = {"", "rl", "ra", "ll"};
687

688 689 690
int DisassemblerIA32::AVXInstruction(byte* data) {
  byte opcode = *data;
  byte* current = data + 1;
691 692 693 694
  if (vex_66() && vex_0f38()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
695 696 697 698
      case 0x18:
        AppendToBuffer("vbroadcastss %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
699 700 701 702 703
      case 0x37:
        AppendToBuffer("vpcmpgtq %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
704 705 706 707 708
      case 0x99:
        AppendToBuffer("vfmadd132s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
709
      case 0xA9:
710 711 712 713
        AppendToBuffer("vfmadd213s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
714
      case 0xB9:
715 716 717 718
        AppendToBuffer("vfmadd231s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
719
      case 0x9B:
720 721 722 723
        AppendToBuffer("vfmsub132s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
724
      case 0xAB:
725 726 727 728
        AppendToBuffer("vfmsub213s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
729
      case 0xBB:
730 731 732 733
        AppendToBuffer("vfmsub231s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
734
      case 0x9D:
735 736 737 738
        AppendToBuffer("vfnmadd132s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
739
      case 0xAD:
740 741 742 743
        AppendToBuffer("vfnmadd213s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
744
      case 0xBD:
745 746 747 748
        AppendToBuffer("vfnmadd231s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
749
      case 0x9F:
750 751 752 753
        AppendToBuffer("vfnmsub132s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
754
      case 0xAF:
755 756 757 758
        AppendToBuffer("vfnmsub213s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
759
      case 0xBF:
760 761 762 763
        AppendToBuffer("vfnmsub231s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
764
      case 0xF7:
765 766 767 768
        AppendToBuffer("shlx %s,", NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
769 770 771 772 773 774 775 776 777
#define DECLARE_SSE_AVX_DIS_CASE(instruction, notUsed1, notUsed2, notUsed3, \
                                 opcode)                                    \
  case 0x##opcode: {                                                        \
    AppendToBuffer("v" #instruction " %s,%s,", NameOfXMMRegister(regop),    \
                   NameOfXMMRegister(vvvv));                                \
    current += PrintRightXMMOperand(current);                               \
    break;                                                                  \
  }

778
        SSSE3_INSTRUCTION_LIST(DECLARE_SSE_AVX_DIS_CASE)
779 780
        SSE4_INSTRUCTION_LIST(DECLARE_SSE_AVX_DIS_CASE)
#undef DECLARE_SSE_AVX_DIS_CASE
781 782 783 784 785 786 787 788
#define DECLARE_SSE_AVX_RM_DIS_CASE(instruction, notUsed1, notUsed2, notUsed3, \
                                    opcode)                                    \
  case 0x##opcode: {                                                           \
    AppendToBuffer("v" #instruction " %s,", NameOfXMMRegister(regop));         \
    current += PrintRightXMMOperand(current);                                  \
    break;                                                                     \
  }

789
        SSSE3_UNOP_INSTRUCTION_LIST(DECLARE_SSE_AVX_RM_DIS_CASE)
790 791
        SSE4_RM_INSTRUCTION_LIST(DECLARE_SSE_AVX_RM_DIS_CASE)
#undef DECLARE_SSE_AVX_RM_DIS_CASE
792 793 794
      default:
        UnimplementedInstruction();
    }
795 796 797 798
  } else if (vex_66() && vex_0f3a()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
799 800 801 802 803 804 805 806 807 808 809 810
      case 0x08:
        AppendToBuffer("vroundps %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%d", Imm8_U(current));
        current++;
        break;
      case 0x09:
        AppendToBuffer("vroundpd %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%d", Imm8_U(current));
        current++;
        break;
811 812 813 814
      case 0x0E:
        AppendToBuffer("vpblendw %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
815
        AppendToBuffer(",%d", Imm8_U(current));
816 817
        current++;
        break;
818 819 820 821
      case 0x0F:
        AppendToBuffer("vpalignr %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
822
        AppendToBuffer(",%d", Imm8_U(current));
823 824
        current++;
        break;
825 826 827
      case 0x14:
        AppendToBuffer("vpextrb ");
        current += PrintRightOperand(current);
828
        AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), Imm8(current));
829 830 831 832 833
        current++;
        break;
      case 0x15:
        AppendToBuffer("vpextrw ");
        current += PrintRightOperand(current);
834
        AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), Imm8(current));
835 836
        current++;
        break;
837 838 839
      case 0x16:
        AppendToBuffer("vpextrd ");
        current += PrintRightOperand(current);
840
        AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), Imm8(current));
841 842
        current++;
        break;
843 844 845 846
      case 0x20:
        AppendToBuffer("vpinsrb %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightOperand(current);
847
        AppendToBuffer(",%d", Imm8(current));
848 849
        current++;
        break;
850 851 852 853
      case 0x21:
        AppendToBuffer("vinsertps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
854
        AppendToBuffer(",%d", Imm8(current));
855 856
        current++;
        break;
857 858 859 860
      case 0x22:
        AppendToBuffer("vpinsrd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightOperand(current);
861
        AppendToBuffer(",%d", Imm8(current));
862 863
        current++;
        break;
864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881
      case 0x4A:
        AppendToBuffer("vblendvps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(*current >> 4));
        break;
      case 0x4B:
        AppendToBuffer("vblendvps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(*current >> 4));
        break;
      case 0x4C:
        AppendToBuffer("vpblendvb %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(*current >> 4));
        break;
882 883 884
      default:
        UnimplementedInstruction();
    }
885
  } else if (vex_f2() && vex_0f()) {
886 887 888
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
889 890 891 892 893 894 895 896 897 898
      case 0x10:
        AppendToBuffer("vmovsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x11:
        AppendToBuffer("vmovsd ");
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
        break;
899 900 901 902
      case 0x12:
        AppendToBuffer("vmovddup %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
903 904 905 906 907
      case 0x51:
        AppendToBuffer("vsqrtsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
908 909 910 911 912 913 914 915 916 917
      case 0x58:
        AppendToBuffer("vaddsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x59:
        AppendToBuffer("vmulsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
918
      case 0x5C:
919 920 921 922
        AppendToBuffer("vsubsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
923
      case 0x5D:
924 925 926 927
        AppendToBuffer("vminsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
928
      case 0x5E:
929 930 931 932
        AppendToBuffer("vdivsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
933
      case 0x5F:
934 935 936 937
        AppendToBuffer("vmaxsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
938 939 940
      case 0x70:
        AppendToBuffer("vpshuflw %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
941
        AppendToBuffer(",%d", Imm8(current));
942 943
        current++;
        break;
944 945 946 947 948
      case 0x7C:
        AppendToBuffer("vhaddps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
949 950 951
      default:
        UnimplementedInstruction();
    }
952 953 954 955
  } else if (vex_f3() && vex_0f()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
956 957 958 959 960 961 962 963 964 965
      case 0x10:
        AppendToBuffer("vmovss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x11:
        AppendToBuffer("vmovss ");
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
        break;
966 967 968 969
      case 0x16:
        AppendToBuffer("vmovshdup %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
970 971 972 973 974
      case 0x51:
        AppendToBuffer("vsqrtss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
975 976 977 978 979 980 981 982 983 984
      case 0x58:
        AppendToBuffer("vaddss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x59:
        AppendToBuffer("vmulss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
985
      case 0x5B:
986 987 988
        AppendToBuffer("vcvttps2dq %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
989
      case 0x5C:
990 991 992 993
        AppendToBuffer("vsubss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
994
      case 0x5D:
995 996 997 998
        AppendToBuffer("vminss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
999
      case 0x5E:
1000 1001 1002 1003
        AppendToBuffer("vdivss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1004
      case 0x5F:
1005 1006 1007 1008
        AppendToBuffer("vmaxss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1009 1010 1011 1012
      case 0x6f:
        AppendToBuffer("vmovdqu %s,", NameOfXMMRegister(regop));
        current += PrintRightOperand(current);
        break;
1013 1014 1015
      case 0x70:
        AppendToBuffer("vpshufhw %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
1016
        AppendToBuffer(",%d", Imm8(current));
1017 1018
        current++;
        break;
1019 1020 1021 1022 1023
      case 0x7f:
        AppendToBuffer("vmovdqu ");
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
        break;
1024 1025 1026 1027
      case 0xE6:
        AppendToBuffer("vcvtdq2pd %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1028 1029 1030
      default:
        UnimplementedInstruction();
    }
1031 1032 1033 1034 1035
  } else if (vex_none() && vex_0f38()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    const char* mnem = "?";
    switch (opcode) {
1036
      case 0xF2:
1037 1038 1039 1040
        AppendToBuffer("andn %s,%s,", NameOfCPURegister(regop),
                       NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        break;
1041
      case 0xF5:
1042 1043 1044 1045
        AppendToBuffer("bzhi %s,", NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
1046
      case 0xF7:
1047 1048 1049 1050
        AppendToBuffer("bextr %s,", NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
1051
      case 0xF3:
1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075
        switch (regop) {
          case 1:
            mnem = "blsr";
            break;
          case 2:
            mnem = "blsmsk";
            break;
          case 3:
            mnem = "blsi";
            break;
          default:
            UnimplementedInstruction();
        }
        AppendToBuffer("%s %s,", mnem, NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        mnem = "?";
        break;
      default:
        UnimplementedInstruction();
    }
  } else if (vex_f2() && vex_0f38()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
1076
      case 0xF5:
1077 1078 1079 1080
        AppendToBuffer("pdep %s,%s,", NameOfCPURegister(regop),
                       NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        break;
1081
      case 0xF6:
1082 1083 1084 1085
        AppendToBuffer("mulx %s,%s,", NameOfCPURegister(regop),
                       NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        break;
1086
      case 0xF7:
1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097
        AppendToBuffer("shrx %s,", NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
      default:
        UnimplementedInstruction();
    }
  } else if (vex_f3() && vex_0f38()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
1098
      case 0xF5:
1099 1100 1101 1102
        AppendToBuffer("pext %s,%s,", NameOfCPURegister(regop),
                       NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        break;
1103
      case 0xF7:
1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114
        AppendToBuffer("sarx %s,", NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
      default:
        UnimplementedInstruction();
    }
  } else if (vex_f2() && vex_0f3a()) {
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
1115
      case 0xF0:
1116 1117
        AppendToBuffer("rorx %s,", NameOfCPURegister(regop));
        current += PrintRightOperand(current);
1118
        AppendToBuffer(",%d", *current & 0x1F);
1119 1120 1121 1122 1123
        current += 1;
        break;
      default:
        UnimplementedInstruction();
    }
1124 1125 1126 1127
  } else if (vex_none() && vex_0f()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
1128 1129 1130 1131
      case 0x10:
        AppendToBuffer("vmovups %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1132 1133 1134 1135 1136
      case 0x11:
        AppendToBuffer("vmovups ");
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
        break;
1137
      case 0x12:
1138 1139 1140 1141 1142 1143 1144
        if (mod == 0b11) {
          AppendToBuffer("vmovhlps %s,%s,", NameOfXMMRegister(regop),
                         NameOfXMMRegister(vvvv));
        } else {
          AppendToBuffer("vmovlps %s,%s,", NameOfXMMRegister(regop),
                         NameOfXMMRegister(vvvv));
        }
1145 1146
        current += PrintRightXMMOperand(current);
        break;
1147 1148 1149 1150 1151
      case 0x13:
        AppendToBuffer("vmovlps ");
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
        break;
1152 1153 1154 1155 1156
      case 0x14:
        AppendToBuffer("vunpcklps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1157 1158 1159 1160
      case 0x16:
        AppendToBuffer("vmovhps %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1161 1162 1163 1164 1165
      case 0x17:
        AppendToBuffer("vmovhps ");
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
        break;
1166 1167 1168 1169
      case 0x28:
        AppendToBuffer("vmovaps %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1170 1171 1172 1173 1174
      case 0x50:
        AppendToBuffer("vmovmskps %s,%s", NameOfCPURegister(regop),
                       NameOfXMMRegister(rm));
        current++;
        break;
1175 1176 1177 1178
      case 0x51:
        AppendToBuffer("vsqrtps %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1179 1180 1181 1182 1183 1184 1185 1186
      case 0x52:
        AppendToBuffer("vrsqrtps %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
      case 0x53:
        AppendToBuffer("vrcpps %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1187 1188
      case 0x54:
        AppendToBuffer("vandps %s,%s,", NameOfXMMRegister(regop),
1189 1190 1191 1192 1193
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x55:
        AppendToBuffer("vandnps %s,%s,", NameOfXMMRegister(regop),
1194 1195 1196
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1197 1198 1199 1200 1201
      case 0x56:
        AppendToBuffer("vorps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1202 1203 1204 1205 1206
      case 0x57:
        AppendToBuffer("vxorps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1207 1208 1209 1210 1211 1212 1213 1214 1215 1216
      case 0x58:
        AppendToBuffer("vaddps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x59:
        AppendToBuffer("vmulps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1217 1218 1219 1220
      case 0x5A:
        AppendToBuffer("vcvtps2pd %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1221 1222 1223 1224
      case 0x5B:
        AppendToBuffer("vcvtdq2ps %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244
      case 0x5C:
        AppendToBuffer("vsubps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5D:
        AppendToBuffer("vminps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5E:
        AppendToBuffer("vdivps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5F:
        AppendToBuffer("vmaxps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1245 1246 1247 1248 1249 1250 1251 1252 1253 1254
      case 0xC2: {
        const char* const pseudo_op[] = {"eq",  "lt",  "le",  "unord",
                                         "neq", "nlt", "nle", "ord"};
        AppendToBuffer("vcmpps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(", (%s)", pseudo_op[*current]);
        current++;
        break;
      }
1255 1256 1257 1258 1259 1260 1261
      case 0xC6:
        AppendToBuffer("vshufps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(", %d", (*current) & 3);
        current += 1;
        break;
1262 1263 1264 1265 1266 1267 1268
      default:
        UnimplementedInstruction();
    }
  } else if (vex_66() && vex_0f()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
1269 1270 1271 1272
      case 0x10:
        AppendToBuffer("vmovupd %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1273 1274 1275 1276
      case 0x28:
        AppendToBuffer("vmovapd %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1277 1278 1279 1280 1281
      case 0x50:
        AppendToBuffer("vmovmskpd %s,%s", NameOfCPURegister(regop),
                       NameOfXMMRegister(rm));
        current++;
        break;
1282 1283 1284 1285 1286
      case 0x54:
        AppendToBuffer("vandpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1287 1288 1289 1290 1291 1292 1293 1294 1295 1296
      case 0x55:
        AppendToBuffer("vandnpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x56:
        AppendToBuffer("vorpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1297 1298 1299 1300 1301
      case 0x57:
        AppendToBuffer("vxorpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1302 1303 1304 1305 1306 1307 1308 1309 1310 1311
      case 0x58:
        AppendToBuffer("vaddpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x59:
        AppendToBuffer("vmulpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1312 1313 1314 1315
      case 0x5A:
        AppendToBuffer("vcvtpd2ps %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335
      case 0x5C:
        AppendToBuffer("vsubpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5D:
        AppendToBuffer("vminpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5E:
        AppendToBuffer("vdivpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5F:
        AppendToBuffer("vmaxpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1336 1337 1338
      case 0x6E:
        AppendToBuffer("vmovd %s,", NameOfXMMRegister(regop));
        current += PrintRightOperand(current);
1339 1340 1341 1342
        break;
      case 0x6f:
        AppendToBuffer("vmovdqa %s,", NameOfXMMRegister(regop));
        current += PrintRightOperand(current);
1343 1344 1345 1346
        break;
      case 0x70:
        AppendToBuffer("vpshufd %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
1347
        AppendToBuffer(",%d", Imm8(current));
1348 1349
        current++;
        break;
1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361
      case 0x71:
        AppendToBuffer("vps%sw %s,%s", sf_str[regop / 2],
                       NameOfXMMRegister(vvvv), NameOfXMMRegister(rm));
        current++;
        AppendToBuffer(",%u", *current++);
        break;
      case 0x72:
        AppendToBuffer("vps%sd %s,%s", sf_str[regop / 2],
                       NameOfXMMRegister(vvvv), NameOfXMMRegister(rm));
        current++;
        AppendToBuffer(",%u", *current++);
        break;
1362 1363 1364 1365 1366 1367
      case 0x73:
        AppendToBuffer("vps%sq %s,%s", sf_str[regop / 2],
                       NameOfXMMRegister(vvvv), NameOfXMMRegister(rm));
        current++;
        AppendToBuffer(",%u", *current++);
        break;
1368 1369 1370 1371 1372
      case 0x7E:
        AppendToBuffer("vmovd ");
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
        break;
1373 1374 1375 1376 1377 1378 1379 1380 1381
      case 0xC2: {
        const char* const pseudo_op[] = {"eq", "lt", "le", "unord", "neq"};
        AppendToBuffer("vcmppd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(", (%s)", pseudo_op[*current]);
        current++;
        break;
      }
1382 1383 1384 1385
      case 0xC4:
        AppendToBuffer("vpinsrw %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightOperand(current);
1386
        AppendToBuffer(",%d", Imm8(current));
1387 1388
        current++;
        break;
1389 1390 1391 1392 1393 1394 1395
      case 0xC6:
        AppendToBuffer("vshufpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%d", Imm8(current));
        current++;
        break;
1396 1397 1398 1399 1400
      case 0xD7:
        AppendToBuffer("vpmovmskb %s,%s", NameOfCPURegister(regop),
                       NameOfXMMRegister(rm));
        current++;
        break;
1401 1402 1403 1404
      case 0xE6:
        AppendToBuffer("vcvttpd2dq %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1405 1406 1407 1408 1409 1410 1411 1412 1413 1414
#define DECLARE_SSE_AVX_DIS_CASE(instruction, notUsed1, notUsed2, opcode) \
  case 0x##opcode: {                                                      \
    AppendToBuffer("v" #instruction " %s,%s,", NameOfXMMRegister(regop),  \
                   NameOfXMMRegister(vvvv));                              \
    current += PrintRightXMMOperand(current);                             \
    break;                                                                \
  }

        SSE2_INSTRUCTION_LIST(DECLARE_SSE_AVX_DIS_CASE)
#undef DECLARE_SSE_AVX_DIS_CASE
1415 1416 1417
      default:
        UnimplementedInstruction();
    }
1418 1419 1420 1421 1422 1423 1424
  } else {
    UnimplementedInstruction();
  }

  return static_cast<int>(current - data);
}

1425 1426
// Returns number of bytes used, including *data.
int DisassemblerIA32::FPUInstruction(byte* data) {
1427
  byte escape_opcode = *data;
1428
  DCHECK_EQ(0xD8, escape_opcode & 0xF8);
1429
  byte modrm_byte = *(data + 1);
1430 1431 1432 1433

  if (modrm_byte >= 0xC0) {
    return RegisterFPUInstruction(escape_opcode, modrm_byte);
  } else {
1434
    return MemoryFPUInstruction(escape_opcode, modrm_byte, data + 1);
1435 1436 1437
  }
}

1438
int DisassemblerIA32::MemoryFPUInstruction(int escape_opcode, int modrm_byte,
1439 1440 1441 1442
                                           byte* modrm_start) {
  const char* mnem = "?";
  int regop = (modrm_byte >> 3) & 0x7;  // reg/op field of modrm byte.
  switch (escape_opcode) {
1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458
    case 0xD9:
      switch (regop) {
        case 0:
          mnem = "fld_s";
          break;
        case 2:
          mnem = "fst_s";
          break;
        case 3:
          mnem = "fstp_s";
          break;
        case 7:
          mnem = "fstcw";
          break;
        default:
          UnimplementedInstruction();
1459
      }
1460 1461
      break;

1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477
    case 0xDB:
      switch (regop) {
        case 0:
          mnem = "fild_s";
          break;
        case 1:
          mnem = "fisttp_s";
          break;
        case 2:
          mnem = "fist_s";
          break;
        case 3:
          mnem = "fistp_s";
          break;
        default:
          UnimplementedInstruction();
1478
      }
1479 1480
      break;

1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496
    case 0xDD:
      switch (regop) {
        case 0:
          mnem = "fld_d";
          break;
        case 1:
          mnem = "fisttp_d";
          break;
        case 2:
          mnem = "fst_d";
          break;
        case 3:
          mnem = "fstp_d";
          break;
        default:
          UnimplementedInstruction();
1497 1498 1499
      }
      break;

1500 1501 1502 1503 1504 1505 1506 1507 1508 1509
    case 0xDF:
      switch (regop) {
        case 5:
          mnem = "fild_d";
          break;
        case 7:
          mnem = "fistp_d";
          break;
        default:
          UnimplementedInstruction();
1510 1511 1512
      }
      break;

1513 1514
    default:
      UnimplementedInstruction();
1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527
  }
  AppendToBuffer("%s ", mnem);
  int count = PrintRightOperand(modrm_start);
  return count + 1;
}

int DisassemblerIA32::RegisterFPUInstruction(int escape_opcode,
                                             byte modrm_byte) {
  bool has_register = false;  // Is the FPU register encoded in modrm_byte?
  const char* mnem = "?";

  switch (escape_opcode) {
    case 0xD8:
1528 1529
      has_register = true;
      switch (modrm_byte & 0xF8) {
1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543
        case 0xC0:
          mnem = "fadd_i";
          break;
        case 0xE0:
          mnem = "fsub_i";
          break;
        case 0xC8:
          mnem = "fmul_i";
          break;
        case 0xF0:
          mnem = "fdiv_i";
          break;
        default:
          UnimplementedInstruction();
1544
      }
1545 1546 1547 1548
      break;

    case 0xD9:
      switch (modrm_byte & 0xF8) {
1549 1550 1551 1552
        case 0xC0:
          mnem = "fld";
          has_register = true;
          break;
1553 1554 1555 1556 1557 1558
        case 0xC8:
          mnem = "fxch";
          has_register = true;
          break;
        default:
          switch (modrm_byte) {
1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611
            case 0xE0:
              mnem = "fchs";
              break;
            case 0xE1:
              mnem = "fabs";
              break;
            case 0xE4:
              mnem = "ftst";
              break;
            case 0xE8:
              mnem = "fld1";
              break;
            case 0xEB:
              mnem = "fldpi";
              break;
            case 0xED:
              mnem = "fldln2";
              break;
            case 0xEE:
              mnem = "fldz";
              break;
            case 0xF0:
              mnem = "f2xm1";
              break;
            case 0xF1:
              mnem = "fyl2x";
              break;
            case 0xF4:
              mnem = "fxtract";
              break;
            case 0xF5:
              mnem = "fprem1";
              break;
            case 0xF7:
              mnem = "fincstp";
              break;
            case 0xF8:
              mnem = "fprem";
              break;
            case 0xFC:
              mnem = "frndint";
              break;
            case 0xFD:
              mnem = "fscale";
              break;
            case 0xFE:
              mnem = "fsin";
              break;
            case 0xFF:
              mnem = "fcos";
              break;
            default:
              UnimplementedInstruction();
1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627
          }
      }
      break;

    case 0xDA:
      if (modrm_byte == 0xE9) {
        mnem = "fucompp";
      } else {
        UnimplementedInstruction();
      }
      break;

    case 0xDB:
      if ((modrm_byte & 0xF8) == 0xE8) {
        mnem = "fucomi";
        has_register = true;
1628
      } else if (modrm_byte == 0xE2) {
1629
        mnem = "fclex";
1630 1631
      } else if (modrm_byte == 0xE3) {
        mnem = "fninit";
1632 1633 1634 1635 1636 1637 1638 1639
      } else {
        UnimplementedInstruction();
      }
      break;

    case 0xDC:
      has_register = true;
      switch (modrm_byte & 0xF8) {
1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653
        case 0xC0:
          mnem = "fadd";
          break;
        case 0xE8:
          mnem = "fsub";
          break;
        case 0xC8:
          mnem = "fmul";
          break;
        case 0xF8:
          mnem = "fdiv";
          break;
        default:
          UnimplementedInstruction();
1654 1655 1656 1657 1658 1659
      }
      break;

    case 0xDD:
      has_register = true;
      switch (modrm_byte & 0xF8) {
1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670
        case 0xC0:
          mnem = "ffree";
          break;
        case 0xD0:
          mnem = "fst";
          break;
        case 0xD8:
          mnem = "fstp";
          break;
        default:
          UnimplementedInstruction();
1671 1672 1673 1674
      }
      break;

    case 0xDE:
1675
      if (modrm_byte == 0xD9) {
1676 1677 1678 1679
        mnem = "fcompp";
      } else {
        has_register = true;
        switch (modrm_byte & 0xF8) {
1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693
          case 0xC0:
            mnem = "faddp";
            break;
          case 0xE8:
            mnem = "fsubp";
            break;
          case 0xC8:
            mnem = "fmulp";
            break;
          case 0xF8:
            mnem = "fdivp";
            break;
          default:
            UnimplementedInstruction();
1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706
        }
      }
      break;

    case 0xDF:
      if (modrm_byte == 0xE0) {
        mnem = "fnstsw_ax";
      } else if ((modrm_byte & 0xF8) == 0xE8) {
        mnem = "fucomip";
        has_register = true;
      }
      break;

1707 1708
    default:
      UnimplementedInstruction();
1709 1710 1711 1712 1713
  }

  if (has_register) {
    AppendToBuffer("%s st%d", mnem, modrm_byte & 0x7);
  } else {
1714
    AppendToBuffer("%s", mnem);
1715 1716 1717 1718 1719
  }
  return 2;
}

// Mnemonics for instructions 0xF0 byte.
1720
// Returns nullptr if the instruction is not handled here.
1721 1722
static const char* F0Mnem(byte f0byte) {
  switch (f0byte) {
1723 1724
    case 0x0B:
      return "ud2";
1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748
    case 0x18:
      return "prefetch";
    case 0xA2:
      return "cpuid";
    case 0xBE:
      return "movsx_b";
    case 0xBF:
      return "movsx_w";
    case 0xB6:
      return "movzx_b";
    case 0xB7:
      return "movzx_w";
    case 0xAF:
      return "imul";
    case 0xA4:
      return "shld";
    case 0xA5:
      return "shld";
    case 0xAD:
      return "shrd";
    case 0xAC:
      return "shrd";  // 3-operand version.
    case 0xAB:
      return "bts";
1749 1750 1751 1752
    case 0xB0:
      return "cmpxchg_b";
    case 0xB1:
      return "cmpxchg";
1753 1754
    case 0xBC:
      return "bsf";
1755 1756
    case 0xBD:
      return "bsr";
1757 1758
    case 0xC7:
      return "cmpxchg8b";
1759 1760
    default:
      return nullptr;
1761 1762 1763
  }
}

1764
// Disassembled instruction '*instr' and writes it into 'out_buffer'.
1765
int DisassemblerIA32::InstructionDecode(v8::base::Vector<char> out_buffer,
1766 1767 1768 1769
                                        byte* instr) {
  tmp_buffer_pos_ = 0;  // starting to write as position 0
  byte* data = instr;
  // Check for hints.
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  const char* branch_hint = nullptr;
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  // We use these two prefixes only with branch prediction
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  if (*data == 0x3E /*ds*/) {
    branch_hint = "predicted taken";
    data++;
  } else if (*data == 0x2E /*cs*/) {
    branch_hint = "predicted not taken";
    data++;
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  } else if (*data == 0xC4 && *(data + 1) >= 0xC0) {
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    vex_byte0_ = *data;
    vex_byte1_ = *(data + 1);
    vex_byte2_ = *(data + 2);
    data += 3;
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  } else if (*data == 0xC5 && *(data + 1) >= 0xC0) {
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    vex_byte0_ = *data;
    vex_byte1_ = *(data + 1);
    data += 2;
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  } else if (*data == 0xF0 /*lock*/) {
    AppendToBuffer("lock ");
    data++;
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  }
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  bool processed = true;  // Will be set to false if the current instruction
                          // is not in 'instructions' table.
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  // Decode AVX instructions.
  if (vex_byte0_ != 0) {
    data += AVXInstruction(data);
  } else {
    const InstructionDesc& idesc = instruction_table_->Get(*data);
    switch (idesc.type) {
      case ZERO_OPERANDS_INSTR:
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        AppendToBuffer("%s", idesc.mnem);
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        data++;
        break;
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      case TWO_OPERANDS_INSTR:
        data++;
        data += PrintOperands(idesc.mnem, idesc.op_order_, data);
        break;
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      case JUMP_CONDITIONAL_SHORT_INSTR:
        data += JumpConditionalShort(data, branch_hint);
        break;
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      case REGISTER_INSTR:
        AppendToBuffer("%s %s", idesc.mnem, NameOfCPURegister(*data & 0x07));
        data++;
        break;
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      case MOVE_REG_INSTR: {
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        byte* addr = reinterpret_cast<byte*>(Imm32(data + 1));
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        AppendToBuffer("mov %s,%s", NameOfCPURegister(*data & 0x07),
                       NameOfAddress(addr));
        data += 5;
        break;
      }
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      case CALL_JUMP_INSTR: {
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        byte* addr = data + Imm32(data + 1) + 5;
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        AppendToBuffer("%s %s", idesc.mnem, NameOfAddress(addr));
        data += 5;
        break;
      }
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      case SHORT_IMMEDIATE_INSTR: {
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        byte* addr = reinterpret_cast<byte*>(Imm32(data + 1));
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        AppendToBuffer("%s eax,%s", idesc.mnem, NameOfAddress(addr));
        data += 5;
        break;
      }
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      case BYTE_IMMEDIATE_INSTR: {
        AppendToBuffer("%s al,0x%x", idesc.mnem, data[1]);
        data += 2;
        break;
      }
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      case NO_INSTR:
        processed = false;
        break;
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      default:
        UNIMPLEMENTED();  // This type is not implemented.
    }
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  }
  //----------------------------
  if (!processed) {
    switch (*data) {
      case 0xC2:
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        AppendToBuffer("ret 0x%x", Imm16_U(data + 1));
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        data += 3;
        break;

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      case 0x6B: {
        data++;
        data += PrintOperands("imul", REG_OPER_OP_ORDER, data);
        AppendToBuffer(",%d", *data);
        data++;
      } break;

      case 0x69: {
        data++;
        data += PrintOperands("imul", REG_OPER_OP_ORDER, data);
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        AppendToBuffer(",%d", Imm32(data));
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        data += 4;
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      } break;
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      case 0xF6: {
        data++;
        int mod, regop, rm;
        get_modrm(*data, &mod, &regop, &rm);
        if (regop == eax) {
          AppendToBuffer("test_b ");
          data += PrintRightByteOperand(data);
          int32_t imm = *data;
          AppendToBuffer(",0x%x", imm);
          data++;
        } else {
          UnimplementedInstruction();
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        }
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      } break;
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      case 0x81:  // fall through
      case 0x83:  // 0x81 with sign extension bit set
        data += PrintImmediateOp(data);
        break;

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      case 0x0F: {
        byte f0byte = data[1];
        const char* f0mnem = F0Mnem(f0byte);
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        int mod, regop, rm;
        // Not every instruction use this, and it is safe to index data+2 as all
        // instructions are at least 3 bytes with operands.
        get_modrm(*(data + 2), &mod, &regop, &rm);
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        if (f0byte == 0x12) {
          data += 2;
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          if (mod == 0b11) {
            AppendToBuffer("movhlps %s,", NameOfXMMRegister(regop));
          } else {
            AppendToBuffer("movlps %s,", NameOfXMMRegister(regop));
          }
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          data += PrintRightXMMOperand(data);
        } else if (f0byte == 0x13) {
          data += 2;
          AppendToBuffer("movlps ");
          data += PrintRightXMMOperand(data);
          AppendToBuffer(",%s", NameOfXMMRegister(regop));
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        } else if (f0byte == 0x14) {
          data += 2;
          AppendToBuffer("unpcklps %s,", NameOfXMMRegister(regop));
          data += PrintRightXMMOperand(data);
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        } else if (f0byte == 0x16) {
          data += 2;
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          AppendToBuffer("movhps %s,", NameOfXMMRegister(regop));
          data += PrintRightXMMOperand(data);
        } else if (f0byte == 0x17) {
          data += 2;
          AppendToBuffer("movhps ");
          data += PrintRightXMMOperand(data);
          AppendToBuffer(",%s", NameOfXMMRegister(regop));
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        } else if (f0byte == 0x18) {
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          data += 2;
          const char* suffix[] = {"nta", "1", "2", "3"};
          AppendToBuffer("%s%s ", f0mnem, suffix[regop & 0x03]);
          data += PrintRightOperand(data);
        } else if (f0byte == 0x1F && data[2] == 0) {
          AppendToBuffer("nop");  // 3 byte nop.
          data += 3;
        } else if (f0byte == 0x1F && data[2] == 0x40 && data[3] == 0) {
          AppendToBuffer("nop");  // 4 byte nop.
          data += 4;
        } else if (f0byte == 0x1F && data[2] == 0x44 && data[3] == 0 &&
                   data[4] == 0) {
          AppendToBuffer("nop");  // 5 byte nop.
          data += 5;
        } else if (f0byte == 0x1F && data[2] == 0x80 && data[3] == 0 &&
                   data[4] == 0 && data[5] == 0 && data[6] == 0) {
          AppendToBuffer("nop");  // 7 byte nop.
          data += 7;
        } else if (f0byte == 0x1F && data[2] == 0x84 && data[3] == 0 &&
                   data[4] == 0 && data[5] == 0 && data[6] == 0 &&
                   data[7] == 0) {
          AppendToBuffer("nop");  // 8 byte nop.
          data += 8;
        } else if (f0byte == 0x0B || f0byte == 0xA2 || f0byte == 0x31) {
          AppendToBuffer("%s", f0mnem);
          data += 2;
        } else if (f0byte == 0x28) {
          data += 2;
          AppendToBuffer("movaps %s,%s", NameOfXMMRegister(regop),
                         NameOfXMMRegister(rm));
          data++;
        } else if (f0byte == 0x10 || f0byte == 0x11) {
          data += 2;
          // movups xmm, xmm/m128
          // movups xmm/m128, xmm
          AppendToBuffer("movups ");
          if (f0byte == 0x11) {
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            data += PrintRightXMMOperand(data);
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            AppendToBuffer(",%s", NameOfXMMRegister(regop));
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          } else {
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            AppendToBuffer("%s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
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          }
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        } else if (f0byte == 0x2E) {
          data += 2;
          AppendToBuffer("ucomiss %s,", NameOfXMMRegister(regop));
          data += PrintRightXMMOperand(data);
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        } else if (f0byte >= 0x51 && f0byte <= 0x5F) {
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          const char* const pseudo_op[] = {
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              "sqrtps",   "rsqrtps", "rcpps", "andps", "andnps",
              "orps",     "xorps",   "addps", "mulps", "cvtps2pd",
              "cvtdq2ps", "subps",   "minps", "divps", "maxps",
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          };
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          data += 2;
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          AppendToBuffer("%s %s,", pseudo_op[f0byte - 0x51],
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                         NameOfXMMRegister(regop));
          data += PrintRightXMMOperand(data);
        } else if (f0byte == 0x50) {
          data += 2;
          AppendToBuffer("movmskps %s,%s", NameOfCPURegister(regop),
                         NameOfXMMRegister(rm));
          data++;
1994 1995 1996 1997 1998 1999
        } else if (f0byte == 0xC0) {
          data += 2;
          data += PrintOperands("xadd_b", OPER_REG_OP_ORDER, data);
        } else if (f0byte == 0xC1) {
          data += 2;
          data += PrintOperands("xadd", OPER_REG_OP_ORDER, data);
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        } else if (f0byte == 0xC2) {
          data += 2;
          const char* const pseudo_op[] = {"eq",  "lt",  "le",  "unord",
                                           "neq", "nlt", "nle", "ord"};
          AppendToBuffer("cmpps %s, ", NameOfXMMRegister(regop));
          data += PrintRightXMMOperand(data);
          AppendToBuffer(", (%s)", pseudo_op[*data]);
          data++;
        } else if (f0byte == 0xC6) {
          // shufps xmm, xmm/m128, imm8
          data += 2;
          int8_t imm8 = static_cast<int8_t>(data[1]);
          AppendToBuffer("shufps %s,%s,%d", NameOfXMMRegister(rm),
                         NameOfXMMRegister(regop), static_cast<int>(imm8));
          data += 2;
        } else if (f0byte >= 0xC8 && f0byte <= 0xCF) {
          // bswap
          data += 2;
          int reg = f0byte - 0xC8;
          AppendToBuffer("bswap %s", NameOfCPURegister(reg));
        } else if ((f0byte & 0xF0) == 0x80) {
          data += JumpConditional(data, branch_hint);
        } else if (f0byte == 0xBE || f0byte == 0xBF || f0byte == 0xB6 ||
                   f0byte == 0xB7 || f0byte == 0xAF) {
          data += 2;
          data += PrintOperands(f0mnem, REG_OPER_OP_ORDER, data);
        } else if ((f0byte & 0xF0) == 0x90) {
          data += SetCC(data);
        } else if ((f0byte & 0xF0) == 0x40) {
          data += CMov(data);
        } else if (f0byte == 0xA4 || f0byte == 0xAC) {
          // shld, shrd
          data += 2;
          AppendToBuffer("%s ", f0mnem);
          int8_t imm8 = static_cast<int8_t>(data[1]);
          data += 2;
          AppendToBuffer("%s,%s,%d", NameOfCPURegister(rm),
                         NameOfCPURegister(regop), static_cast<int>(imm8));
        } else if (f0byte == 0xAB || f0byte == 0xA5 || f0byte == 0xAD) {
          // shrd_cl, shld_cl, bts
          data += 2;
          AppendToBuffer("%s ", f0mnem);
          data += PrintRightOperand(data);
          if (f0byte == 0xAB) {
            AppendToBuffer(",%s", NameOfCPURegister(regop));
          } else {
            AppendToBuffer(",%s,cl", NameOfCPURegister(regop));
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          }
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        } else if (f0byte == 0xB0) {
          // cmpxchg_b
          data += 2;
          AppendToBuffer("%s ", f0mnem);
          data += PrintRightOperand(data);
          AppendToBuffer(",%s", NameOfByteCPURegister(regop));
        } else if (f0byte == 0xB1) {
          // cmpxchg
          data += 2;
          data += PrintOperands(f0mnem, OPER_REG_OP_ORDER, data);
        } else if (f0byte == 0xBC) {
          data += 2;
          AppendToBuffer("%s %s,", f0mnem, NameOfCPURegister(regop));
          data += PrintRightOperand(data);
        } else if (f0byte == 0xBD) {
          data += 2;
          AppendToBuffer("%s %s,", f0mnem, NameOfCPURegister(regop));
          data += PrintRightOperand(data);
        } else if (f0byte == 0xC7) {
          // cmpxchg8b
          data += 2;
          AppendToBuffer("%s ", f0mnem);
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          data += PrintRightOperand(data);
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        } else if (f0byte == 0xAE && (data[2] & 0xF8) == 0xF0) {
          AppendToBuffer("mfence");
          data += 3;
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        } else if (f0byte == 0xAE && (data[2] & 0xF8) == 0xE8) {
          AppendToBuffer("lfence");
          data += 3;
        } else {
          UnimplementedInstruction();
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          data += 1;
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        }
2081
      } break;
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      case 0x8F: {
        data++;
        int mod, regop, rm;
        get_modrm(*data, &mod, &regop, &rm);
        if (regop == eax) {
          AppendToBuffer("pop ");
          data += PrintRightOperand(data);
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        }
2091
      } break;
2092

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      case 0xFF: {
        data++;
        int mod, regop, rm;
        get_modrm(*data, &mod, &regop, &rm);
        const char* mnem = nullptr;
        switch (regop) {
          case esi:
            mnem = "push";
            break;
          case eax:
            mnem = "inc";
            break;
          case ecx:
            mnem = "dec";
            break;
          case edx:
            mnem = "call";
            break;
          case esp:
            mnem = "jmp";
            break;
          default:
            mnem = "???";
        }
        AppendToBuffer("%s ", mnem);
        data += PrintRightOperand(data);
      } break;

      case 0xC7:  // imm32, fall through
      case 0xC6:  // imm8
      {
        bool is_byte = *data == 0xC6;
        data++;
        if (is_byte) {
          AppendToBuffer("%s ", "mov_b");
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          data += PrintRightByteOperand(data);
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          int32_t imm = *data;
          AppendToBuffer(",0x%x", imm);
          data++;
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        } else {
          AppendToBuffer("%s ", "mov");
          data += PrintRightOperand(data);
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          AppendToBuffer(",0x%x", Imm32(data));
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          data += 4;
2137
        }
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      } break;

      case 0x80: {
        data++;
        int mod, regop, rm;
        get_modrm(*data, &mod, &regop, &rm);
        const char* mnem = nullptr;
        switch (regop) {
          case 5:
            mnem = "subb";
            break;
          case 7:
            mnem = "cmpb";
            break;
          default:
            UnimplementedInstruction();
        }
        AppendToBuffer("%s ", mnem);
        data += PrintRightByteOperand(data);
        int32_t imm = *data;
        AppendToBuffer(",0x%x", imm);
        data++;
      } break;
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2162 2163
      case 0x88:  // 8bit, fall through
      case 0x89:  // 32bit
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      {
        bool is_byte = *data == 0x88;
        int mod, regop, rm;
        data++;
        get_modrm(*data, &mod, &regop, &rm);
        if (is_byte) {
          AppendToBuffer("%s ", "mov_b");
          data += PrintRightByteOperand(data);
          AppendToBuffer(",%s", NameOfByteCPURegister(regop));
        } else {
          AppendToBuffer("%s ", "mov");
          data += PrintRightOperand(data);
          AppendToBuffer(",%s", NameOfCPURegister(regop));
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        }
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      } break;
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      case 0x66:  // prefix
2181
        while (*data == 0x66) data++;
2182
        if (*data == 0xF && data[1] == 0x1F) {
2183
          AppendToBuffer("nop");  // 0x66 prefix
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        } else if (*data == 0x39) {
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          data++;
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          data += PrintOperands("cmpw", OPER_REG_OP_ORDER, data);
        } else if (*data == 0x3B) {
          data++;
          data += PrintOperands("cmpw", REG_OPER_OP_ORDER, data);
        } else if (*data == 0x81) {
          data++;
          AppendToBuffer("cmpw ");
          data += PrintRightOperand(data);
2194
          AppendToBuffer(",0x%x", Imm16(data));
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          data += 2;
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        } else if (*data == 0x87) {
          data++;
          int mod, regop, rm;
          get_modrm(*data, &mod, &regop, &rm);
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          AppendToBuffer("xchg_w %s,", NameOfCPURegister(regop));
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          data += PrintRightOperand(data);
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        } else if (*data == 0x89) {
          data++;
          int mod, regop, rm;
          get_modrm(*data, &mod, &regop, &rm);
          AppendToBuffer("mov_w ");
          data += PrintRightOperand(data);
          AppendToBuffer(",%s", NameOfCPURegister(regop));
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        } else if (*data == 0x8B) {
          data++;
          data += PrintOperands("mov_w", REG_OPER_OP_ORDER, data);
        } else if (*data == 0x90) {
          AppendToBuffer("nop");  // 0x66 prefix
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        } else if (*data == 0xC7) {
          data++;
          AppendToBuffer("%s ", "mov_w");
          data += PrintRightOperand(data);
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          AppendToBuffer(",0x%x", Imm16(data));
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          data += 2;
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        } else if (*data == 0xF7) {
          data++;
          AppendToBuffer("%s ", "test_w");
          data += PrintRightOperand(data);
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          AppendToBuffer(",0x%x", Imm16(data));
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          data += 2;
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        } else if (*data == 0x0F) {
          data++;
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          if (*data == 0x10) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movupd %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
          } else if (*data == 0x28) {
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            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movapd %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
          } else if (*data == 0x38) {
2241
            data++;
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            byte op = *data;
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            switch (op) {
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#define SSE34_DIS_CASE(instruction, notUsed1, notUsed2, notUsed3, opcode) \
  case 0x##opcode: {                                                      \
    AppendToBuffer(#instruction " %s,", NameOfXMMRegister(regop));        \
    data += PrintRightXMMOperand(data);                                   \
    break;                                                                \
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  }

2254
              SSSE3_INSTRUCTION_LIST(SSE34_DIS_CASE)
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              SSSE3_UNOP_INSTRUCTION_LIST(SSE34_DIS_CASE)
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              SSE4_INSTRUCTION_LIST(SSE34_DIS_CASE)
              SSE4_RM_INSTRUCTION_LIST(SSE34_DIS_CASE)
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#undef SSE34_DIS_CASE
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              case 0x10:
                AppendToBuffer("pblendvb %s,", NameOfXMMRegister(regop));
                data += PrintRightXMMOperand(data);
                AppendToBuffer(",xmm0");
                break;
              case 0x14:
                AppendToBuffer("blendvps %s,", NameOfXMMRegister(regop));
                data += PrintRightXMMOperand(data);
                AppendToBuffer(",xmm0");
                break;
              case 0x15:
                AppendToBuffer("blendvps %s,", NameOfXMMRegister(regop));
                data += PrintRightXMMOperand(data);
                AppendToBuffer(",xmm0");
                break;
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              case 0x37:
                AppendToBuffer("pcmpgtq %s,", NameOfXMMRegister(regop));
                data += PrintRightXMMOperand(data);
                break;
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              default:
                UnimplementedInstruction();
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            }
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          } else if (*data == 0x3A) {
            data++;
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            if (*data >= 0x08 && *data <= 0x0B) {
              const char* const pseudo_op[] = {
                  "roundps",
                  "roundpd",
                  "roundss",
                  "roundsd",
              };
              byte op = *data;
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              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              int8_t imm8 = static_cast<int8_t>(data[1]);
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              AppendToBuffer("%s %s,%s,%d", pseudo_op[op - 0x08],
                             NameOfXMMRegister(regop), NameOfXMMRegister(rm),
                             static_cast<int>(imm8));
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              data += 2;
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            } else if (*data == 0x0E) {
              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              AppendToBuffer("pblendw %s,", NameOfXMMRegister(regop));
              data += PrintRightXMMOperand(data);
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              AppendToBuffer(",%d", Imm8_U(data));
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              data++;
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            } else if (*data == 0x0F) {
              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              AppendToBuffer("palignr %s,", NameOfXMMRegister(regop));
              data += PrintRightXMMOperand(data);
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              AppendToBuffer(",%d", Imm8_U(data));
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              data++;
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            } else if (*data == 0x14) {
              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              AppendToBuffer("pextrb ");
              data += PrintRightOperand(data);
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              AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), Imm8(data));
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              data++;
            } else if (*data == 0x15) {
              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              AppendToBuffer("pextrw ");
              data += PrintRightOperand(data);
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              AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), Imm8(data));
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              data++;
2331
            } else if (*data == 0x16) {
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              data++;
              int mod, regop, rm;
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              get_modrm(*data, &mod, &regop, &rm);
              AppendToBuffer("pextrd ");
              data += PrintRightOperand(data);
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              AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), Imm8(data));
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              data++;
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            } else if (*data == 0x17) {
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              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              int8_t imm8 = static_cast<int8_t>(data[1]);
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              AppendToBuffer("extractps %s,%s,%d", NameOfCPURegister(rm),
                             NameOfXMMRegister(regop), static_cast<int>(imm8));
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              data += 2;
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            } else if (*data == 0x20) {
              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              AppendToBuffer("pinsrb %s,", NameOfXMMRegister(regop));
              data += PrintRightOperand(data);
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              AppendToBuffer(",%d", Imm8(data));
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              data++;
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            } else if (*data == 0x21) {
              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              AppendToBuffer("insertps %s,", NameOfXMMRegister(regop));
              data += PrintRightXMMOperand(data);
2361
              AppendToBuffer(",%d", Imm8(data));
2362
              data++;
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            } else if (*data == 0x22) {
              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
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              AppendToBuffer("pinsrd %s,", NameOfXMMRegister(regop));
              data += PrintRightOperand(data);
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              AppendToBuffer(",%d", Imm8(data));
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              data++;
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            } else {
              UnimplementedInstruction();
            }
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          } else if (*data == 0x2E || *data == 0x2F) {
            const char* mnem = (*data == 0x2E) ? "ucomisd" : "comisd";
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            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
2379
            if (mod == 0x3) {
2380
              AppendToBuffer("%s %s,%s", mnem, NameOfXMMRegister(regop),
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                             NameOfXMMRegister(rm));
              data++;
            } else {
              AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
              data += PrintRightOperand(data);
            }
          } else if (*data == 0x50) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
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            AppendToBuffer("movmskpd %s,%s", NameOfCPURegister(regop),
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                           NameOfXMMRegister(rm));
            data++;
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          } else if (*data >= 0x54 && *data <= 0x5A) {
            const char* const pseudo_op[] = {"andpd",   "andnpd", "orpd",
                                             "xorpd",   "addpd",  "mulpd",
                                             "cvtpd2ps"};
2398
            byte op = *data;
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            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
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            AppendToBuffer("%s %s,", pseudo_op[op - 0x54],
                           NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
          } else if (*data >= 0x5c && *data <= 0x5f) {
            const char* const pseudo_op[] = {
                "subpd",
                "minpd",
                "divpd",
                "maxpd",
            };
            byte op = *data;
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            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
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            AppendToBuffer("%s %s,", pseudo_op[op - 0x5c],
                           NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
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          } else if (*data == 0x6E) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movd %s,", NameOfXMMRegister(regop));
            data += PrintRightOperand(data);
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          } else if (*data == 0x6F) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movdqa %s,", NameOfXMMRegister(regop));
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            data += PrintRightXMMOperand(data);
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          } else if (*data == 0x70) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
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            AppendToBuffer("pshufd %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
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            AppendToBuffer(",%d", Imm8(data));
2438
            data++;
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          } else if (*data == 0x90) {
            data++;
            AppendToBuffer("nop");  // 2 byte nop.
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          } else if (*data == 0x71) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            int8_t imm8 = static_cast<int8_t>(data[1]);
            AppendToBuffer("ps%sw %s,%d", sf_str[regop / 2],
                           NameOfXMMRegister(rm), static_cast<int>(imm8));
            data += 2;
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          } else if (*data == 0x72) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            int8_t imm8 = static_cast<int8_t>(data[1]);
2455
            AppendToBuffer("ps%sd %s,%d", sf_str[regop / 2],
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                           NameOfXMMRegister(rm), static_cast<int>(imm8));
            data += 2;
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          } else if (*data == 0x73) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            int8_t imm8 = static_cast<int8_t>(data[1]);
2463
            DCHECK(regop == esi || regop == edx);
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            AppendToBuffer("ps%sq %s,%d", sf_str[regop / 2],
                           NameOfXMMRegister(rm), static_cast<int>(imm8));
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            data += 2;
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          } else if (*data == 0x7F) {
            AppendToBuffer("movdqa ");
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
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            data += PrintRightXMMOperand(data);
2473
            AppendToBuffer(",%s", NameOfXMMRegister(regop));
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          } else if (*data == 0x7E) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movd ");
            data += PrintRightOperand(data);
            AppendToBuffer(",%s", NameOfXMMRegister(regop));
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          } else if (*data == 0xC1) {
            data += 2;
            data += PrintOperands("xadd_w", OPER_REG_OP_ORDER, data);
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          } else if (*data == 0xC2) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            const char* const pseudo_op[] = {"eq", "lt", "le", "unord", "neq"};
            AppendToBuffer("cmppd %s, ", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
            AppendToBuffer(", (%s)", pseudo_op[*data]);
            data++;
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          } else if (*data == 0xC4) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("pinsrw %s,", NameOfXMMRegister(regop));
            data += PrintRightOperand(data);
2499
            AppendToBuffer(",%d", Imm8(data));
2500
            data++;
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          } else if (*data == 0xC6) {
            // shufpd xmm, xmm/m128, imm8
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("shufpd %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
            AppendToBuffer(",%d", Imm8(data));
            data++;
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          } else if (*data == 0xE6) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("cvttpd2dq %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
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          } else if (*data == 0xE7) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
2520
            if (mod == 3) {
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2521 2522
              // movntdq
              UnimplementedInstruction();
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            } else {
              UnimplementedInstruction();
            }
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          } else if (*data == 0xB1) {
            data++;
            data += PrintOperands("cmpxchg_w", OPER_REG_OP_ORDER, data);
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          } else if (*data == 0xD7) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("pmovmskb %s,%s", NameOfCPURegister(regop),
                           NameOfXMMRegister(rm));
            data++;
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          } else {
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            byte op = *data;
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            switch (op) {
#define SSE2_DIS_CASE(instruction, notUsed1, notUsed2, opcode)     \
  case 0x##opcode: {                                               \
    AppendToBuffer(#instruction " %s,", NameOfXMMRegister(regop)); \
    data += PrintRightXMMOperand(data);                            \
    break;                                                         \
  }

              SSE2_INSTRUCTION_LIST(SSE2_DIS_CASE)
#undef SSE2_DIS_CASE
              default:
                UnimplementedInstruction();
            }
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          }
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        } else {
          UnimplementedInstruction();
        }
        break;

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      case 0xFE: {
        data++;
        int mod, regop, rm;
        get_modrm(*data, &mod, &regop, &rm);
        if (regop == ecx) {
          AppendToBuffer("dec_b ");
          data += PrintRightOperand(data);
        } else {
          UnimplementedInstruction();
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        }
2570
      } break;
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      case 0x68:
2573
        AppendToBuffer("push 0x%x", Imm32(data + 1));
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        data += 5;
        break;

      case 0x6A:
2578
        AppendToBuffer("push 0x%x", Imm8(data + 1));
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        data += 2;
        break;

      case 0xA8:
2583
        AppendToBuffer("test al,0x%x", Imm8_U(data + 1));
2584 2585 2586 2587
        data += 2;
        break;

      case 0xA9:
2588
        AppendToBuffer("test eax,0x%x", Imm32(data + 1));
2589 2590 2591 2592 2593 2594 2595 2596 2597
        data += 5;
        break;

      case 0xD1:  // fall through
      case 0xD3:  // fall through
      case 0xC1:
        data += D1D3C1Instruction(data);
        break;

2598
      case 0xD8:  // fall through
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      case 0xD9:  // fall through
2600
      case 0xDA:  // fall through
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      case 0xDB:  // fall through
      case 0xDC:  // fall through
      case 0xDD:  // fall through
      case 0xDE:  // fall through
      case 0xDF:
        data += FPUInstruction(data);
        break;

      case 0xEB:
        data += JumpShort(data);
        break;

      case 0xF2:
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        if (*(data + 1) == 0x0F) {
          byte b2 = *(data + 2);
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          if (b2 == 0x11) {
            AppendToBuffer("movsd ");
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
2621
            data += PrintRightXMMOperand(data);
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            AppendToBuffer(",%s", NameOfXMMRegister(regop));
          } else if (b2 == 0x10) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movsd %s,", NameOfXMMRegister(regop));
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            data += PrintRightXMMOperand(data);
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          } else if (b2 == 0x12) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movddup %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
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          } else if (b2 == 0x5A) {
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            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("cvtsd2ss %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
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          } else if (b2 == 0x70) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("pshuflw %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
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            AppendToBuffer(",%d", Imm8(data));
2648
            data++;
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          } else {
            const char* mnem = "?";
            switch (b2) {
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              case 0x2A:
                mnem = "cvtsi2sd";
                break;
              case 0x2C:
                mnem = "cvttsd2si";
                break;
              case 0x2D:
                mnem = "cvtsd2si";
                break;
              case 0x51:
                mnem = "sqrtsd";
                break;
              case 0x58:
                mnem = "addsd";
                break;
              case 0x59:
                mnem = "mulsd";
                break;
              case 0x5C:
                mnem = "subsd";
                break;
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              case 0x5D:
                mnem = "minsd";
                break;
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              case 0x5E:
                mnem = "divsd";
                break;
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              case 0x5F:
                mnem = "maxsd";
                break;
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              case 0x7C:
                mnem = "haddps";
                break;
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            }
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            if (b2 == 0x2A) {
2690 2691
              AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
              data += PrintRightOperand(data);
2692
            } else if (b2 == 0x2C || b2 == 0x2D) {
2693 2694
              AppendToBuffer("%s %s,", mnem, NameOfCPURegister(regop));
              data += PrintRightXMMOperand(data);
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            } else if (b2 == 0xC2) {
              // Intel manual 2A, Table 3-18.
              const char* const pseudo_op[] = {
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                  "cmpeqsd",  "cmpltsd",  "cmplesd",  "cmpunordsd",
                  "cmpneqsd", "cmpnltsd", "cmpnlesd", "cmpordsd"};
              AppendToBuffer("%s %s,%s", pseudo_op[data[1]],
                             NameOfXMMRegister(regop), NameOfXMMRegister(rm));
2702
              data += 2;
2703
            } else {
2704 2705
              AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
              data += PrintRightXMMOperand(data);
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            }
          }
        } else {
          UnimplementedInstruction();
2710
          data++;
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        }
        break;

      case 0xF3:
2715 2716
        if (*(data + 1) == 0x0F) {
          byte b2 = *(data + 2);
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          if (b2 == 0x11) {
            AppendToBuffer("movss ");
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            data += PrintRightXMMOperand(data);
            AppendToBuffer(",%s", NameOfXMMRegister(regop));
          } else if (b2 == 0x10) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movss %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
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          } else if (b2 == 0x16) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movshdup %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
2736
          } else if (b2 == 0x5A) {
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            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
2740 2741
            AppendToBuffer("cvtss2sd %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
2742
          } else if (b2 == 0x6F) {
2743 2744 2745 2746
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movdqu %s,", NameOfXMMRegister(regop));
2747
            data += PrintRightXMMOperand(data);
2748 2749 2750 2751 2752 2753
          } else if (b2 == 0x70) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("pshufhw %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
2754
            AppendToBuffer(",%d", Imm8(data));
2755
            data++;
2756
          } else if (b2 == 0x7F) {
2757 2758 2759 2760
            AppendToBuffer("movdqu ");
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
2761
            data += PrintRightXMMOperand(data);
2762
            AppendToBuffer(",%s", NameOfXMMRegister(regop));
2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780
          } else if (b2 == 0xB8) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("popcnt %s,", NameOfCPURegister(regop));
            data += PrintRightOperand(data);
          } else if (b2 == 0xBC) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("tzcnt %s,", NameOfCPURegister(regop));
            data += PrintRightOperand(data);
          } else if (b2 == 0xBD) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("lzcnt %s,", NameOfCPURegister(regop));
            data += PrintRightOperand(data);
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          } else if (b2 == 0xE6) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("cvtdq2pd %s", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
2787
          } else {
2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807
            const char* mnem = "?";
            switch (b2) {
              case 0x2A:
                mnem = "cvtsi2ss";
                break;
              case 0x2C:
                mnem = "cvttss2si";
                break;
              case 0x2D:
                mnem = "cvtss2si";
                break;
              case 0x51:
                mnem = "sqrtss";
                break;
              case 0x58:
                mnem = "addss";
                break;
              case 0x59:
                mnem = "mulss";
                break;
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              case 0x5B:
                mnem = "cvttps2dq";
                break;
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              case 0x5C:
                mnem = "subss";
                break;
              case 0x5D:
                mnem = "minss";
                break;
              case 0x5E:
                mnem = "divss";
                break;
              case 0x5F:
                mnem = "maxss";
                break;
2823 2824 2825
              case 0x7E:
                mnem = "movq";
                break;
2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847
            }
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            if (b2 == 0x2A) {
              AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
              data += PrintRightOperand(data);
            } else if (b2 == 0x2C || b2 == 0x2D) {
              AppendToBuffer("%s %s,", mnem, NameOfCPURegister(regop));
              data += PrintRightXMMOperand(data);
            } else if (b2 == 0xC2) {
              // Intel manual 2A, Table 3-18.
              const char* const pseudo_op[] = {
                  "cmpeqss",  "cmpltss",  "cmpless",  "cmpunordss",
                  "cmpneqss", "cmpnltss", "cmpnless", "cmpordss"};
              AppendToBuffer("%s %s,%s", pseudo_op[data[1]],
                             NameOfXMMRegister(regop), NameOfXMMRegister(rm));
              data += 2;
            } else {
              AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
              data += PrintRightXMMOperand(data);
            }
2848
          }
2849
        } else if (*(data + 1) == 0xA5) {
2850 2851
          data += 2;
          AppendToBuffer("rep_movs");
2852
        } else if (*(data + 1) == 0xAB) {
2853 2854
          data += 2;
          AppendToBuffer("rep_stos");
2855 2856 2857
        } else if (*(data + 1) == 0x90) {
          data += 2;
          AppendToBuffer("pause");
2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868
        } else {
          UnimplementedInstruction();
        }
        break;

      case 0xF7:
        data += F7Instruction(data);
        break;

      default:
        UnimplementedInstruction();
2869
        data++;
2870 2871 2872 2873 2874 2875 2876 2877
    }
  }

  if (tmp_buffer_pos_ < sizeof tmp_buffer_) {
    tmp_buffer_[tmp_buffer_pos_] = '\0';
  }

  int instr_len = data - instr;
2878 2879 2880
  if (instr_len == 0) {
    printf("%02x", *data);
  }
2881
  DCHECK_GT(instr_len, 0);  // Ensure progress.
2882 2883 2884 2885

  int outp = 0;
  // Instruction bytes.
  for (byte* bp = instr; bp < data; bp++) {
2886
    outp += v8::base::SNPrintF(out_buffer + outp, "%02x", *bp);
2887
  }
2888 2889
  // Indent instruction, leaving space for 6 bytes, i.e. 12 characters in hex.
  while (outp < 12) {
2890
    outp += v8::base::SNPrintF(out_buffer + outp, "  ");
2891 2892
  }

2893
  outp += v8::base::SNPrintF(out_buffer + outp, " %s", tmp_buffer_.begin());
2894
  return instr_len;
2895
}
2896 2897 2898

//------------------------------------------------------------------------------

2899 2900
static const char* const cpu_regs[8] = {"eax", "ecx", "edx", "ebx",
                                        "esp", "ebp", "esi", "edi"};
2901

2902 2903
static const char* const byte_cpu_regs[8] = {"al", "cl", "dl", "bl",
                                             "ah", "ch", "dh", "bh"};
2904

2905 2906
static const char* const xmm_regs[8] = {"xmm0", "xmm1", "xmm2", "xmm3",
                                        "xmm4", "xmm5", "xmm6", "xmm7"};
2907 2908

const char* NameConverter::NameOfAddress(byte* addr) const {
2909
  v8::base::SNPrintF(tmp_buffer_, "%p", static_cast<void*>(addr));
2910
  return tmp_buffer_.begin();
2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921
}

const char* NameConverter::NameOfConstant(byte* addr) const {
  return NameOfAddress(addr);
}

const char* NameConverter::NameOfCPURegister(int reg) const {
  if (0 <= reg && reg < 8) return cpu_regs[reg];
  return "noreg";
}

2922 2923 2924 2925 2926
const char* NameConverter::NameOfByteCPURegister(int reg) const {
  if (0 <= reg && reg < 8) return byte_cpu_regs[reg];
  return "noreg";
}

2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938
const char* NameConverter::NameOfXMMRegister(int reg) const {
  if (0 <= reg && reg < 8) return xmm_regs[reg];
  return "noxmmreg";
}

const char* NameConverter::NameInCode(byte* addr) const {
  // IA32 does not embed debug strings at the moment.
  UNREACHABLE();
}

//------------------------------------------------------------------------------

2939
int Disassembler::InstructionDecode(v8::base::Vector<char> buffer,
2940
                                    byte* instruction) {
2941
  DisassemblerIA32 d(converter_, unimplemented_opcode_action());
2942 2943
  return d.InstructionDecode(buffer, instruction);
}
2944

2945 2946 2947
// The IA-32 assembler does not currently use constant pools.
int Disassembler::ConstantPoolSizeAt(byte* instruction) { return -1; }

2948 2949 2950
// static
void Disassembler::Disassemble(FILE* f, byte* begin, byte* end,
                               UnimplementedOpcodeAction unimplemented_action) {
2951
  NameConverter converter;
2952
  Disassembler d(converter, unimplemented_action);
2953
  for (byte* pc = begin; pc < end;) {
2954
    v8::base::EmbeddedVector<char, 128> buffer;
2955 2956
    buffer[0] = '\0';
    byte* prev_pc = pc;
2957
    pc += d.InstructionDecode(buffer, pc);
2958
    fprintf(f, "%p", static_cast<void*>(prev_pc));
2959 2960 2961
    fprintf(f, "    ");

    for (byte* bp = prev_pc; bp < pc; bp++) {
2962
      fprintf(f, "%02x", *bp);
2963 2964 2965 2966
    }
    for (int i = 6 - (pc - prev_pc); i >= 0; i--) {
      fprintf(f, "  ");
    }
2967
    fprintf(f, "  %s\n", buffer.begin());
2968 2969 2970 2971
  }
}

}  // namespace disasm
2972 2973

#endif  // V8_TARGET_ARCH_IA32