Commit 97254b0d authored by jing.bao's avatar jing.bao Committed by Commit bot

[ia32] Supplement shift instructions for SIMD

psll/rl/raw(xmm, imm)
psrad(xmm, imm)
vpsll/rl/raw(xmm, xmm, imm)
vpsll/rl/rad(xmm, xmm, imm)

BUG=

Review-Url: https://codereview.chromium.org/2747783004
Cr-Commit-Position: refs/heads/master@{#43762}
parent a0bcd197
......@@ -2520,7 +2520,6 @@ void Assembler::extractps(Register dst, XMMRegister src, byte imm8) {
EMIT(imm8);
}
void Assembler::ptest(XMMRegister dst, XMMRegister src) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
......@@ -2531,6 +2530,14 @@ void Assembler::ptest(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::psllw(XMMRegister reg, int8_t shift) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
EMIT(0x71);
emit_sse_operand(esi, reg); // esi == 6
EMIT(shift);
}
void Assembler::pslld(XMMRegister reg, int8_t shift) {
EnsureSpace ensure_space(this);
......@@ -2541,6 +2548,14 @@ void Assembler::pslld(XMMRegister reg, int8_t shift) {
EMIT(shift);
}
void Assembler::psrlw(XMMRegister reg, int8_t shift) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
EMIT(0x71);
emit_sse_operand(edx, reg); // edx == 2
EMIT(shift);
}
void Assembler::psrld(XMMRegister reg, int8_t shift) {
EnsureSpace ensure_space(this);
......@@ -2551,6 +2566,23 @@ void Assembler::psrld(XMMRegister reg, int8_t shift) {
EMIT(shift);
}
void Assembler::psraw(XMMRegister reg, int8_t shift) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
EMIT(0x71);
emit_sse_operand(esp, reg); // esp == 4
EMIT(shift);
}
void Assembler::psrad(XMMRegister reg, int8_t shift) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
EMIT(0x72);
emit_sse_operand(esp, reg); // esp == 4
EMIT(shift);
}
void Assembler::psllq(XMMRegister reg, int8_t shift) {
EnsureSpace ensure_space(this);
......@@ -2764,6 +2796,41 @@ void Assembler::vpd(byte op, XMMRegister dst, XMMRegister src1,
emit_sse_operand(dst, src2);
}
void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int8_t imm8) {
XMMRegister iop = {6};
vinstr(0x71, iop, dst, Operand(src), k66, k0F, kWIG);
EMIT(imm8);
}
void Assembler::vpslld(XMMRegister dst, XMMRegister src, int8_t imm8) {
XMMRegister iop = {6};
vinstr(0x72, iop, dst, Operand(src), k66, k0F, kWIG);
EMIT(imm8);
}
void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int8_t imm8) {
XMMRegister iop = {2};
vinstr(0x71, iop, dst, Operand(src), k66, k0F, kWIG);
EMIT(imm8);
}
void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int8_t imm8) {
XMMRegister iop = {2};
vinstr(0x72, iop, dst, Operand(src), k66, k0F, kWIG);
EMIT(imm8);
}
void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int8_t imm8) {
XMMRegister iop = {4};
vinstr(0x71, iop, dst, Operand(src), k66, k0F, kWIG);
EMIT(imm8);
}
void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int8_t imm8) {
XMMRegister iop = {4};
vinstr(0x72, iop, dst, Operand(src), k66, k0F, kWIG);
EMIT(imm8);
}
void Assembler::bmi1(byte op, Register reg, Register vreg, const Operand& rm) {
DCHECK(IsEnabled(BMI1));
......
......@@ -1061,8 +1061,12 @@ class Assembler : public AssemblerBase {
void ptest(XMMRegister dst, XMMRegister src);
void psllw(XMMRegister reg, int8_t shift);
void pslld(XMMRegister reg, int8_t shift);
void psrlw(XMMRegister reg, int8_t shift);
void psrld(XMMRegister reg, int8_t shift);
void psraw(XMMRegister reg, int8_t shift);
void psrad(XMMRegister reg, int8_t shift);
void psllq(XMMRegister reg, int8_t shift);
void psllq(XMMRegister dst, XMMRegister src);
void psrlq(XMMRegister reg, int8_t shift);
......@@ -1306,6 +1310,13 @@ class Assembler : public AssemblerBase {
}
void vss(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
void vpsllw(XMMRegister dst, XMMRegister src, int8_t imm8);
void vpslld(XMMRegister dst, XMMRegister src, int8_t imm8);
void vpsrlw(XMMRegister dst, XMMRegister src, int8_t imm8);
void vpsrld(XMMRegister dst, XMMRegister src, int8_t imm8);
void vpsraw(XMMRegister dst, XMMRegister src, int8_t imm8);
void vpsrad(XMMRegister dst, XMMRegister src, int8_t imm8);
// BMI instruction
void andn(Register dst, Register src1, Register src2) {
andn(dst, src1, Operand(src2));
......
......@@ -729,6 +729,7 @@ int DisassemblerIA32::CMov(byte* data) {
return 2 + op_size; // includes 0x0F
}
const char* sf_str[4] = {"", "rl", "ra", "ll"};
int DisassemblerIA32::AVXInstruction(byte* data) {
byte opcode = *data;
......@@ -1014,6 +1015,18 @@ int DisassemblerIA32::AVXInstruction(byte* data) {
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x71:
AppendToBuffer("vps%sw %s,%s", sf_str[regop / 2],
NameOfXMMRegister(vvvv), NameOfXMMRegister(rm));
current++;
AppendToBuffer(",%u", *current++);
break;
case 0x72:
AppendToBuffer("vps%sd %s,%s", sf_str[regop / 2],
NameOfXMMRegister(vvvv), NameOfXMMRegister(rm));
current++;
AppendToBuffer(",%u", *current++);
break;
#define DECLARE_SSE_AVX_DIS_CASE(instruction, notUsed1, notUsed2, opcode) \
case 0x##opcode: { \
AppendToBuffer("v" #instruction " %s,%s,", NameOfXMMRegister(regop), \
......@@ -1861,13 +1874,20 @@ int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
NameOfXMMRegister(regop),
NameOfXMMRegister(rm));
data++;
} else if (*data == 0x71) {
data++;
int mod, regop, rm;
get_modrm(*data, &mod, &regop, &rm);
int8_t imm8 = static_cast<int8_t>(data[1]);
AppendToBuffer("ps%sw %s,%d", sf_str[regop / 2],
NameOfXMMRegister(rm), static_cast<int>(imm8));
data += 2;
} else if (*data == 0x72) {
data++;
int mod, regop, rm;
get_modrm(*data, &mod, &regop, &rm);
int8_t imm8 = static_cast<int8_t>(data[1]);
DCHECK(regop == esi || regop == edx);
AppendToBuffer("%s %s,%d", (regop == esi) ? "pslld" : "psrld",
AppendToBuffer("ps%sd %s,%d", sf_str[regop / 2],
NameOfXMMRegister(rm), static_cast<int>(imm8));
data += 2;
} else if (*data == 0x73) {
......@@ -1876,10 +1896,8 @@ int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
get_modrm(*data, &mod, &regop, &rm);
int8_t imm8 = static_cast<int8_t>(data[1]);
DCHECK(regop == esi || regop == edx);
AppendToBuffer("%s %s,%d",
(regop == esi) ? "psllq" : "psrlq",
NameOfXMMRegister(rm),
static_cast<int>(imm8));
AppendToBuffer("ps%sq %s,%d", sf_str[regop / 2],
NameOfXMMRegister(rm), static_cast<int>(imm8));
data += 2;
} else if (*data == 0xD3) {
data++;
......
......@@ -54,7 +54,6 @@ TEST(DisasmIa320) {
v8::internal::byte buffer[4096];
Assembler assm(isolate, buffer, sizeof buffer);
DummyStaticFunction(NULL); // just bloody use it (DELETE; debugging)
// Short immediate instructions
__ adc(eax, 12345678);
__ add(eax, Immediate(12345678));
......@@ -458,6 +457,13 @@ TEST(DisasmIa320) {
__ cmpltsd(xmm0, xmm1);
__ andpd(xmm0, xmm1);
__ psllw(xmm0, 17);
__ pslld(xmm0, 17);
__ psrlw(xmm0, 17);
__ psrld(xmm0, 17);
__ psraw(xmm0, 17);
__ psrad(xmm0, 17);
__ psllq(xmm0, 17);
__ psllq(xmm0, xmm1);
__ psrlq(xmm0, 17);
......@@ -550,6 +556,12 @@ TEST(DisasmIa320) {
__ vxorpd(xmm0, xmm1, xmm2);
__ vxorpd(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vpsllw(xmm0, xmm7, 21);
__ vpslld(xmm0, xmm7, 21);
__ vpsrlw(xmm0, xmm7, 21);
__ vpsrld(xmm0, xmm7, 21);
__ vpsraw(xmm0, xmm7, 21);
__ vpsrad(xmm0, xmm7, 21);
#define EMIT_SSE2_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3) \
__ v##instruction(xmm7, xmm5, xmm1); \
__ v##instruction(xmm7, xmm5, Operand(edx, 4));
......
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