Commit 1073dc98 authored by jing.bao's avatar jing.bao Committed by Commit bot

[ia32] Add rcpps, rsqrtps, cvtdq2ps, cvttps2dq

instr(xmm, xmm/mem)
vinstr(xmm, xmm/mem)

BUG=

Review-Url: https://codereview.chromium.org/2870253003
Cr-Commit-Position: refs/heads/master@{#45293}
parent 168eb163
......@@ -2162,6 +2162,20 @@ void Assembler::cvtsd2ss(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::cvtdq2ps(XMMRegister dst, const Operand& src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x5B);
emit_sse_operand(dst, src);
}
void Assembler::cvttps2dq(XMMRegister dst, const Operand& src) {
EnsureSpace ensure_space(this);
EMIT(0xF3);
EMIT(0x0F);
EMIT(0x5B);
emit_sse_operand(dst, src);
}
void Assembler::addsd(XMMRegister dst, const Operand& src) {
EnsureSpace ensure_space(this);
......@@ -2263,6 +2277,20 @@ void Assembler::divps(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::rcpps(XMMRegister dst, const Operand& src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x53);
emit_sse_operand(dst, src);
}
void Assembler::rsqrtps(XMMRegister dst, const Operand& src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x52);
emit_sse_operand(dst, src);
}
void Assembler::minps(XMMRegister dst, const Operand& src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
......
......@@ -980,6 +980,10 @@ class Assembler : public AssemblerBase {
void mulps(XMMRegister dst, XMMRegister src) { mulps(dst, Operand(src)); }
void divps(XMMRegister dst, const Operand& src);
void divps(XMMRegister dst, XMMRegister src) { divps(dst, Operand(src)); }
void rcpps(XMMRegister dst, const Operand& src);
void rcpps(XMMRegister dst, XMMRegister src) { rcpps(dst, Operand(src)); }
void rsqrtps(XMMRegister dst, const Operand& src);
void rsqrtps(XMMRegister dst, XMMRegister src) { rsqrtps(dst, Operand(src)); }
void minps(XMMRegister dst, const Operand& src);
void minps(XMMRegister dst, XMMRegister src) { minps(dst, Operand(src)); }
......@@ -1023,6 +1027,15 @@ class Assembler : public AssemblerBase {
void cvtsd2ss(XMMRegister dst, XMMRegister src) {
cvtsd2ss(dst, Operand(src));
}
void cvtdq2ps(XMMRegister dst, XMMRegister src) {
cvtdq2ps(dst, Operand(src));
}
void cvtdq2ps(XMMRegister dst, const Operand& src);
void cvttps2dq(XMMRegister dst, XMMRegister src) {
cvttps2dq(dst, Operand(src));
}
void cvttps2dq(XMMRegister dst, const Operand& src);
void addsd(XMMRegister dst, XMMRegister src) { addsd(dst, Operand(src)); }
void addsd(XMMRegister dst, const Operand& src);
void subsd(XMMRegister dst, XMMRegister src) { subsd(dst, Operand(src)); }
......@@ -1331,6 +1344,17 @@ class Assembler : public AssemblerBase {
}
void vss(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
void vrcpps(XMMRegister dst, XMMRegister src) { vrcpps(dst, Operand(src)); }
void vrcpps(XMMRegister dst, const Operand& src) {
vinstr(0x53, dst, xmm0, src, kNone, k0F, kWIG);
}
void vrsqrtps(XMMRegister dst, XMMRegister src) {
vrsqrtps(dst, Operand(src));
}
void vrsqrtps(XMMRegister dst, const Operand& src) {
vinstr(0x52, dst, xmm0, src, kNone, k0F, kWIG);
}
void vpsllw(XMMRegister dst, XMMRegister src, int8_t imm8);
void vpslld(XMMRegister dst, XMMRegister src, int8_t imm8);
void vpsrlw(XMMRegister dst, XMMRegister src, int8_t imm8);
......@@ -1338,6 +1362,19 @@ class Assembler : public AssemblerBase {
void vpsraw(XMMRegister dst, XMMRegister src, int8_t imm8);
void vpsrad(XMMRegister dst, XMMRegister src, int8_t imm8);
void vcvtdq2ps(XMMRegister dst, XMMRegister src) {
vcvtdq2ps(dst, Operand(src));
}
void vcvtdq2ps(XMMRegister dst, const Operand& src) {
vinstr(0x5B, dst, xmm0, src, kNone, k0F, kWIG);
}
void vcvttps2dq(XMMRegister dst, XMMRegister src) {
vcvttps2dq(dst, Operand(src));
}
void vcvttps2dq(XMMRegister dst, const Operand& src) {
vinstr(0x5B, dst, xmm0, src, kF3, k0F, kWIG);
}
// BMI instruction
void andn(Register dst, Register src1, Register src2) {
andn(dst, src1, Operand(src2));
......
......@@ -868,6 +868,10 @@ int DisassemblerIA32::AVXInstruction(byte* data) {
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x5b:
AppendToBuffer("vcvttps2dq %s,", NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
break;
case 0x5c:
AppendToBuffer("vsubss %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
......@@ -988,6 +992,14 @@ int DisassemblerIA32::AVXInstruction(byte* data) {
int mod, regop, rm, vvvv = vex_vreg();
get_modrm(*current, &mod, &regop, &rm);
switch (opcode) {
case 0x52:
AppendToBuffer("vrsqrtps %s,", NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
break;
case 0x53:
AppendToBuffer("vrcpps %s,", NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
break;
case 0x54:
AppendToBuffer("vandps %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
......@@ -1008,6 +1020,10 @@ int DisassemblerIA32::AVXInstruction(byte* data) {
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x5B:
AppendToBuffer("vcvtdq2ps %s,", NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
break;
case 0x5C:
AppendToBuffer("vsubps %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
......@@ -1547,28 +1563,17 @@ int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
get_modrm(*data, &mod, &regop, &rm);
AppendToBuffer("ucomiss %s,", NameOfXMMRegister(regop));
data += PrintRightXMMOperand(data);
} else if (f0byte >= 0x53 && f0byte <= 0x5F) {
} else if (f0byte >= 0x52 && f0byte <= 0x5F) {
const char* const pseudo_op[] = {
"rcpps",
"andps",
"andnps",
"orps",
"xorps",
"addps",
"mulps",
"cvtps2pd",
"cvtdq2ps",
"subps",
"minps",
"divps",
"maxps",
"rsqrtps", "rcpps", "andps", "andnps", "orps",
"xorps", "addps", "mulps", "cvtps2pd", "cvtdq2ps",
"subps", "minps", "divps", "maxps",
};
data += 2;
int mod, regop, rm;
get_modrm(*data, &mod, &regop, &rm);
AppendToBuffer("%s %s,",
pseudo_op[f0byte - 0x53],
AppendToBuffer("%s %s,", pseudo_op[f0byte - 0x52],
NameOfXMMRegister(regop));
data += PrintRightXMMOperand(data);
} else if (f0byte == 0x50) {
......@@ -2266,6 +2271,9 @@ int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
case 0x59:
mnem = "mulss";
break;
case 0x5B:
mnem = "cvttps2dq";
break;
case 0x5C:
mnem = "subss";
break;
......
......@@ -428,6 +428,10 @@ TEST(DisasmIa320) {
__ minps(xmm1, Operand(ebx, ecx, times_4, 10000));
__ maxps(xmm1, xmm0);
__ maxps(xmm1, Operand(ebx, ecx, times_4, 10000));
__ rcpps(xmm1, xmm0);
__ rcpps(xmm1, Operand(ebx, ecx, times_4, 10000));
__ rsqrtps(xmm1, xmm0);
__ rsqrtps(xmm1, Operand(ebx, ecx, times_4, 10000));
__ cmpeqps(xmm5, xmm1);
__ cmpeqps(xmm5, Operand(ebx, ecx, times_4, 10000));
......@@ -446,6 +450,10 @@ TEST(DisasmIa320) {
__ cvtsi2sd(xmm1, Operand(ebx, ecx, times_4, 10000));
__ cvtss2sd(xmm1, Operand(ebx, ecx, times_4, 10000));
__ cvtss2sd(xmm1, xmm0);
__ cvtdq2ps(xmm1, xmm0);
__ cvtdq2ps(xmm1, Operand(ebx, ecx, times_4, 10000));
__ cvttps2dq(xmm1, xmm0);
__ cvttps2dq(xmm1, Operand(ebx, ecx, times_4, 10000));
__ movsd(xmm1, Operand(ebx, ecx, times_4, 10000));
__ movsd(Operand(ebx, ecx, times_4, 10000), xmm1);
// 128 bit move instructions.
......@@ -575,6 +583,10 @@ TEST(DisasmIa320) {
__ vdivps(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vmaxps(xmm0, xmm1, xmm2);
__ vmaxps(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vrcpps(xmm1, xmm0);
__ vrcpps(xmm1, Operand(ebx, ecx, times_4, 10000));
__ vrsqrtps(xmm1, xmm0);
__ vrsqrtps(xmm1, Operand(ebx, ecx, times_4, 10000));
__ vcmpeqps(xmm5, xmm4, xmm1);
__ vcmpeqps(xmm5, xmm4, Operand(ebx, ecx, times_4, 10000));
......@@ -608,6 +620,12 @@ TEST(DisasmIa320) {
__ vpsrld(xmm0, xmm7, 21);
__ vpsraw(xmm0, xmm7, 21);
__ vpsrad(xmm0, xmm7, 21);
__ vcvtdq2ps(xmm1, xmm0);
__ vcvtdq2ps(xmm1, Operand(ebx, ecx, times_4, 10000));
__ vcvttps2dq(xmm1, xmm0);
__ vcvttps2dq(xmm1, Operand(ebx, ecx, times_4, 10000));
#define EMIT_SSE2_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3) \
__ v##instruction(xmm7, xmm5, xmm1); \
__ v##instruction(xmm7, xmm5, Operand(edx, 4));
......
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