Move architecture dependent files

Bug: v8:9247
Change-Id: I2f999ed3a8cc0931e5092f2ac6e709b8ff3f9e42
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1630678
Commit-Queue: Yang Guo <yangguo@chromium.org>
Reviewed-by: Ross McIlroy <rmcilroy@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Cr-Commit-Position: refs/heads/master@{#61896}

OWNERS

@@ -22,5 +22,10 @@ per-file codereview.settings=file://INFRA_OWNERS
 per-file AUTHORS=file://COMMON_OWNERS
 per-file WATCHLIST=file://COMMON_OWNERS
 
+per-file *-mips*=file://MIPS_OWNERS
+per-file *-mips64*=file://MIPS_OWNERS
+per-file *-ppc*=file://PPC_OWNERS
+per-file *-s390*=file://S390_OWNERS
+
 # TEAM: v8-dev@googlegroups.com
 # COMPONENT: Blink>JavaScript

src/builtins/mips/builtins-mips.cc

@@ -13,9 +13,9 @@
 #include "src/logging/counters.h"
 // For interpreter_entry_return_pc_offset. TODO(jkummerow): Drop.
 #include "src/codegen/macro-assembler-inl.h"
+#include "src/codegen/mips/constants-mips.h"
 #include "src/codegen/register-configuration.h"
 #include "src/heap/heap-inl.h"
-#include "src/mips/constants-mips.h"
 #include "src/objects/cell.h"
 #include "src/objects/foreign.h"
 #include "src/objects/heap-number.h"

src/builtins/mips64/OWNERS

-xwafish@gmail.com

src/builtins/mips64/builtins-mips64.cc

@@ -13,9 +13,9 @@
 #include "src/logging/counters.h"
 // For interpreter_entry_return_pc_offset. TODO(jkummerow): Drop.
 #include "src/codegen/macro-assembler-inl.h"
+#include "src/codegen/mips64/constants-mips64.h"
 #include "src/codegen/register-configuration.h"
 #include "src/heap/heap-inl.h"
-#include "src/mips64/constants-mips64.h"
 #include "src/objects/cell.h"
 #include "src/objects/foreign.h"
 #include "src/objects/heap-number.h"

src/arm/assembler-arm-inl.h → src/codegen/arm/assembler-arm-inl.h

@@ -34,10 +34,10 @@
 // significantly by Google Inc.
 // Copyright 2012 the V8 project authors. All rights reserved.
 
-#ifndef V8_ARM_ASSEMBLER_ARM_INL_H_
-#define V8_ARM_ASSEMBLER_ARM_INL_H_
+#ifndef V8_CODEGEN_ARM_ASSEMBLER_ARM_INL_H_
+#define V8_CODEGEN_ARM_ASSEMBLER_ARM_INL_H_
 
-#include "src/arm/assembler-arm.h"
+#include "src/codegen/arm/assembler-arm.h"
 
 #include "src/codegen/assembler.h"
 #include "src/debug/debug.h"
@@ -55,7 +55,6 @@ int DoubleRegister::NumRegisters() {
   return CpuFeatures::IsSupported(VFP32DREGS) ? 32 : 16;
 }
 
-
 void RelocInfo::apply(intptr_t delta) {
   if (RelocInfo::IsInternalReference(rmode_)) {
     // absolute code pointer inside code object moves with the code object.
@@ -68,7 +67,6 @@ void RelocInfo::apply(intptr_t delta) {
   }
 }
 
-
 Address RelocInfo::target_address() {
   DCHECK(IsCodeTargetMode(rmode_) || IsRuntimeEntry(rmode_) ||
          IsWasmCall(rmode_));
@@ -88,16 +86,12 @@ Address RelocInfo::target_address_address() {
   }
 }
 
-
 Address RelocInfo::constant_pool_entry_address() {
   DCHECK(IsInConstantPool());
   return Assembler::constant_pool_entry_address(pc_, constant_pool_);
 }
 
-
-int RelocInfo::target_address_size() {
-  return kPointerSize;
-}
+int RelocInfo::target_address_size() { return kPointerSize; }
 
 HeapObject RelocInfo::target_object() {
   DCHECK(IsCodeTarget(rmode_) || rmode_ == FULL_EMBEDDED_OBJECT);
@@ -146,7 +140,6 @@ Address RelocInfo::target_internal_reference() {
   return Memory<Address>(pc_);
 }
 
-
 Address RelocInfo::target_internal_reference_address() {
   DCHECK(rmode_ == INTERNAL_REFERENCE);
   return pc_;
@@ -208,7 +201,6 @@ void Assembler::CheckBuffer() {
   MaybeCheckConstPool();
 }
 
-
 void Assembler::emit(Instr x) {
   CheckBuffer();
   *reinterpret_cast<Instr*>(pc_) = x;
@@ -230,12 +222,10 @@ void Assembler::deserialization_set_target_internal_reference_at(
   Memory<Address>(pc) = target;
 }
 
-
 bool Assembler::is_constant_pool_load(Address pc) {
   return IsLdrPcImmediateOffset(Memory<int32_t>(pc));
 }
 
-
 Address Assembler::constant_pool_entry_address(Address pc,
                                                Address constant_pool) {
   DCHECK(Assembler::IsLdrPcImmediateOffset(Memory<int32_t>(pc)));
@@ -243,7 +233,6 @@ Address Assembler::constant_pool_entry_address(Address pc,
   return pc + GetLdrRegisterImmediateOffset(instr) + Instruction::kPcLoadDelta;
 }
 
-
 Address Assembler::target_address_at(Address pc, Address constant_pool) {
   if (is_constant_pool_load(pc)) {
     // This is a constant pool lookup. Return the value in the constant pool.
@@ -369,4 +358,4 @@ T UseScratchRegisterScope::AcquireVfp() {
 }  // namespace internal
 }  // namespace v8
 
-#endif  // V8_ARM_ASSEMBLER_ARM_INL_H_
+#endif  // V8_CODEGEN_ARM_ASSEMBLER_ARM_INL_H_

src/arm/constants-arm.cc → src/codegen/arm/constants-arm.cc

@@ -4,8 +4,7 @@
 
 #if V8_TARGET_ARCH_ARM
 
-#include "src/arm/constants-arm.h"
-
+#include "src/codegen/arm/constants-arm.h"
 
 namespace v8 {
 namespace internal {
@@ -19,24 +18,22 @@ Float64 Instruction::DoubleImmedVmov() const {
   //
   // where B = ~b. Only the high 16 bits are affected.
   uint64_t high16;
-  high16  = (Bits(17, 16) << 4) | Bits(3, 0);   // xxxxxxxx,xxcdefgh.
-  high16 |= (0xFF * Bit(18)) << 6;              // xxbbbbbb,bbxxxxxx.
-  high16 |= (Bit(18) ^ 1) << 14;                // xBxxxxxx,xxxxxxxx.
-  high16 |= Bit(19) << 15;                      // axxxxxxx,xxxxxxxx.
+  high16 = (Bits(17, 16) << 4) | Bits(3, 0);  // xxxxxxxx,xxcdefgh.
+  high16 |= (0xFF * Bit(18)) << 6;            // xxbbbbbb,bbxxxxxx.
+  high16 |= (Bit(18) ^ 1) << 14;              // xBxxxxxx,xxxxxxxx.
+  high16 |= Bit(19) << 15;                    // axxxxxxx,xxxxxxxx.
 
   uint64_t imm = high16 << 48;
   return Float64::FromBits(imm);
 }
 
-
 // These register names are defined in a way to match the native disassembler
 // formatting. See for example the command "objdump -d <binary file>".
 const char* Registers::names_[kNumRegisters] = {
-  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
-  "r8", "r9", "r10", "fp", "ip", "sp", "lr", "pc",
+    "r0", "r1", "r2",  "r3", "r4", "r5", "r6", "r7",
+    "r8", "r9", "r10", "fp", "ip", "sp", "lr", "pc",
 };
 
-
 // List of alias names which can be used when referring to ARM registers.
 const Registers::RegisterAlias Registers::aliases_[] = {
     {10, "sl"},  {11, "r11"}, {12, "r12"},           {13, "r13"},
@@ -47,23 +44,18 @@ const Registers::RegisterAlias Registers::aliases_[] = {
 // These register names are defined in a way to match the native disassembler
 // formatting. See for example the command "objdump -d <binary file>".
 const char* VFPRegisters::names_[kNumVFPRegisters] = {
-    "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
-    "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
-    "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
-    "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
-    "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
-    "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
-    "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
-    "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"
-};
-
+    "s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",  "s8",  "s9",  "s10",
+    "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
+    "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", "d0",
+    "d1",  "d2",  "d3",  "d4",  "d5",  "d6",  "d7",  "d8",  "d9",  "d10", "d11",
+    "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
+    "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"};
 
 const char* VFPRegisters::Name(int reg, bool is_double) {
   DCHECK((0 <= reg) && (reg < kNumVFPRegisters));
   return names_[reg + (is_double ? kNumVFPSingleRegisters : 0)];
 }
 
-
 int VFPRegisters::Number(const char* name, bool* is_double) {
   for (int i = 0; i < kNumVFPRegisters; i++) {
     if (strcmp(names_[i], name) == 0) {
@@ -81,7 +73,6 @@ int VFPRegisters::Number(const char* name, bool* is_double) {
   return kNoRegister;
 }
 
-
 int Registers::Number(const char* name) {
   // Look through the canonical names.
   for (int i = 0; i < kNumRegisters; i++) {
@@ -103,7 +94,6 @@ int Registers::Number(const char* name) {
   return kNoRegister;
 }
 
-
 }  // namespace internal
 }  // namespace v8
 

src/arm/cpu-arm.cc → src/codegen/arm/cpu-arm.cc

@@ -6,7 +6,7 @@
 #ifdef __arm__
 #ifdef __QNXNTO__
 #include <sys/mman.h>  // for cache flushing.
-#undef MAP_TYPE
+#undef MAP_TYPE        // NOLINT
 #else
 #include <sys/syscall.h>  // for cache flushing.
 #endif
@@ -43,21 +43,21 @@ V8_NOINLINE void CpuFeatures::FlushICache(void* start, size_t size) {
   // Use a different variant of the asm with GCC because some versions doesn't
   // support r7 as an asm input.
   asm volatile(
-    // This assembly works for both ARM and Thumb targets.
+      // This assembly works for both ARM and Thumb targets.
 
-    // Preserve r7; it is callee-saved, and GCC uses it as a frame pointer for
-    // Thumb targets.
-    "  push {r7}\n"
-                                  // r0 = beg
-                                  // r1 = end
-                                  // r2 = flags (0)
-    "  ldr r7, =%c[scno]\n"       // r7 = syscall number
-    "  svc 0\n"
+      // Preserve r7; it is callee-saved, and GCC uses it as a frame pointer for
+      // Thumb targets.
+      "  push {r7}\n"
+      // r0 = beg
+      // r1 = end
+      // r2 = flags (0)
+      "  ldr r7, =%c[scno]\n"  // r7 = syscall number
+      "  svc 0\n"
 
-    "  pop {r7}\n"
-    :
-    : "r" (beg), "r" (end), "r" (flg), [scno] "i" (__ARM_NR_cacheflush)
-    : "memory");
+      "  pop {r7}\n"
+      :
+      : "r"(beg), "r"(end), "r"(flg), [scno] "i"(__ARM_NR_cacheflush)
+      : "memory");
 #endif
 #endif
 #endif  // !USE_SIMULATOR

src/arm/interface-descriptors-arm.cc → src/codegen/arm/interface-descriptors-arm.cc

@@ -74,7 +74,6 @@ const Register ApiGetterDescriptor::CallbackRegister() { return r3; }
 const Register GrowArrayElementsDescriptor::ObjectRegister() { return r0; }
 const Register GrowArrayElementsDescriptor::KeyRegister() { return r3; }
 
-
 // static
 const Register TypeConversionDescriptor::ArgumentRegister() { return r0; }
 

src/arm/macro-assembler-arm.cc → src/codegen/arm/macro-assembler-arm.cc

@@ -30,7 +30,7 @@
 // Satisfy cpplint check, but don't include platform-specific header. It is
 // included recursively via macro-assembler.h.
 #if 0
-#include "src/arm/macro-assembler-arm.h"
+#include "src/codegen/arm/macro-assembler-arm.h"
 #endif
 
 namespace v8 {
@@ -535,7 +535,6 @@ void MacroAssembler::Mls(Register dst, Register src1, Register src2,
   }
 }
 
-
 void MacroAssembler::And(Register dst, Register src1, const Operand& src2,
                          Condition cond) {
   if (!src2.IsRegister() && !src2.MustOutputRelocInfo(this) &&
@@ -547,13 +546,12 @@ void MacroAssembler::And(Register dst, Register src1, const Operand& src2,
              base::bits::IsPowerOfTwo(src2.immediate() + 1)) {
     CpuFeatureScope scope(this, ARMv7);
     ubfx(dst, src1, 0,
-        WhichPowerOf2(static_cast<uint32_t>(src2.immediate()) + 1), cond);
+         WhichPowerOf2(static_cast<uint32_t>(src2.immediate()) + 1), cond);
   } else {
     and_(dst, src1, src2, LeaveCC, cond);
   }
 }
 
-
 void MacroAssembler::Ubfx(Register dst, Register src1, int lsb, int width,
                           Condition cond) {
   DCHECK_LT(lsb, 32);
@@ -569,7 +567,6 @@ void MacroAssembler::Ubfx(Register dst, Register src1, int lsb, int width,
   }
 }
 
-
 void MacroAssembler::Sbfx(Register dst, Register src1, int lsb, int width,
                           Condition cond) {
   DCHECK_LT(lsb, 32);
@@ -590,7 +587,6 @@ void MacroAssembler::Sbfx(Register dst, Register src1, int lsb, int width,
   }
 }
 
-
 void TurboAssembler::Bfc(Register dst, Register src, int lsb, int width,
                          Condition cond) {
   DCHECK_LT(lsb, 32);
@@ -843,8 +839,9 @@ void TurboAssembler::PushCommonFrame(Register marker_reg) {
 
 void TurboAssembler::PushStandardFrame(Register function_reg) {
   DCHECK(!function_reg.is_valid() || function_reg.code() < cp.code());
-  stm(db_w, sp, (function_reg.is_valid() ? function_reg.bit() : 0) | cp.bit() |
-                    fp.bit() | lr.bit());
+  stm(db_w, sp,
+      (function_reg.is_valid() ? function_reg.bit() : 0) | cp.bit() | fp.bit() |
+          lr.bit());
   int offset = -StandardFrameConstants::kContextOffset;
   offset += function_reg.is_valid() ? kPointerSize : 0;
   add(fp, sp, Operand(offset));
@@ -1400,7 +1397,7 @@ int TurboAssembler::ActivationFrameAlignment() {
   // Note: This will break if we ever start generating snapshots on one ARM
   // platform for another ARM platform with a different alignment.
   return base::OS::ActivationFrameAlignment();
-#else  // V8_HOST_ARCH_ARM
+#else   // V8_HOST_ARCH_ARM
   // If we are using the simulator then we should always align to the expected
   // alignment. As the simulator is used to generate snapshots we do not know
   // if the target platform will need alignment, so this is controlled from a
@@ -1460,7 +1457,6 @@ void TurboAssembler::MovFromFloatResult(const DwVfpRegister dst) {
   }
 }
 
-
 // On ARM this is just a synonym to make the purpose clear.
 void TurboAssembler::MovFromFloatParameter(DwVfpRegister dst) {
   MovFromFloatResult(dst);
@@ -1744,7 +1740,6 @@ void MacroAssembler::PushStackHandler() {
   str(sp, MemOperand(r6));
 }
 
-
 void MacroAssembler::PopStackHandler() {
   UseScratchRegisterScope temps(this);
   Register scratch = temps.Acquire();
@@ -1756,11 +1751,8 @@ void MacroAssembler::PopStackHandler() {
   add(sp, sp, Operand(StackHandlerConstants::kSize - kPointerSize));
 }
 
-
-void MacroAssembler::CompareObjectType(Register object,
-                                       Register map,
-                                       Register type_reg,
-                                       InstanceType type) {
+void MacroAssembler::CompareObjectType(Register object, Register map,
+                                       Register type_reg, InstanceType type) {
   UseScratchRegisterScope temps(this);
   const Register temp = type_reg == no_reg ? temps.Acquire() : type_reg;
 
@@ -1768,9 +1760,7 @@ void MacroAssembler::CompareObjectType(Register object,
   CompareInstanceType(map, temp, type);
 }
 
-
-void MacroAssembler::CompareInstanceType(Register map,
-                                         Register type_reg,
+void MacroAssembler::CompareInstanceType(Register map, Register type_reg,
                                          InstanceType type) {
   ldrh(type_reg, FieldMemOperand(map, Map::kInstanceTypeOffset));
   cmp(type_reg, Operand(type));
@@ -1862,8 +1852,7 @@ void TurboAssembler::CallRuntimeWithCEntry(Runtime::FunctionId fid,
   CallCodeObject(centry);
 }
 
-void MacroAssembler::CallRuntime(const Runtime::Function* f,
-                                 int num_arguments,
+void MacroAssembler::CallRuntime(const Runtime::Function* f, int num_arguments,
                                  SaveFPRegsMode save_doubles) {
   // All parameters are on the stack.  r0 has the return value after call.
 
@@ -1932,7 +1921,6 @@ void MacroAssembler::IncrementCounter(StatsCounter* counter, int value,
   }
 }
 
-
 void MacroAssembler::DecrementCounter(StatsCounter* counter, int value,
                                       Register scratch1, Register scratch2) {
   DCHECK_GT(value, 0);
@@ -1945,8 +1933,7 @@ void MacroAssembler::DecrementCounter(StatsCounter* counter, int value,
 }
 
 void TurboAssembler::Assert(Condition cond, AbortReason reason) {
-  if (emit_debug_code())
-    Check(cond, reason);
+  if (emit_debug_code()) Check(cond, reason);
 }
 
 void TurboAssembler::AssertUnreachable(AbortReason reason) {
@@ -2011,7 +1998,6 @@ void MacroAssembler::LoadNativeContextSlot(int index, Register dst) {
   ldr(dst, ContextMemOperand(dst, index));
 }
 
-
 void TurboAssembler::InitializeRootRegister() {
   ExternalReference isolate_root = ExternalReference::isolate_root(isolate());
   mov(kRootRegister, Operand(isolate_root));
@@ -2057,7 +2043,6 @@ void MacroAssembler::AssertNotSmi(Register object) {
   }
 }
 
-
 void MacroAssembler::AssertSmi(Register object) {
   if (emit_debug_code()) {
     STATIC_ASSERT(kSmiTag == 0);
@@ -2092,7 +2077,6 @@ void MacroAssembler::AssertFunction(Register object) {
   }
 }
 
-
 void MacroAssembler::AssertBoundFunction(Register object) {
   if (emit_debug_code()) {
     STATIC_ASSERT(kSmiTag == 0);
@@ -2148,7 +2132,6 @@ void MacroAssembler::AssertUndefinedOrAllocationSite(Register object,
   }
 }
 
-
 void TurboAssembler::CheckFor32DRegs(Register scratch) {
   Move(scratch, ExternalReference::cpu_features());
   ldr(scratch, MemOperand(scratch));
@@ -2338,8 +2321,8 @@ void TurboAssembler::PrepareCallCFunction(int num_reg_arguments,
                                           int num_double_arguments,
                                           Register scratch) {
   int frame_alignment = ActivationFrameAlignment();
-  int stack_passed_arguments = CalculateStackPassedWords(
-      num_reg_arguments, num_double_arguments);
+  int stack_passed_arguments =
+      CalculateStackPassedWords(num_reg_arguments, num_double_arguments);
   if (frame_alignment > kPointerSize) {
     UseScratchRegisterScope temps(this);
     if (!scratch.is_valid()) scratch = temps.Acquire();
@@ -2362,7 +2345,6 @@ void TurboAssembler::MovToFloatParameter(DwVfpRegister src) {
   }
 }
 
-
 // On ARM this is just a synonym to make the purpose clear.
 void TurboAssembler::MovToFloatResult(DwVfpRegister src) {
   MovToFloatParameter(src);
@@ -2457,8 +2439,8 @@ void TurboAssembler::CallCFunctionHelper(Register function,
     Pop(scratch1);
   }
 
-  int stack_passed_arguments = CalculateStackPassedWords(
-      num_reg_arguments, num_double_arguments);
+  int stack_passed_arguments =
+      CalculateStackPassedWords(num_reg_arguments, num_double_arguments);
   if (ActivationFrameAlignment() > kPointerSize) {
     ldr(sp, MemOperand(sp, stack_passed_arguments * kPointerSize));
   } else {
@@ -2477,11 +2459,8 @@ void TurboAssembler::CheckPageFlag(Register object, int mask, Condition cc,
   b(cc, condition_met);
 }
 
-Register GetRegisterThatIsNotOneOf(Register reg1,
-                                   Register reg2,
-                                   Register reg3,
-                                   Register reg4,
-                                   Register reg5,
+Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3,
+                                   Register reg4, Register reg5,
                                    Register reg6) {
   RegList regs = 0;
   if (reg1.is_valid()) regs |= reg1.bit();

src/arm/macro-assembler-arm.h → src/codegen/arm/macro-assembler-arm.h

@@ -6,10 +6,10 @@
 #error This header must be included via macro-assembler.h
 #endif
 
-#ifndef V8_ARM_MACRO_ASSEMBLER_ARM_H_
-#define V8_ARM_MACRO_ASSEMBLER_ARM_H_
+#ifndef V8_CODEGEN_ARM_MACRO_ASSEMBLER_ARM_H_
+#define V8_CODEGEN_ARM_MACRO_ASSEMBLER_ARM_H_
 
-#include "src/arm/assembler-arm.h"
+#include "src/codegen/arm/assembler-arm.h"
 #include "src/codegen/bailout-reason.h"
 #include "src/common/globals.h"
 #include "src/objects/contexts.h"
@@ -29,9 +29,7 @@ enum RememberedSetAction { EMIT_REMEMBERED_SET, OMIT_REMEMBERED_SET };
 enum SmiCheck { INLINE_SMI_CHECK, OMIT_SMI_CHECK };
 enum LinkRegisterStatus { kLRHasNotBeenSaved, kLRHasBeenSaved };
 
-
-Register GetRegisterThatIsNotOneOf(Register reg1,
-                                   Register reg2 = no_reg,
+Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2 = no_reg,
                                    Register reg3 = no_reg,
                                    Register reg4 = no_reg,
                                    Register reg5 = no_reg,
@@ -666,17 +664,13 @@ class V8_EXPORT_PRIVATE MacroAssembler : public TurboAssembler {
   // register unless the heap_object register is the same register as one of the
   // other registers.
   // Type_reg can be no_reg. In that case a scratch register is used.
-  void CompareObjectType(Register heap_object,
-                         Register map,
-                         Register type_reg,
+  void CompareObjectType(Register heap_object, Register map, Register type_reg,
                          InstanceType type);
 
   // Compare instance type in a map.  map contains a valid map object whose
   // object type should be compared with the given type.  This both
   // sets the flags and leaves the object type in the type_reg register.
-  void CompareInstanceType(Register map,
-                           Register type_reg,
-                           InstanceType type);
+  void CompareInstanceType(Register map, Register type_reg, InstanceType type);
 
   // Compare the object in a register to a value from the root list.
   // Acquires a scratch register.
@@ -709,8 +703,7 @@ class V8_EXPORT_PRIVATE MacroAssembler : public TurboAssembler {
   // Runtime calls
 
   // Call a runtime routine.
-  void CallRuntime(const Runtime::Function* f,
-                   int num_arguments,
+  void CallRuntime(const Runtime::Function* f, int num_arguments,
                    SaveFPRegsMode save_doubles = kDontSaveFPRegs);
 
   // Convenience function: Same as above, but takes the fid instead.
@@ -743,10 +736,10 @@ class V8_EXPORT_PRIVATE MacroAssembler : public TurboAssembler {
   // ---------------------------------------------------------------------------
   // StatsCounter support
 
-  void IncrementCounter(StatsCounter* counter, int value,
-                        Register scratch1, Register scratch2);
-  void DecrementCounter(StatsCounter* counter, int value,
-                        Register scratch1, Register scratch2);
+  void IncrementCounter(StatsCounter* counter, int value, Register scratch1,
+                        Register scratch2);
+  void DecrementCounter(StatsCounter* counter, int value, Register scratch1,
+                        Register scratch2);
 
   // ---------------------------------------------------------------------------
   // Smi utilities
@@ -781,12 +774,12 @@ class V8_EXPORT_PRIVATE MacroAssembler : public TurboAssembler {
   // via --debug-code.
   void AssertUndefinedOrAllocationSite(Register object, Register scratch);
 
-  template<typename Field>
+  template <typename Field>
   void DecodeField(Register dst, Register src) {
     Ubfx(dst, src, Field::kShift, Field::kSize);
   }
 
-  template<typename Field>
+  template <typename Field>
   void DecodeField(Register reg) {
     DecodeField<Field>(reg, reg);
   }
@@ -814,7 +807,6 @@ inline MemOperand ContextMemOperand(Register context, int index = 0) {
   return MemOperand(context, Context::SlotOffset(index));
 }
 
-
 inline MemOperand NativeContextMemOperand() {
   return ContextMemOperand(cp, Context::NATIVE_CONTEXT_INDEX);
 }
@@ -824,4 +816,4 @@ inline MemOperand NativeContextMemOperand() {
 }  // namespace internal
 }  // namespace v8
 
-#endif  // V8_ARM_MACRO_ASSEMBLER_ARM_H_
+#endif  // V8_CODEGEN_ARM_MACRO_ASSEMBLER_ARM_H_

src/arm/register-arm.h → src/codegen/arm/register-arm.h

@@ -2,8 +2,8 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
-#ifndef V8_ARM_REGISTER_ARM_H_
-#define V8_ARM_REGISTER_ARM_H_
+#ifndef V8_CODEGEN_ARM_REGISTER_ARM_H_
+#define V8_CODEGEN_ARM_REGISTER_ARM_H_
 
 #include "src/codegen/register.h"
 #include "src/codegen/reglist.h"
@@ -366,4 +366,4 @@ constexpr Register kRootRegister = r10;  // Roots array pointer.
 }  // namespace internal
 }  // namespace v8
 
-#endif  // V8_ARM_REGISTER_ARM_H_
+#endif  // V8_CODEGEN_ARM_REGISTER_ARM_H_

src/arm64/cpu-arm64.cc → src/codegen/arm64/cpu-arm64.cc

@@ -6,7 +6,7 @@
 
 #if V8_TARGET_ARCH_ARM64
 
-#include "src/arm64/utils-arm64.h"
+#include "src/codegen/arm64/utils-arm64.h"
 #include "src/codegen/cpu-features.h"
 
 namespace v8 {
@@ -58,58 +58,54 @@ void CpuFeatures::FlushICache(void* address, size_t length) {
   uintptr_t istart = start & ~(isize - 1);
   uintptr_t end = start + length;
 
-  __asm__ __volatile__ (  // NOLINT
-    // Clean every line of the D cache containing the target data.
-    "0:                                \n\t"
-    // dc       : Data Cache maintenance
-    //    c     : Clean
-    //     i    : Invalidate
-    //      va  : by (Virtual) Address
-    //        c : to the point of Coherency
-    // See ARM DDI 0406B page B2-12 for more information.
-    // We would prefer to use "cvau" (clean to the point of unification) here
-    // but we use "civac" to work around Cortex-A53 errata 819472, 826319,
-    // 827319 and 824069.
-    "dc   civac, %[dline]               \n\t"
-    "add  %[dline], %[dline], %[dsize]  \n\t"
-    "cmp  %[dline], %[end]              \n\t"
-    "b.lt 0b                            \n\t"
-    // Barrier to make sure the effect of the code above is visible to the rest
-    // of the world.
-    // dsb    : Data Synchronisation Barrier
-    //    ish : Inner SHareable domain
-    // The point of unification for an Inner Shareable shareability domain is
-    // the point by which the instruction and data caches of all the processors
-    // in that Inner Shareable shareability domain are guaranteed to see the
-    // same copy of a memory location.  See ARM DDI 0406B page B2-12 for more
-    // information.
-    "dsb  ish                           \n\t"
-    // Invalidate every line of the I cache containing the target data.
-    "1:                                 \n\t"
-    // ic      : instruction cache maintenance
-    //    i    : invalidate
-    //     va  : by address
-    //       u : to the point of unification
-    "ic   ivau, %[iline]                \n\t"
-    "add  %[iline], %[iline], %[isize]  \n\t"
-    "cmp  %[iline], %[end]              \n\t"
-    "b.lt 1b                            \n\t"
-    // Barrier to make sure the effect of the code above is visible to the rest
-    // of the world.
-    "dsb  ish                           \n\t"
-    // Barrier to ensure any prefetching which happened before this code is
-    // discarded.
-    // isb : Instruction Synchronisation Barrier
-    "isb                                \n\t"
-    : [dline] "+r" (dstart),
-      [iline] "+r" (istart)
-    : [dsize] "r"  (dsize),
-      [isize] "r"  (isize),
-      [end]   "r"  (end)
-    // This code does not write to memory but without the dependency gcc might
-    // move this code before the code is generated.
-    : "cc", "memory"
-  );  // NOLINT
+  __asm__ __volatile__(  // NOLINT
+                         // Clean every line of the D cache containing the
+                         // target data.
+      "0:                                \n\t"
+      // dc       : Data Cache maintenance
+      //    c     : Clean
+      //     i    : Invalidate
+      //      va  : by (Virtual) Address
+      //        c : to the point of Coherency
+      // See ARM DDI 0406B page B2-12 for more information.
+      // We would prefer to use "cvau" (clean to the point of unification) here
+      // but we use "civac" to work around Cortex-A53 errata 819472, 826319,
+      // 827319 and 824069.
+      "dc   civac, %[dline]               \n\t"
+      "add  %[dline], %[dline], %[dsize]  \n\t"
+      "cmp  %[dline], %[end]              \n\t"
+      "b.lt 0b                            \n\t"
+      // Barrier to make sure the effect of the code above is visible to the
+      // rest of the world. dsb    : Data Synchronisation Barrier
+      //    ish : Inner SHareable domain
+      // The point of unification for an Inner Shareable shareability domain is
+      // the point by which the instruction and data caches of all the
+      // processors in that Inner Shareable shareability domain are guaranteed
+      // to see the same copy of a memory location.  See ARM DDI 0406B page
+      // B2-12 for more information.
+      "dsb  ish                           \n\t"
+      // Invalidate every line of the I cache containing the target data.
+      "1:                                 \n\t"
+      // ic      : instruction cache maintenance
+      //    i    : invalidate
+      //     va  : by address
+      //       u : to the point of unification
+      "ic   ivau, %[iline]                \n\t"
+      "add  %[iline], %[iline], %[isize]  \n\t"
+      "cmp  %[iline], %[end]              \n\t"
+      "b.lt 1b                            \n\t"
+      // Barrier to make sure the effect of the code above is visible to the
+      // rest of the world.
+      "dsb  ish                           \n\t"
+      // Barrier to ensure any prefetching which happened before this code is
+      // discarded.
+      // isb : Instruction Synchronisation Barrier
+      "isb                                \n\t"
+      : [dline] "+r"(dstart), [iline] "+r"(istart)
+      : [dsize] "r"(dsize), [isize] "r"(isize), [end] "r"(end)
+      // This code does not write to memory but without the dependency gcc might
+      // move this code before the code is generated.
+      : "cc", "memory");  // NOLINT
 #endif  // V8_OS_WIN
 #endif  // V8_HOST_ARCH_ARM64
 }

src/arm64/decoder-arm64.cc → src/codegen/arm64/decoder-arm64.cc

@@ -4,26 +4,23 @@
 
 #if V8_TARGET_ARCH_ARM64
 
-#include "src/arm64/decoder-arm64.h"
+#include "src/codegen/arm64/decoder-arm64.h"
 #include "src/common/globals.h"
 #include "src/utils/utils.h"
 
 namespace v8 {
 namespace internal {
 
-
 void DispatchingDecoderVisitor::AppendVisitor(DecoderVisitor* new_visitor) {
   visitors_.remove(new_visitor);
   visitors_.push_back(new_visitor);
 }
 
-
 void DispatchingDecoderVisitor::PrependVisitor(DecoderVisitor* new_visitor) {
   visitors_.remove(new_visitor);
   visitors_.push_front(new_visitor);
 }
 
-
 void DispatchingDecoderVisitor::InsertVisitorBefore(
     DecoderVisitor* new_visitor, DecoderVisitor* registered_visitor) {
   visitors_.remove(new_visitor);
@@ -40,7 +37,6 @@ void DispatchingDecoderVisitor::InsertVisitorBefore(
   visitors_.insert(it, new_visitor);
 }
 
-
 void DispatchingDecoderVisitor::InsertVisitorAfter(
     DecoderVisitor* new_visitor, DecoderVisitor* registered_visitor) {
   visitors_.remove(new_visitor);
@@ -58,12 +54,10 @@ void DispatchingDecoderVisitor::InsertVisitorAfter(
   visitors_.push_back(new_visitor);
 }
 
-
 void DispatchingDecoderVisitor::RemoveVisitor(DecoderVisitor* visitor) {
   visitors_.remove(visitor);
 }
 
-
 #define DEFINE_VISITOR_CALLERS(A)                                \
   void DispatchingDecoderVisitor::Visit##A(Instruction* instr) { \
     if (!(instr->Mask(A##FMask) == A##Fixed)) {                  \
@@ -77,7 +71,6 @@ void DispatchingDecoderVisitor::RemoveVisitor(DecoderVisitor* visitor) {
 VISITOR_LIST(DEFINE_VISITOR_CALLERS)
 #undef DEFINE_VISITOR_CALLERS
 
-
 }  // namespace internal
 }  // namespace v8
 

src/arm64/decoder-arm64.h → src/codegen/arm64/decoder-arm64.h

@@ -2,18 +2,17 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
-#ifndef V8_ARM64_DECODER_ARM64_H_
-#define V8_ARM64_DECODER_ARM64_H_
+#ifndef V8_CODEGEN_ARM64_DECODER_ARM64_H_
+#define V8_CODEGEN_ARM64_DECODER_ARM64_H_
 
 #include <list>
 
-#include "src/arm64/instructions-arm64.h"
+#include "src/codegen/arm64/instructions-arm64.h"
 #include "src/common/globals.h"
 
 namespace v8 {
 namespace internal {
 
-
 // List macro containing all visitors needed by the decoder class.
 
 #define VISITOR_LIST(V)                 \
@@ -90,9 +89,9 @@ class V8_EXPORT_PRIVATE DecoderVisitor {
  public:
   virtual ~DecoderVisitor() {}
 
-  #define DECLARE(A) virtual void Visit##A(Instruction* instr) = 0;
+#define DECLARE(A) virtual void Visit##A(Instruction* instr) = 0;
   VISITOR_LIST(DECLARE)
-  #undef DECLARE
+#undef DECLARE
 };
 
 // A visitor that dispatches to a list of visitors.
@@ -132,16 +131,16 @@ class V8_EXPORT_PRIVATE DispatchingDecoderVisitor : public DecoderVisitor {
 
   void VisitNEONShiftImmediate(const Instruction* instr);
 
-  #define DECLARE(A) void Visit##A(Instruction* instr);
+#define DECLARE(A) void Visit##A(Instruction* instr);
   VISITOR_LIST(DECLARE)
-  #undef DECLARE
+#undef DECLARE
 
  private:
   // Visitors are registered in a list.
   std::list<DecoderVisitor*> visitors_;
 };
 
-template<typename V>
+template <typename V>
 class Decoder : public V {
  public:
   Decoder() {}
@@ -149,7 +148,7 @@ class Decoder : public V {
 
   // Top-level instruction decoder function. Decodes an instruction and calls
   // the visitor functions registered with the Decoder class.
-  virtual void Decode(Instruction *instr);
+  virtual void Decode(Instruction* instr);
 
  private:
   // Decode the PC relative addressing instruction, and call the corresponding
@@ -208,8 +207,7 @@ class Decoder : public V {
   void DecodeNEONScalarDataProcessing(Instruction* instr);
 };
 
-
 }  // namespace internal
 }  // namespace v8
 
-#endif  // V8_ARM64_DECODER_ARM64_H_
+#endif  // V8_CODEGEN_ARM64_DECODER_ARM64_H_

src/arm64/interface-descriptors-arm64.cc → src/codegen/arm64/interface-descriptors-arm64.cc

@@ -74,7 +74,6 @@ const Register ApiGetterDescriptor::CallbackRegister() { return x3; }
 const Register GrowArrayElementsDescriptor::ObjectRegister() { return x0; }
 const Register GrowArrayElementsDescriptor::KeyRegister() { return x3; }
 
-
 // static
 const Register TypeConversionDescriptor::ArgumentRegister() { return x0; }
 

src/arm64/register-arm64.cc → src/codegen/arm64/register-arm64.cc

@@ -4,7 +4,7 @@
 
 #if V8_TARGET_ARCH_ARM64
 
-#include "src/arm64/register-arm64.h"
+#include "src/codegen/arm64/register-arm64.h"
 
 namespace v8 {
 namespace internal {