instruction-selector-ppc.cc 70.6 KB
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// Copyright 2014 the V8 project authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.

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#include "src/base/adapters.h"
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#include "src/compiler/instruction-selector-impl.h"
#include "src/compiler/node-matchers.h"
#include "src/compiler/node-properties.h"
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#include "src/ppc/frames-ppc.h"
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namespace v8 {
namespace internal {
namespace compiler {

enum ImmediateMode {
  kInt16Imm,
  kInt16Imm_Unsigned,
  kInt16Imm_Negate,
  kInt16Imm_4ByteAligned,
  kShift32Imm,
  kShift64Imm,
  kNoImmediate
};


// Adds PPC-specific methods for generating operands.
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class PPCOperandGenerator final : public OperandGenerator {
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 public:
  explicit PPCOperandGenerator(InstructionSelector* selector)
      : OperandGenerator(selector) {}

  InstructionOperand UseOperand(Node* node, ImmediateMode mode) {
    if (CanBeImmediate(node, mode)) {
      return UseImmediate(node);
    }
    return UseRegister(node);
  }

  bool CanBeImmediate(Node* node, ImmediateMode mode) {
    int64_t value;
    if (node->opcode() == IrOpcode::kInt32Constant)
      value = OpParameter<int32_t>(node);
    else if (node->opcode() == IrOpcode::kInt64Constant)
      value = OpParameter<int64_t>(node);
    else
      return false;
    return CanBeImmediate(value, mode);
  }

  bool CanBeImmediate(int64_t value, ImmediateMode mode) {
    switch (mode) {
      case kInt16Imm:
        return is_int16(value);
      case kInt16Imm_Unsigned:
        return is_uint16(value);
      case kInt16Imm_Negate:
        return is_int16(-value);
      case kInt16Imm_4ByteAligned:
        return is_int16(value) && !(value & 3);
      case kShift32Imm:
        return 0 <= value && value < 32;
      case kShift64Imm:
        return 0 <= value && value < 64;
      case kNoImmediate:
        return false;
    }
    return false;
  }
};


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namespace {
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void VisitRR(InstructionSelector* selector, InstructionCode opcode,
             Node* node) {
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  PPCOperandGenerator g(selector);
  selector->Emit(opcode, g.DefineAsRegister(node),
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                 g.UseRegister(node->InputAt(0)));
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}

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void VisitRRR(InstructionSelector* selector, InstructionCode opcode,
              Node* node) {
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  PPCOperandGenerator g(selector);
  selector->Emit(opcode, g.DefineAsRegister(node),
                 g.UseRegister(node->InputAt(0)),
                 g.UseRegister(node->InputAt(1)));
}

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void VisitRRO(InstructionSelector* selector, InstructionCode opcode, Node* node,
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              ImmediateMode operand_mode) {
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  PPCOperandGenerator g(selector);
  selector->Emit(opcode, g.DefineAsRegister(node),
                 g.UseRegister(node->InputAt(0)),
                 g.UseOperand(node->InputAt(1), operand_mode));
}


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#if V8_TARGET_ARCH_PPC64
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void VisitTryTruncateDouble(InstructionSelector* selector,
                            InstructionCode opcode, Node* node) {
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  PPCOperandGenerator g(selector);
  InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0))};
  InstructionOperand outputs[2];
  size_t output_count = 0;
  outputs[output_count++] = g.DefineAsRegister(node);

  Node* success_output = NodeProperties::FindProjection(node, 1);
  if (success_output) {
    outputs[output_count++] = g.DefineAsRegister(success_output);
  }

  selector->Emit(opcode, output_count, outputs, 1, inputs);
}
#endif


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// Shared routine for multiple binary operations.
template <typename Matcher>
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void VisitBinop(InstructionSelector* selector, Node* node,
                InstructionCode opcode, ImmediateMode operand_mode,
                FlagsContinuation* cont) {
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  PPCOperandGenerator g(selector);
  Matcher m(node);
  InstructionOperand inputs[4];
  size_t input_count = 0;
  InstructionOperand outputs[2];
  size_t output_count = 0;

  inputs[input_count++] = g.UseRegister(m.left().node());
  inputs[input_count++] = g.UseOperand(m.right().node(), operand_mode);

  if (cont->IsBranch()) {
    inputs[input_count++] = g.Label(cont->true_block());
    inputs[input_count++] = g.Label(cont->false_block());
  }

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  if (cont->IsDeoptimize()) {
    // If we can deoptimize as a result of the binop, we need to make sure that
    // the deopt inputs are not overwritten by the binop result. One way
    // to achieve that is to declare the output register as same-as-first.
    outputs[output_count++] = g.DefineSameAsFirst(node);
  } else {
    outputs[output_count++] = g.DefineAsRegister(node);
  }
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  if (cont->IsSet()) {
    outputs[output_count++] = g.DefineAsRegister(cont->result());
  }

  DCHECK_NE(0u, input_count);
  DCHECK_NE(0u, output_count);
  DCHECK_GE(arraysize(inputs), input_count);
  DCHECK_GE(arraysize(outputs), output_count);

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  opcode = cont->Encode(opcode);
  if (cont->IsDeoptimize()) {
    selector->EmitDeoptimize(opcode, output_count, outputs, input_count, inputs,
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                             cont->kind(), cont->reason(), cont->frame_state());
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  } else if (cont->IsTrap()) {
    inputs[input_count++] = g.UseImmediate(cont->trap_id());
    selector->Emit(opcode, output_count, outputs, input_count, inputs);
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  } else {
    selector->Emit(opcode, output_count, outputs, input_count, inputs);
  }
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}


// Shared routine for multiple binary operations.
template <typename Matcher>
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void VisitBinop(InstructionSelector* selector, Node* node,
                InstructionCode opcode, ImmediateMode operand_mode) {
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  FlagsContinuation cont;
  VisitBinop<Matcher>(selector, node, opcode, operand_mode, &cont);
}

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}  // namespace

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void InstructionSelector::VisitLoad(Node* node) {
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  LoadRepresentation load_rep = LoadRepresentationOf(node->op());
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  PPCOperandGenerator g(this);
  Node* base = node->InputAt(0);
  Node* offset = node->InputAt(1);
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  ArchOpcode opcode = kArchNop;
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  ImmediateMode mode = kInt16Imm;
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  switch (load_rep.representation()) {
    case MachineRepresentation::kFloat32:
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      opcode = kPPC_LoadFloat32;
      break;
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    case MachineRepresentation::kFloat64:
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      opcode = kPPC_LoadDouble;
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      break;
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    case MachineRepresentation::kBit:  // Fall through.
    case MachineRepresentation::kWord8:
      opcode = load_rep.IsSigned() ? kPPC_LoadWordS8 : kPPC_LoadWordU8;
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      break;
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    case MachineRepresentation::kWord16:
      opcode = load_rep.IsSigned() ? kPPC_LoadWordS16 : kPPC_LoadWordU16;
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      break;
#if !V8_TARGET_ARCH_PPC64
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    case MachineRepresentation::kTaggedSigned:   // Fall through.
    case MachineRepresentation::kTaggedPointer:  // Fall through.
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    case MachineRepresentation::kTagged:  // Fall through.
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#endif
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    case MachineRepresentation::kWord32:
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      opcode = kPPC_LoadWordU32;
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      break;
#if V8_TARGET_ARCH_PPC64
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    case MachineRepresentation::kTaggedSigned:   // Fall through.
    case MachineRepresentation::kTaggedPointer:  // Fall through.
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    case MachineRepresentation::kTagged:  // Fall through.
    case MachineRepresentation::kWord64:
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      opcode = kPPC_LoadWord64;
      mode = kInt16Imm_4ByteAligned;
      break;
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#else
    case MachineRepresentation::kWord64:  // Fall through.
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#endif
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    case MachineRepresentation::kSimd128:  // Fall through.
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    case MachineRepresentation::kSimd1x4:  // Fall through.
    case MachineRepresentation::kSimd1x8:  // Fall through.
    case MachineRepresentation::kSimd1x16:  // Fall through.
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    case MachineRepresentation::kNone:
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      UNREACHABLE();
      return;
  }
  if (g.CanBeImmediate(offset, mode)) {
    Emit(opcode | AddressingModeField::encode(kMode_MRI),
         g.DefineAsRegister(node), g.UseRegister(base), g.UseImmediate(offset));
  } else if (g.CanBeImmediate(base, mode)) {
    Emit(opcode | AddressingModeField::encode(kMode_MRI),
         g.DefineAsRegister(node), g.UseRegister(offset), g.UseImmediate(base));
  } else {
    Emit(opcode | AddressingModeField::encode(kMode_MRR),
         g.DefineAsRegister(node), g.UseRegister(base), g.UseRegister(offset));
  }
}

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void InstructionSelector::VisitProtectedLoad(Node* node) {
  // TODO(eholk)
  UNIMPLEMENTED();
}
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void InstructionSelector::VisitStore(Node* node) {
  PPCOperandGenerator g(this);
  Node* base = node->InputAt(0);
  Node* offset = node->InputAt(1);
  Node* value = node->InputAt(2);

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  StoreRepresentation store_rep = StoreRepresentationOf(node->op());
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  WriteBarrierKind write_barrier_kind = store_rep.write_barrier_kind();
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  MachineRepresentation rep = store_rep.representation();
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  if (write_barrier_kind != kNoWriteBarrier) {
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    DCHECK(CanBeTaggedPointer(rep));
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    AddressingMode addressing_mode;
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    InstructionOperand inputs[3];
    size_t input_count = 0;
    inputs[input_count++] = g.UseUniqueRegister(base);
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    // OutOfLineRecordWrite uses the offset in an 'add' instruction as well as
    // for the store itself, so we must check compatibility with both.
    if (g.CanBeImmediate(offset, kInt16Imm)
#if V8_TARGET_ARCH_PPC64
        && g.CanBeImmediate(offset, kInt16Imm_4ByteAligned)
#endif
            ) {
      inputs[input_count++] = g.UseImmediate(offset);
      addressing_mode = kMode_MRI;
    } else {
      inputs[input_count++] = g.UseUniqueRegister(offset);
      addressing_mode = kMode_MRR;
    }
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    inputs[input_count++] = g.UseUniqueRegister(value);
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    RecordWriteMode record_write_mode = RecordWriteMode::kValueIsAny;
    switch (write_barrier_kind) {
      case kNoWriteBarrier:
        UNREACHABLE();
        break;
      case kMapWriteBarrier:
        record_write_mode = RecordWriteMode::kValueIsMap;
        break;
      case kPointerWriteBarrier:
        record_write_mode = RecordWriteMode::kValueIsPointer;
        break;
      case kFullWriteBarrier:
        record_write_mode = RecordWriteMode::kValueIsAny;
        break;
    }
    InstructionOperand temps[] = {g.TempRegister(), g.TempRegister()};
    size_t const temp_count = arraysize(temps);
    InstructionCode code = kArchStoreWithWriteBarrier;
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    code |= AddressingModeField::encode(addressing_mode);
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    code |= MiscField::encode(static_cast<int>(record_write_mode));
    Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
  } else {
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    ArchOpcode opcode = kArchNop;
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    ImmediateMode mode = kInt16Imm;
    switch (rep) {
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      case MachineRepresentation::kFloat32:
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        opcode = kPPC_StoreFloat32;
        break;
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      case MachineRepresentation::kFloat64:
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        opcode = kPPC_StoreDouble;
        break;
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      case MachineRepresentation::kBit:  // Fall through.
      case MachineRepresentation::kWord8:
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        opcode = kPPC_StoreWord8;
        break;
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      case MachineRepresentation::kWord16:
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        opcode = kPPC_StoreWord16;
        break;
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#if !V8_TARGET_ARCH_PPC64
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      case MachineRepresentation::kTaggedSigned:   // Fall through.
      case MachineRepresentation::kTaggedPointer:  // Fall through.
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      case MachineRepresentation::kTagged:  // Fall through.
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#endif
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      case MachineRepresentation::kWord32:
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        opcode = kPPC_StoreWord32;
        break;
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#if V8_TARGET_ARCH_PPC64
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      case MachineRepresentation::kTaggedSigned:   // Fall through.
      case MachineRepresentation::kTaggedPointer:  // Fall through.
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      case MachineRepresentation::kTagged:  // Fall through.
      case MachineRepresentation::kWord64:
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        opcode = kPPC_StoreWord64;
        mode = kInt16Imm_4ByteAligned;
        break;
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#else
      case MachineRepresentation::kWord64:  // Fall through.
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#endif
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      case MachineRepresentation::kSimd128:  // Fall through.
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      case MachineRepresentation::kSimd1x4:  // Fall through.
      case MachineRepresentation::kSimd1x8:  // Fall through.
      case MachineRepresentation::kSimd1x16:  // Fall through.
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      case MachineRepresentation::kNone:
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        UNREACHABLE();
        return;
    }
    if (g.CanBeImmediate(offset, mode)) {
      Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(),
           g.UseRegister(base), g.UseImmediate(offset), g.UseRegister(value));
    } else if (g.CanBeImmediate(base, mode)) {
      Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(),
           g.UseRegister(offset), g.UseImmediate(base), g.UseRegister(value));
    } else {
      Emit(opcode | AddressingModeField::encode(kMode_MRR), g.NoOutput(),
           g.UseRegister(base), g.UseRegister(offset), g.UseRegister(value));
    }
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  }
}

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void InstructionSelector::VisitProtectedStore(Node* node) {
  // TODO(eholk)
  UNIMPLEMENTED();
}

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// Architecture supports unaligned access, therefore VisitLoad is used instead
void InstructionSelector::VisitUnalignedLoad(Node* node) { UNREACHABLE(); }

// Architecture supports unaligned access, therefore VisitStore is used instead
void InstructionSelector::VisitUnalignedStore(Node* node) { UNREACHABLE(); }
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void InstructionSelector::VisitCheckedLoad(Node* node) {
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  CheckedLoadRepresentation load_rep = CheckedLoadRepresentationOf(node->op());
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  PPCOperandGenerator g(this);
  Node* const base = node->InputAt(0);
  Node* const offset = node->InputAt(1);
  Node* const length = node->InputAt(2);
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  ArchOpcode opcode = kArchNop;
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  switch (load_rep.representation()) {
    case MachineRepresentation::kWord8:
      opcode = load_rep.IsSigned() ? kCheckedLoadInt8 : kCheckedLoadUint8;
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      break;
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    case MachineRepresentation::kWord16:
      opcode = load_rep.IsSigned() ? kCheckedLoadInt16 : kCheckedLoadUint16;
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      break;
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    case MachineRepresentation::kWord32:
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      opcode = kCheckedLoadWord32;
      break;
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#if V8_TARGET_ARCH_PPC64
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    case MachineRepresentation::kWord64:
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      opcode = kCheckedLoadWord64;
      break;
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#endif
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    case MachineRepresentation::kFloat32:
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      opcode = kCheckedLoadFloat32;
      break;
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    case MachineRepresentation::kFloat64:
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      opcode = kCheckedLoadFloat64;
      break;
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    case MachineRepresentation::kBit:     // Fall through.
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    case MachineRepresentation::kTaggedSigned:   // Fall through.
    case MachineRepresentation::kTaggedPointer:  // Fall through.
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    case MachineRepresentation::kTagged:  // Fall through.
#if !V8_TARGET_ARCH_PPC64
    case MachineRepresentation::kWord64:  // Fall through.
#endif
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    case MachineRepresentation::kSimd128:  // Fall through.
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    case MachineRepresentation::kSimd1x4:  // Fall through.
    case MachineRepresentation::kSimd1x8:  // Fall through.
    case MachineRepresentation::kSimd1x16:  // Fall through.
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    case MachineRepresentation::kNone:
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      UNREACHABLE();
      return;
  }
  AddressingMode addressingMode = kMode_MRR;
  Emit(opcode | AddressingModeField::encode(addressingMode),
       g.DefineAsRegister(node), g.UseRegister(base), g.UseRegister(offset),
       g.UseOperand(length, kInt16Imm_Unsigned));
}


void InstructionSelector::VisitCheckedStore(Node* node) {
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  MachineRepresentation rep = CheckedStoreRepresentationOf(node->op());
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  PPCOperandGenerator g(this);
  Node* const base = node->InputAt(0);
  Node* const offset = node->InputAt(1);
  Node* const length = node->InputAt(2);
  Node* const value = node->InputAt(3);
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  ArchOpcode opcode = kArchNop;
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  switch (rep) {
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    case MachineRepresentation::kWord8:
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      opcode = kCheckedStoreWord8;
      break;
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    case MachineRepresentation::kWord16:
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      opcode = kCheckedStoreWord16;
      break;
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    case MachineRepresentation::kWord32:
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      opcode = kCheckedStoreWord32;
      break;
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#if V8_TARGET_ARCH_PPC64
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    case MachineRepresentation::kWord64:
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      opcode = kCheckedStoreWord64;
      break;
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#endif
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    case MachineRepresentation::kFloat32:
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      opcode = kCheckedStoreFloat32;
      break;
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    case MachineRepresentation::kFloat64:
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      opcode = kCheckedStoreFloat64;
      break;
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    case MachineRepresentation::kBit:     // Fall through.
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    case MachineRepresentation::kTaggedSigned:   // Fall through.
    case MachineRepresentation::kTaggedPointer:  // Fall through.
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    case MachineRepresentation::kTagged:  // Fall through.
#if !V8_TARGET_ARCH_PPC64
    case MachineRepresentation::kWord64:  // Fall through.
#endif
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    case MachineRepresentation::kSimd128:  // Fall through.
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    case MachineRepresentation::kSimd1x4:  // Fall through.
    case MachineRepresentation::kSimd1x8:  // Fall through.
    case MachineRepresentation::kSimd1x16:  // Fall through.
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    case MachineRepresentation::kNone:
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      UNREACHABLE();
      return;
  }
  AddressingMode addressingMode = kMode_MRR;
  Emit(opcode | AddressingModeField::encode(addressingMode), g.NoOutput(),
       g.UseRegister(base), g.UseRegister(offset),
       g.UseOperand(length, kInt16Imm_Unsigned), g.UseRegister(value));
}


template <typename Matcher>
static void VisitLogical(InstructionSelector* selector, Node* node, Matcher* m,
                         ArchOpcode opcode, bool left_can_cover,
                         bool right_can_cover, ImmediateMode imm_mode) {
  PPCOperandGenerator g(selector);

  // Map instruction to equivalent operation with inverted right input.
  ArchOpcode inv_opcode = opcode;
  switch (opcode) {
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    case kPPC_And:
      inv_opcode = kPPC_AndComplement;
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      break;
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    case kPPC_Or:
      inv_opcode = kPPC_OrComplement;
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      break;
    default:
      UNREACHABLE();
  }

  // Select Logical(y, ~x) for Logical(Xor(x, -1), y).
  if ((m->left().IsWord32Xor() || m->left().IsWord64Xor()) && left_can_cover) {
    Matcher mleft(m->left().node());
    if (mleft.right().Is(-1)) {
      selector->Emit(inv_opcode, g.DefineAsRegister(node),
                     g.UseRegister(m->right().node()),
                     g.UseRegister(mleft.left().node()));
      return;
    }
  }

  // Select Logical(x, ~y) for Logical(x, Xor(y, -1)).
  if ((m->right().IsWord32Xor() || m->right().IsWord64Xor()) &&
      right_can_cover) {
    Matcher mright(m->right().node());
    if (mright.right().Is(-1)) {
      // TODO(all): support shifted operand on right.
      selector->Emit(inv_opcode, g.DefineAsRegister(node),
                     g.UseRegister(m->left().node()),
                     g.UseRegister(mright.left().node()));
      return;
    }
  }

  VisitBinop<Matcher>(selector, node, opcode, imm_mode);
}


static inline bool IsContiguousMask32(uint32_t value, int* mb, int* me) {
  int mask_width = base::bits::CountPopulation32(value);
  int mask_msb = base::bits::CountLeadingZeros32(value);
  int mask_lsb = base::bits::CountTrailingZeros32(value);
  if ((mask_width == 0) || (mask_msb + mask_width + mask_lsb != 32))
    return false;
  *mb = mask_lsb + mask_width - 1;
  *me = mask_lsb;
  return true;
}


#if V8_TARGET_ARCH_PPC64
static inline bool IsContiguousMask64(uint64_t value, int* mb, int* me) {
  int mask_width = base::bits::CountPopulation64(value);
  int mask_msb = base::bits::CountLeadingZeros64(value);
  int mask_lsb = base::bits::CountTrailingZeros64(value);
  if ((mask_width == 0) || (mask_msb + mask_width + mask_lsb != 64))
    return false;
  *mb = mask_lsb + mask_width - 1;
  *me = mask_lsb;
  return true;
}
#endif


// TODO(mbrandy): Absorb rotate-right into rlwinm?
void InstructionSelector::VisitWord32And(Node* node) {
  PPCOperandGenerator g(this);
  Int32BinopMatcher m(node);
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  int mb = 0;
  int me = 0;
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  if (m.right().HasValue() && IsContiguousMask32(m.right().Value(), &mb, &me)) {
    int sh = 0;
    Node* left = m.left().node();
    if ((m.left().IsWord32Shr() || m.left().IsWord32Shl()) &&
        CanCover(node, left)) {
      // Try to absorb left/right shift into rlwinm
      Int32BinopMatcher mleft(m.left().node());
      if (mleft.right().IsInRange(0, 31)) {
        left = mleft.left().node();
        sh = mleft.right().Value();
        if (m.left().IsWord32Shr()) {
          // Adjust the mask such that it doesn't include any rotated bits.
          if (mb > 31 - sh) mb = 31 - sh;
          sh = (32 - sh) & 0x1f;
        } else {
          // Adjust the mask such that it doesn't include any rotated bits.
          if (me < sh) me = sh;
        }
      }
    }
    if (mb >= me) {
      Emit(kPPC_RotLeftAndMask32, g.DefineAsRegister(node), g.UseRegister(left),
           g.TempImmediate(sh), g.TempImmediate(mb), g.TempImmediate(me));
      return;
    }
  }
  VisitLogical<Int32BinopMatcher>(
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      this, node, &m, kPPC_And, CanCover(node, m.left().node()),
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      CanCover(node, m.right().node()), kInt16Imm_Unsigned);
}


#if V8_TARGET_ARCH_PPC64
// TODO(mbrandy): Absorb rotate-right into rldic?
void InstructionSelector::VisitWord64And(Node* node) {
  PPCOperandGenerator g(this);
  Int64BinopMatcher m(node);
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  int mb = 0;
  int me = 0;
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  if (m.right().HasValue() && IsContiguousMask64(m.right().Value(), &mb, &me)) {
    int sh = 0;
    Node* left = m.left().node();
    if ((m.left().IsWord64Shr() || m.left().IsWord64Shl()) &&
        CanCover(node, left)) {
      // Try to absorb left/right shift into rldic
      Int64BinopMatcher mleft(m.left().node());
      if (mleft.right().IsInRange(0, 63)) {
        left = mleft.left().node();
        sh = mleft.right().Value();
        if (m.left().IsWord64Shr()) {
          // Adjust the mask such that it doesn't include any rotated bits.
          if (mb > 63 - sh) mb = 63 - sh;
          sh = (64 - sh) & 0x3f;
        } else {
          // Adjust the mask such that it doesn't include any rotated bits.
          if (me < sh) me = sh;
        }
      }
    }
    if (mb >= me) {
      bool match = false;
      ArchOpcode opcode;
      int mask;
      if (me == 0) {
        match = true;
        opcode = kPPC_RotLeftAndClearLeft64;
        mask = mb;
      } else if (mb == 63) {
        match = true;
        opcode = kPPC_RotLeftAndClearRight64;
        mask = me;
      } else if (sh && me <= sh && m.left().IsWord64Shl()) {
        match = true;
        opcode = kPPC_RotLeftAndClear64;
        mask = mb;
      }
      if (match) {
        Emit(opcode, g.DefineAsRegister(node), g.UseRegister(left),
             g.TempImmediate(sh), g.TempImmediate(mask));
        return;
      }
    }
  }
  VisitLogical<Int64BinopMatcher>(
626
      this, node, &m, kPPC_And, CanCover(node, m.left().node()),
627 628 629 630 631 632 633 634
      CanCover(node, m.right().node()), kInt16Imm_Unsigned);
}
#endif


void InstructionSelector::VisitWord32Or(Node* node) {
  Int32BinopMatcher m(node);
  VisitLogical<Int32BinopMatcher>(
635
      this, node, &m, kPPC_Or, CanCover(node, m.left().node()),
636 637 638 639 640 641 642 643
      CanCover(node, m.right().node()), kInt16Imm_Unsigned);
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Or(Node* node) {
  Int64BinopMatcher m(node);
  VisitLogical<Int64BinopMatcher>(
644
      this, node, &m, kPPC_Or, CanCover(node, m.left().node()),
645 646 647 648 649 650 651 652 653
      CanCover(node, m.right().node()), kInt16Imm_Unsigned);
}
#endif


void InstructionSelector::VisitWord32Xor(Node* node) {
  PPCOperandGenerator g(this);
  Int32BinopMatcher m(node);
  if (m.right().Is(-1)) {
654
    Emit(kPPC_Not, g.DefineAsRegister(node), g.UseRegister(m.left().node()));
655
  } else {
656
    VisitBinop<Int32BinopMatcher>(this, node, kPPC_Xor, kInt16Imm_Unsigned);
657 658 659 660 661 662 663 664 665
  }
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Xor(Node* node) {
  PPCOperandGenerator g(this);
  Int64BinopMatcher m(node);
  if (m.right().Is(-1)) {
666
    Emit(kPPC_Not, g.DefineAsRegister(node), g.UseRegister(m.left().node()));
667
  } else {
668
    VisitBinop<Int64BinopMatcher>(this, node, kPPC_Xor, kInt16Imm_Unsigned);
669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694
  }
}
#endif


void InstructionSelector::VisitWord32Shl(Node* node) {
  PPCOperandGenerator g(this);
  Int32BinopMatcher m(node);
  if (m.left().IsWord32And() && m.right().IsInRange(0, 31)) {
    // Try to absorb logical-and into rlwinm
    Int32BinopMatcher mleft(m.left().node());
    int sh = m.right().Value();
    int mb;
    int me;
    if (mleft.right().HasValue() &&
        IsContiguousMask32(mleft.right().Value() << sh, &mb, &me)) {
      // Adjust the mask such that it doesn't include any rotated bits.
      if (me < sh) me = sh;
      if (mb >= me) {
        Emit(kPPC_RotLeftAndMask32, g.DefineAsRegister(node),
             g.UseRegister(mleft.left().node()), g.TempImmediate(sh),
             g.TempImmediate(mb), g.TempImmediate(me));
        return;
      }
    }
  }
695
  VisitRRO(this, kPPC_ShiftLeft32, node, kShift32Imm);
696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Shl(Node* node) {
  PPCOperandGenerator g(this);
  Int64BinopMatcher m(node);
  // TODO(mbrandy): eliminate left sign extension if right >= 32
  if (m.left().IsWord64And() && m.right().IsInRange(0, 63)) {
    // Try to absorb logical-and into rldic
    Int64BinopMatcher mleft(m.left().node());
    int sh = m.right().Value();
    int mb;
    int me;
    if (mleft.right().HasValue() &&
        IsContiguousMask64(mleft.right().Value() << sh, &mb, &me)) {
      // Adjust the mask such that it doesn't include any rotated bits.
      if (me < sh) me = sh;
      if (mb >= me) {
        bool match = false;
        ArchOpcode opcode;
        int mask;
        if (me == 0) {
          match = true;
          opcode = kPPC_RotLeftAndClearLeft64;
          mask = mb;
        } else if (mb == 63) {
          match = true;
          opcode = kPPC_RotLeftAndClearRight64;
          mask = me;
        } else if (sh && me <= sh) {
          match = true;
          opcode = kPPC_RotLeftAndClear64;
          mask = mb;
        }
        if (match) {
          Emit(opcode, g.DefineAsRegister(node),
               g.UseRegister(mleft.left().node()), g.TempImmediate(sh),
               g.TempImmediate(mask));
          return;
        }
      }
    }
  }
740
  VisitRRO(this, kPPC_ShiftLeft64, node, kShift64Imm);
741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766
}
#endif


void InstructionSelector::VisitWord32Shr(Node* node) {
  PPCOperandGenerator g(this);
  Int32BinopMatcher m(node);
  if (m.left().IsWord32And() && m.right().IsInRange(0, 31)) {
    // Try to absorb logical-and into rlwinm
    Int32BinopMatcher mleft(m.left().node());
    int sh = m.right().Value();
    int mb;
    int me;
    if (mleft.right().HasValue() &&
        IsContiguousMask32((uint32_t)(mleft.right().Value()) >> sh, &mb, &me)) {
      // Adjust the mask such that it doesn't include any rotated bits.
      if (mb > 31 - sh) mb = 31 - sh;
      sh = (32 - sh) & 0x1f;
      if (mb >= me) {
        Emit(kPPC_RotLeftAndMask32, g.DefineAsRegister(node),
             g.UseRegister(mleft.left().node()), g.TempImmediate(sh),
             g.TempImmediate(mb), g.TempImmediate(me));
        return;
      }
    }
  }
767
  VisitRRO(this, kPPC_ShiftRight32, node, kShift32Imm);
768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806
}

#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Shr(Node* node) {
  PPCOperandGenerator g(this);
  Int64BinopMatcher m(node);
  if (m.left().IsWord64And() && m.right().IsInRange(0, 63)) {
    // Try to absorb logical-and into rldic
    Int64BinopMatcher mleft(m.left().node());
    int sh = m.right().Value();
    int mb;
    int me;
    if (mleft.right().HasValue() &&
        IsContiguousMask64((uint64_t)(mleft.right().Value()) >> sh, &mb, &me)) {
      // Adjust the mask such that it doesn't include any rotated bits.
      if (mb > 63 - sh) mb = 63 - sh;
      sh = (64 - sh) & 0x3f;
      if (mb >= me) {
        bool match = false;
        ArchOpcode opcode;
        int mask;
        if (me == 0) {
          match = true;
          opcode = kPPC_RotLeftAndClearLeft64;
          mask = mb;
        } else if (mb == 63) {
          match = true;
          opcode = kPPC_RotLeftAndClearRight64;
          mask = me;
        }
        if (match) {
          Emit(opcode, g.DefineAsRegister(node),
               g.UseRegister(mleft.left().node()), g.TempImmediate(sh),
               g.TempImmediate(mask));
          return;
        }
      }
    }
  }
807
  VisitRRO(this, kPPC_ShiftRight64, node, kShift64Imm);
808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827
}
#endif


void InstructionSelector::VisitWord32Sar(Node* node) {
  PPCOperandGenerator g(this);
  Int32BinopMatcher m(node);
  // Replace with sign extension for (x << K) >> K where K is 16 or 24.
  if (CanCover(node, m.left().node()) && m.left().IsWord32Shl()) {
    Int32BinopMatcher mleft(m.left().node());
    if (mleft.right().Is(16) && m.right().Is(16)) {
      Emit(kPPC_ExtendSignWord16, g.DefineAsRegister(node),
           g.UseRegister(mleft.left().node()));
      return;
    } else if (mleft.right().Is(24) && m.right().Is(24)) {
      Emit(kPPC_ExtendSignWord8, g.DefineAsRegister(node),
           g.UseRegister(mleft.left().node()));
      return;
    }
  }
828
  VisitRRO(this, kPPC_ShiftRightAlg32, node, kShift32Imm);
829 830
}

831
#if !V8_TARGET_ARCH_PPC64
832
void VisitPairBinop(InstructionSelector* selector, InstructionCode opcode,
833
                    InstructionCode opcode2, Node* node) {
834
  PPCOperandGenerator g(selector);
835

836 837 838 839 840 841 842
  Node* projection1 = NodeProperties::FindProjection(node, 1);
  if (projection1) {
    // We use UseUniqueRegister here to avoid register sharing with the output
    // registers.
    InstructionOperand inputs[] = {
        g.UseRegister(node->InputAt(0)), g.UseUniqueRegister(node->InputAt(1)),
        g.UseRegister(node->InputAt(2)), g.UseUniqueRegister(node->InputAt(3))};
843

844 845 846
    InstructionOperand outputs[] = {
        g.DefineAsRegister(node),
        g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
847

848 849 850 851 852 853 854 855
    selector->Emit(opcode, 2, outputs, 4, inputs);
  } else {
    // The high word of the result is not used, so we emit the standard 32 bit
    // instruction.
    selector->Emit(opcode2, g.DefineSameAsFirst(node),
                   g.UseRegister(node->InputAt(0)),
                   g.UseRegister(node->InputAt(2)));
  }
856 857
}

858
void InstructionSelector::VisitInt32PairAdd(Node* node) {
859
  VisitPairBinop(this, kPPC_AddPair, kPPC_Add32, node);
860 861 862
}

void InstructionSelector::VisitInt32PairSub(Node* node) {
863
  VisitPairBinop(this, kPPC_SubPair, kPPC_Sub, node);
864
}
865

866 867
void InstructionSelector::VisitInt32PairMul(Node* node) {
  PPCOperandGenerator g(this);
868 869 870 871 872 873
  Node* projection1 = NodeProperties::FindProjection(node, 1);
  if (projection1) {
    InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)),
                                   g.UseUniqueRegister(node->InputAt(1)),
                                   g.UseUniqueRegister(node->InputAt(2)),
                                   g.UseUniqueRegister(node->InputAt(3))};
874

875 876 877
    InstructionOperand outputs[] = {
        g.DefineAsRegister(node),
        g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
878

879
    InstructionOperand temps[] = {g.TempRegister(), g.TempRegister()};
880

881 882 883 884 885 886 887
    Emit(kPPC_MulPair, 2, outputs, 4, inputs, 2, temps);
  } else {
    // The high word of the result is not used, so we emit the standard 32 bit
    // instruction.
    Emit(kPPC_Mul32, g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)),
         g.UseRegister(node->InputAt(2)));
  }
888
}
889

890 891
namespace {
// Shared routine for multiple shift operations.
892
void VisitPairShift(InstructionSelector* selector, InstructionCode opcode,
893 894
                    Node* node) {
  PPCOperandGenerator g(selector);
895 896
  // We use g.UseUniqueRegister here to guarantee that there is
  // no register aliasing of input registers with output registers.
897 898 899 900 901 902 903 904
  Int32Matcher m(node->InputAt(2));
  InstructionOperand shift_operand;
  if (m.HasValue()) {
    shift_operand = g.UseImmediate(m.node());
  } else {
    shift_operand = g.UseUniqueRegister(m.node());
  }

905 906
  InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)),
                                 g.UseUniqueRegister(node->InputAt(1)),
907 908
                                 shift_operand};

909
  Node* projection1 = NodeProperties::FindProjection(node, 1);
910

911 912 913 914 915 916 917 918 919 920 921 922 923
  InstructionOperand outputs[2];
  InstructionOperand temps[1];
  int32_t output_count = 0;
  int32_t temp_count = 0;

  outputs[output_count++] = g.DefineAsRegister(node);
  if (projection1) {
    outputs[output_count++] = g.DefineAsRegister(projection1);
  } else {
    temps[temp_count++] = g.TempRegister();
  }

  selector->Emit(opcode, output_count, outputs, 3, inputs, temp_count, temps);
924
}
925
}  // namespace
926 927 928 929 930 931 932 933 934 935 936

void InstructionSelector::VisitWord32PairShl(Node* node) {
  VisitPairShift(this, kPPC_ShiftLeftPair, node);
}

void InstructionSelector::VisitWord32PairShr(Node* node) {
  VisitPairShift(this, kPPC_ShiftRightPair, node);
}

void InstructionSelector::VisitWord32PairSar(Node* node) {
  VisitPairShift(this, kPPC_ShiftRightAlgPair, node);
937 938
}
#endif
939 940 941

#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Sar(Node* node) {
942 943 944 945 946 947
  PPCOperandGenerator g(this);
  Int64BinopMatcher m(node);
  if (CanCover(m.node(), m.left().node()) && m.left().IsLoad() &&
      m.right().Is(32)) {
    // Just load and sign-extend the interesting 4 bytes instead. This happens,
    // for example, when we're loading and untagging SMIs.
948 949
    BaseWithIndexAndDisplacement64Matcher mleft(m.left().node(),
                                                AddressOption::kAllowAll);
950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966
    if (mleft.matches() && mleft.index() == nullptr) {
      int64_t offset = 0;
      Node* displacement = mleft.displacement();
      if (displacement != nullptr) {
        Int64Matcher mdisplacement(displacement);
        DCHECK(mdisplacement.HasValue());
        offset = mdisplacement.Value();
      }
      offset = SmiWordOffset(offset);
      if (g.CanBeImmediate(offset, kInt16Imm_4ByteAligned)) {
        Emit(kPPC_LoadWordS32 | AddressingModeField::encode(kMode_MRI),
             g.DefineAsRegister(node), g.UseRegister(mleft.base()),
             g.TempImmediate(offset));
        return;
      }
    }
  }
967
  VisitRRO(this, kPPC_ShiftRightAlg64, node, kShift64Imm);
968 969 970 971 972 973
}
#endif


// TODO(mbrandy): Absorb logical-and into rlwinm?
void InstructionSelector::VisitWord32Ror(Node* node) {
974
  VisitRRO(this, kPPC_RotRight32, node, kShift32Imm);
975 976 977 978 979 980
}


#if V8_TARGET_ARCH_PPC64
// TODO(mbrandy): Absorb logical-and into rldic?
void InstructionSelector::VisitWord64Ror(Node* node) {
981
  VisitRRO(this, kPPC_RotRight64, node, kShift64Imm);
982 983 984 985
}
#endif


986 987 988 989 990 991
void InstructionSelector::VisitWord32Clz(Node* node) {
  PPCOperandGenerator g(this);
  Emit(kPPC_Cntlz32, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)));
}


992 993 994 995 996 997 998 999
#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Clz(Node* node) {
  PPCOperandGenerator g(this);
  Emit(kPPC_Cntlz64, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)));
}
#endif


1000 1001 1002 1003 1004
void InstructionSelector::VisitWord32Popcnt(Node* node) {
  PPCOperandGenerator g(this);
  Emit(kPPC_Popcnt32, g.DefineAsRegister(node),
       g.UseRegister(node->InputAt(0)));
}
1005 1006


1007 1008 1009 1010 1011 1012 1013 1014 1015
#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Popcnt(Node* node) {
  PPCOperandGenerator g(this);
  Emit(kPPC_Popcnt64, g.DefineAsRegister(node),
       g.UseRegister(node->InputAt(0)));
}
#endif


1016
void InstructionSelector::VisitWord32Ctz(Node* node) { UNREACHABLE(); }
1017 1018


1019 1020 1021 1022 1023
#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Ctz(Node* node) { UNREACHABLE(); }
#endif


1024 1025 1026 1027 1028 1029 1030
void InstructionSelector::VisitWord32ReverseBits(Node* node) { UNREACHABLE(); }


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64ReverseBits(Node* node) { UNREACHABLE(); }
#endif

1031 1032 1033
void InstructionSelector::VisitWord64ReverseBytes(Node* node) { UNREACHABLE(); }

void InstructionSelector::VisitWord32ReverseBytes(Node* node) { UNREACHABLE(); }
1034

1035
void InstructionSelector::VisitInt32Add(Node* node) {
1036
  VisitBinop<Int32BinopMatcher>(this, node, kPPC_Add32, kInt16Imm);
1037 1038 1039 1040 1041
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitInt64Add(Node* node) {
1042
  VisitBinop<Int64BinopMatcher>(this, node, kPPC_Add64, kInt16Imm);
1043 1044 1045 1046 1047 1048 1049
}
#endif

void InstructionSelector::VisitInt32Sub(Node* node) {
  PPCOperandGenerator g(this);
  Int32BinopMatcher m(node);
  if (m.left().Is(0)) {
1050
    Emit(kPPC_Neg, g.DefineAsRegister(node), g.UseRegister(m.right().node()));
1051
  } else {
1052
    VisitBinop<Int32BinopMatcher>(this, node, kPPC_Sub, kInt16Imm_Negate);
1053 1054 1055 1056 1057 1058 1059 1060 1061
  }
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitInt64Sub(Node* node) {
  PPCOperandGenerator g(this);
  Int64BinopMatcher m(node);
  if (m.left().Is(0)) {
1062
    Emit(kPPC_Neg, g.DefineAsRegister(node), g.UseRegister(m.right().node()));
1063
  } else {
1064
    VisitBinop<Int64BinopMatcher>(this, node, kPPC_Sub, kInt16Imm_Negate);
1065 1066 1067 1068
  }
}
#endif

1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098
namespace {

void VisitCompare(InstructionSelector* selector, InstructionCode opcode,
                  InstructionOperand left, InstructionOperand right,
                  FlagsContinuation* cont);
void EmitInt32MulWithOverflow(InstructionSelector* selector, Node* node,
                              FlagsContinuation* cont) {
  PPCOperandGenerator g(selector);
  Int32BinopMatcher m(node);
  InstructionOperand result_operand = g.DefineAsRegister(node);
  InstructionOperand high32_operand = g.TempRegister();
  InstructionOperand temp_operand = g.TempRegister();
  {
    InstructionOperand outputs[] = {result_operand, high32_operand};
    InstructionOperand inputs[] = {g.UseRegister(m.left().node()),
                                   g.UseRegister(m.right().node())};
    selector->Emit(kPPC_Mul32WithHigh32, 2, outputs, 2, inputs);
  }
  {
    InstructionOperand shift_31 = g.UseImmediate(31);
    InstructionOperand outputs[] = {temp_operand};
    InstructionOperand inputs[] = {result_operand, shift_31};
    selector->Emit(kPPC_ShiftRightAlg32, 1, outputs, 2, inputs);
  }

  VisitCompare(selector, kPPC_Cmp32, high32_operand, temp_operand, cont);
}

}  // namespace

1099 1100

void InstructionSelector::VisitInt32Mul(Node* node) {
1101
  VisitRRR(this, kPPC_Mul32, node);
1102 1103 1104 1105 1106
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitInt64Mul(Node* node) {
1107
  VisitRRR(this, kPPC_Mul64, node);
1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126
}
#endif


void InstructionSelector::VisitInt32MulHigh(Node* node) {
  PPCOperandGenerator g(this);
  Emit(kPPC_MulHigh32, g.DefineAsRegister(node),
       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}


void InstructionSelector::VisitUint32MulHigh(Node* node) {
  PPCOperandGenerator g(this);
  Emit(kPPC_MulHighU32, g.DefineAsRegister(node),
       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}


void InstructionSelector::VisitInt32Div(Node* node) {
1127
  VisitRRR(this, kPPC_Div32, node);
1128 1129 1130 1131 1132
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitInt64Div(Node* node) {
1133
  VisitRRR(this, kPPC_Div64, node);
1134 1135 1136 1137 1138
}
#endif


void InstructionSelector::VisitUint32Div(Node* node) {
1139
  VisitRRR(this, kPPC_DivU32, node);
1140 1141 1142 1143 1144
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitUint64Div(Node* node) {
1145
  VisitRRR(this, kPPC_DivU64, node);
1146 1147 1148 1149 1150
}
#endif


void InstructionSelector::VisitInt32Mod(Node* node) {
1151
  VisitRRR(this, kPPC_Mod32, node);
1152 1153 1154 1155 1156
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitInt64Mod(Node* node) {
1157
  VisitRRR(this, kPPC_Mod64, node);
1158 1159 1160 1161 1162
}
#endif


void InstructionSelector::VisitUint32Mod(Node* node) {
1163
  VisitRRR(this, kPPC_ModU32, node);
1164 1165 1166 1167 1168
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitUint64Mod(Node* node) {
1169
  VisitRRR(this, kPPC_ModU64, node);
1170 1171 1172 1173 1174
}
#endif


void InstructionSelector::VisitChangeFloat32ToFloat64(Node* node) {
1175
  VisitRR(this, kPPC_Float32ToDouble, node);
1176 1177 1178
}


1179 1180 1181 1182 1183
void InstructionSelector::VisitRoundInt32ToFloat32(Node* node) {
  VisitRR(this, kPPC_Int32ToFloat32, node);
}


1184
void InstructionSelector::VisitRoundUint32ToFloat32(Node* node) {
1185
  VisitRR(this, kPPC_Uint32ToFloat32, node);
1186 1187 1188
}


1189
void InstructionSelector::VisitChangeInt32ToFloat64(Node* node) {
1190
  VisitRR(this, kPPC_Int32ToDouble, node);
1191 1192 1193 1194
}


void InstructionSelector::VisitChangeUint32ToFloat64(Node* node) {
1195
  VisitRR(this, kPPC_Uint32ToDouble, node);
1196 1197 1198 1199
}


void InstructionSelector::VisitChangeFloat64ToInt32(Node* node) {
1200
  VisitRR(this, kPPC_DoubleToInt32, node);
1201 1202 1203 1204
}


void InstructionSelector::VisitChangeFloat64ToUint32(Node* node) {
1205
  VisitRR(this, kPPC_DoubleToUint32, node);
1206 1207
}

1208 1209 1210
void InstructionSelector::VisitTruncateFloat64ToUint32(Node* node) {
  VisitRR(this, kPPC_DoubleToUint32, node);
}
1211 1212

#if V8_TARGET_ARCH_PPC64
1213
void InstructionSelector::VisitTryTruncateFloat32ToInt64(Node* node) {
1214
  VisitTryTruncateDouble(this, kPPC_DoubleToInt64, node);
1215 1216 1217
}


1218
void InstructionSelector::VisitTryTruncateFloat64ToInt64(Node* node) {
1219
  VisitTryTruncateDouble(this, kPPC_DoubleToInt64, node);
1220 1221 1222
}


1223
void InstructionSelector::VisitTryTruncateFloat32ToUint64(Node* node) {
1224
  VisitTryTruncateDouble(this, kPPC_DoubleToUint64, node);
1225 1226 1227
}


1228
void InstructionSelector::VisitTryTruncateFloat64ToUint64(Node* node) {
1229
  VisitTryTruncateDouble(this, kPPC_DoubleToUint64, node);
1230 1231 1232
}


1233 1234
void InstructionSelector::VisitChangeInt32ToInt64(Node* node) {
  // TODO(mbrandy): inspect input to see if nop is appropriate.
1235
  VisitRR(this, kPPC_ExtendSignWord32, node);
1236 1237 1238 1239 1240
}


void InstructionSelector::VisitChangeUint32ToUint64(Node* node) {
  // TODO(mbrandy): inspect input to see if nop is appropriate.
1241
  VisitRR(this, kPPC_Uint32ToUint64, node);
1242
}
1243 1244 1245 1246

void InstructionSelector::VisitChangeFloat64ToUint64(Node* node) {
  VisitRR(this, kPPC_DoubleToUint64, node);
}
1247 1248 1249 1250
#endif


void InstructionSelector::VisitTruncateFloat64ToFloat32(Node* node) {
1251 1252 1253
  VisitRR(this, kPPC_DoubleToFloat32, node);
}

1254
void InstructionSelector::VisitTruncateFloat64ToWord32(Node* node) {
1255 1256 1257 1258 1259
  VisitRR(this, kArchTruncateDoubleToI, node);
}

void InstructionSelector::VisitRoundFloat64ToInt32(Node* node) {
  VisitRR(this, kPPC_DoubleToInt32, node);
1260 1261 1262
}


1263
void InstructionSelector::VisitTruncateFloat32ToInt32(Node* node) {
1264
  VisitRR(this, kPPC_DoubleToInt32, node);
1265 1266 1267
}


1268
void InstructionSelector::VisitTruncateFloat32ToUint32(Node* node) {
1269
  VisitRR(this, kPPC_DoubleToUint32, node);
1270 1271 1272
}


1273 1274 1275
#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitTruncateInt64ToInt32(Node* node) {
  // TODO(mbrandy): inspect input to see if nop is appropriate.
1276
  VisitRR(this, kPPC_Int64ToInt32, node);
1277
}
1278 1279


1280 1281 1282 1283 1284
void InstructionSelector::VisitRoundInt64ToFloat32(Node* node) {
  VisitRR(this, kPPC_Int64ToFloat32, node);
}


1285 1286 1287
void InstructionSelector::VisitRoundInt64ToFloat64(Node* node) {
  VisitRR(this, kPPC_Int64ToDouble, node);
}
1288 1289


1290 1291 1292 1293 1294
void InstructionSelector::VisitRoundUint64ToFloat32(Node* node) {
  VisitRR(this, kPPC_Uint64ToFloat32, node);
}


1295
void InstructionSelector::VisitRoundUint64ToFloat64(Node* node) {
1296
  VisitRR(this, kPPC_Uint64ToDouble, node);
1297
}
1298 1299 1300
#endif


1301
void InstructionSelector::VisitBitcastFloat32ToInt32(Node* node) {
1302
  VisitRR(this, kPPC_BitcastFloat32ToInt32, node);
1303 1304 1305 1306 1307
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitBitcastFloat64ToInt64(Node* node) {
1308
  VisitRR(this, kPPC_BitcastDoubleToInt64, node);
1309 1310 1311 1312 1313
}
#endif


void InstructionSelector::VisitBitcastInt32ToFloat32(Node* node) {
1314
  VisitRR(this, kPPC_BitcastInt32ToFloat32, node);
1315 1316 1317 1318 1319
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitBitcastInt64ToFloat64(Node* node) {
1320
  VisitRR(this, kPPC_BitcastInt64ToDouble, node);
1321 1322 1323 1324
}
#endif


1325
void InstructionSelector::VisitFloat32Add(Node* node) {
1326
  VisitRRR(this, kPPC_AddDouble | MiscField::encode(1), node);
1327 1328 1329
}


1330 1331
void InstructionSelector::VisitFloat64Add(Node* node) {
  // TODO(mbrandy): detect multiply-add
1332 1333 1334 1335 1336
  VisitRRR(this, kPPC_AddDouble, node);
}


void InstructionSelector::VisitFloat32Sub(Node* node) {
1337 1338
  VisitRRR(this, kPPC_SubDouble | MiscField::encode(1), node);
}
1339 1340 1341

void InstructionSelector::VisitFloat64Sub(Node* node) {
  // TODO(mbrandy): detect multiply-subtract
1342 1343
  VisitRRR(this, kPPC_SubDouble, node);
}
1344 1345

void InstructionSelector::VisitFloat32Mul(Node* node) {
1346
  VisitRRR(this, kPPC_MulDouble | MiscField::encode(1), node);
1347 1348 1349 1350 1351
}


void InstructionSelector::VisitFloat64Mul(Node* node) {
  // TODO(mbrandy): detect negate
1352 1353 1354 1355 1356
  VisitRRR(this, kPPC_MulDouble, node);
}


void InstructionSelector::VisitFloat32Div(Node* node) {
1357
  VisitRRR(this, kPPC_DivDouble | MiscField::encode(1), node);
1358 1359 1360 1361
}


void InstructionSelector::VisitFloat64Div(Node* node) {
1362
  VisitRRR(this, kPPC_DivDouble, node);
1363 1364 1365 1366 1367
}


void InstructionSelector::VisitFloat64Mod(Node* node) {
  PPCOperandGenerator g(this);
1368
  Emit(kPPC_ModDouble, g.DefineAsFixed(node, d1),
1369 1370 1371 1372
       g.UseFixed(node->InputAt(0), d1),
       g.UseFixed(node->InputAt(1), d2))->MarkAsCall();
}

1373 1374 1375
void InstructionSelector::VisitFloat32Max(Node* node) {
  VisitRRR(this, kPPC_MaxDouble | MiscField::encode(1), node);
}
1376

1377 1378 1379
void InstructionSelector::VisitFloat64Max(Node* node) {
  VisitRRR(this, kPPC_MaxDouble, node);
}
1380 1381


1382 1383 1384 1385
void InstructionSelector::VisitFloat64SilenceNaN(Node* node) {
  VisitRR(this, kPPC_Float64SilenceNaN, node);
}

1386 1387 1388
void InstructionSelector::VisitFloat32Min(Node* node) {
  VisitRRR(this, kPPC_MinDouble | MiscField::encode(1), node);
}
1389

1390 1391 1392
void InstructionSelector::VisitFloat64Min(Node* node) {
  VisitRRR(this, kPPC_MinDouble, node);
}
1393 1394


1395
void InstructionSelector::VisitFloat32Abs(Node* node) {
1396
  VisitRR(this, kPPC_AbsDouble | MiscField::encode(1), node);
1397
}
1398 1399


1400 1401 1402
void InstructionSelector::VisitFloat64Abs(Node* node) {
  VisitRR(this, kPPC_AbsDouble, node);
}
1403

1404
void InstructionSelector::VisitFloat32Sqrt(Node* node) {
1405
  VisitRR(this, kPPC_SqrtDouble | MiscField::encode(1), node);
1406
}
1407

1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421
void InstructionSelector::VisitFloat64Ieee754Unop(Node* node,
                                                  InstructionCode opcode) {
  PPCOperandGenerator g(this);
  Emit(opcode, g.DefineAsFixed(node, d1), g.UseFixed(node->InputAt(0), d1))
       ->MarkAsCall();
}

void InstructionSelector::VisitFloat64Ieee754Binop(Node* node,
                                                  InstructionCode opcode) {
  PPCOperandGenerator g(this);
  Emit(opcode, g.DefineAsFixed(node, d1),
       g.UseFixed(node->InputAt(0), d1),
       g.UseFixed(node->InputAt(1), d2))->MarkAsCall();
}
1422

1423
void InstructionSelector::VisitFloat64Sqrt(Node* node) {
1424
  VisitRR(this, kPPC_SqrtDouble, node);
1425 1426 1427
}


1428
void InstructionSelector::VisitFloat32RoundDown(Node* node) {
1429
  VisitRR(this, kPPC_FloorDouble | MiscField::encode(1), node);
1430
}
1431 1432


1433
void InstructionSelector::VisitFloat64RoundDown(Node* node) {
1434
  VisitRR(this, kPPC_FloorDouble, node);
1435 1436 1437
}


1438
void InstructionSelector::VisitFloat32RoundUp(Node* node) {
1439
  VisitRR(this, kPPC_CeilDouble | MiscField::encode(1), node);
1440
}
1441 1442


1443 1444 1445 1446 1447
void InstructionSelector::VisitFloat64RoundUp(Node* node) {
  VisitRR(this, kPPC_CeilDouble, node);
}


1448
void InstructionSelector::VisitFloat32RoundTruncate(Node* node) {
1449
  VisitRR(this, kPPC_TruncateDouble | MiscField::encode(1), node);
1450 1451 1452
}


1453
void InstructionSelector::VisitFloat64RoundTruncate(Node* node) {
1454
  VisitRR(this, kPPC_TruncateDouble, node);
1455 1456 1457 1458
}


void InstructionSelector::VisitFloat64RoundTiesAway(Node* node) {
1459
  VisitRR(this, kPPC_RoundDouble, node);
1460 1461 1462
}


1463 1464 1465 1466 1467
void InstructionSelector::VisitFloat32RoundTiesEven(Node* node) {
  UNREACHABLE();
}


1468 1469 1470 1471
void InstructionSelector::VisitFloat64RoundTiesEven(Node* node) {
  UNREACHABLE();
}

1472 1473 1474
void InstructionSelector::VisitFloat32Neg(Node* node) {
  VisitRR(this, kPPC_NegDouble, node);
}
1475

1476 1477 1478
void InstructionSelector::VisitFloat64Neg(Node* node) {
  VisitRR(this, kPPC_NegDouble, node);
}
1479

1480 1481
void InstructionSelector::VisitInt32AddWithOverflow(Node* node) {
  if (Node* ovf = NodeProperties::FindProjection(node, 1)) {
1482
    FlagsContinuation cont = FlagsContinuation::ForSet(kOverflow, ovf);
1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493
    return VisitBinop<Int32BinopMatcher>(this, node, kPPC_AddWithOverflow32,
                                         kInt16Imm, &cont);
  }
  FlagsContinuation cont;
  VisitBinop<Int32BinopMatcher>(this, node, kPPC_AddWithOverflow32, kInt16Imm,
                                &cont);
}


void InstructionSelector::VisitInt32SubWithOverflow(Node* node) {
  if (Node* ovf = NodeProperties::FindProjection(node, 1)) {
1494
    FlagsContinuation cont = FlagsContinuation::ForSet(kOverflow, ovf);
1495 1496 1497 1498 1499 1500 1501 1502 1503
    return VisitBinop<Int32BinopMatcher>(this, node, kPPC_SubWithOverflow32,
                                         kInt16Imm_Negate, &cont);
  }
  FlagsContinuation cont;
  VisitBinop<Int32BinopMatcher>(this, node, kPPC_SubWithOverflow32,
                                kInt16Imm_Negate, &cont);
}


1504 1505 1506
#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitInt64AddWithOverflow(Node* node) {
  if (Node* ovf = NodeProperties::FindProjection(node, 1)) {
1507
    FlagsContinuation cont = FlagsContinuation::ForSet(kOverflow, ovf);
1508
    return VisitBinop<Int64BinopMatcher>(this, node, kPPC_Add64, kInt16Imm,
1509 1510 1511
                                         &cont);
  }
  FlagsContinuation cont;
1512
  VisitBinop<Int64BinopMatcher>(this, node, kPPC_Add64, kInt16Imm, &cont);
1513 1514 1515 1516 1517
}


void InstructionSelector::VisitInt64SubWithOverflow(Node* node) {
  if (Node* ovf = NodeProperties::FindProjection(node, 1)) {
1518
    FlagsContinuation cont = FlagsContinuation::ForSet(kOverflow, ovf);
1519 1520 1521 1522 1523 1524 1525 1526 1527
    return VisitBinop<Int64BinopMatcher>(this, node, kPPC_Sub, kInt16Imm_Negate,
                                         &cont);
  }
  FlagsContinuation cont;
  VisitBinop<Int64BinopMatcher>(this, node, kPPC_Sub, kInt16Imm_Negate, &cont);
}
#endif


1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542
static bool CompareLogical(FlagsContinuation* cont) {
  switch (cont->condition()) {
    case kUnsignedLessThan:
    case kUnsignedGreaterThanOrEqual:
    case kUnsignedLessThanOrEqual:
    case kUnsignedGreaterThan:
      return true;
    default:
      return false;
  }
  UNREACHABLE();
  return false;
}


1543 1544
namespace {

1545
// Shared routine for multiple compare operations.
1546 1547 1548
void VisitCompare(InstructionSelector* selector, InstructionCode opcode,
                  InstructionOperand left, InstructionOperand right,
                  FlagsContinuation* cont) {
1549 1550 1551 1552
  PPCOperandGenerator g(selector);
  opcode = cont->Encode(opcode);
  if (cont->IsBranch()) {
    selector->Emit(opcode, g.NoOutput(), left, right,
1553
                   g.Label(cont->true_block()), g.Label(cont->false_block()));
1554
  } else if (cont->IsDeoptimize()) {
1555 1556
    selector->EmitDeoptimize(opcode, g.NoOutput(), left, right, cont->kind(),
                             cont->reason(), cont->frame_state());
1557
  } else if (cont->IsSet()) {
1558
    selector->Emit(opcode, g.DefineAsRegister(cont->result()), left, right);
1559 1560 1561 1562
  } else {
    DCHECK(cont->IsTrap());
    selector->Emit(opcode, g.NoOutput(), left, right,
                   g.UseImmediate(cont->trap_id()));
1563 1564 1565 1566 1567
  }
}


// Shared routine for multiple word compare operations.
1568 1569 1570
void VisitWordCompare(InstructionSelector* selector, Node* node,
                      InstructionCode opcode, FlagsContinuation* cont,
                      bool commutative, ImmediateMode immediate_mode) {
1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589
  PPCOperandGenerator g(selector);
  Node* left = node->InputAt(0);
  Node* right = node->InputAt(1);

  // Match immediates on left or right side of comparison.
  if (g.CanBeImmediate(right, immediate_mode)) {
    VisitCompare(selector, opcode, g.UseRegister(left), g.UseImmediate(right),
                 cont);
  } else if (g.CanBeImmediate(left, immediate_mode)) {
    if (!commutative) cont->Commute();
    VisitCompare(selector, opcode, g.UseRegister(right), g.UseImmediate(left),
                 cont);
  } else {
    VisitCompare(selector, opcode, g.UseRegister(left), g.UseRegister(right),
                 cont);
  }
}


1590 1591
void VisitWord32Compare(InstructionSelector* selector, Node* node,
                        FlagsContinuation* cont) {
1592 1593 1594 1595 1596 1597
  ImmediateMode mode = (CompareLogical(cont) ? kInt16Imm_Unsigned : kInt16Imm);
  VisitWordCompare(selector, node, kPPC_Cmp32, cont, false, mode);
}


#if V8_TARGET_ARCH_PPC64
1598 1599
void VisitWord64Compare(InstructionSelector* selector, Node* node,
                        FlagsContinuation* cont) {
1600 1601 1602 1603 1604 1605
  ImmediateMode mode = (CompareLogical(cont) ? kInt16Imm_Unsigned : kInt16Imm);
  VisitWordCompare(selector, node, kPPC_Cmp64, cont, false, mode);
}
#endif


1606 1607 1608
// Shared routine for multiple float32 compare operations.
void VisitFloat32Compare(InstructionSelector* selector, Node* node,
                         FlagsContinuation* cont) {
1609 1610 1611
  PPCOperandGenerator g(selector);
  Node* left = node->InputAt(0);
  Node* right = node->InputAt(1);
1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623
  VisitCompare(selector, kPPC_CmpDouble, g.UseRegister(left),
               g.UseRegister(right), cont);
}


// Shared routine for multiple float64 compare operations.
void VisitFloat64Compare(InstructionSelector* selector, Node* node,
                         FlagsContinuation* cont) {
  PPCOperandGenerator g(selector);
  Node* left = node->InputAt(0);
  Node* right = node->InputAt(1);
  VisitCompare(selector, kPPC_CmpDouble, g.UseRegister(left),
1624 1625 1626 1627 1628
               g.UseRegister(right), cont);
}


// Shared routine for word comparisons against zero.
1629 1630 1631
void VisitWordCompareZero(InstructionSelector* selector, Node* user,
                          Node* value, InstructionCode opcode,
                          FlagsContinuation* cont) {
1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643
  // Try to combine with comparisons against 0 by simply inverting the branch.
  while (value->opcode() == IrOpcode::kWord32Equal &&
         selector->CanCover(user, value)) {
    Int32BinopMatcher m(value);
    if (!m.right().Is(0)) break;

    user = value;
    value = m.left().node();
    cont->Negate();
  }

  if (selector->CanCover(user, value)) {
1644
    switch (value->opcode()) {
1645
      case IrOpcode::kWord32Equal:
1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660
        cont->OverwriteAndNegateIfEqual(kEqual);
        return VisitWord32Compare(selector, value, cont);
      case IrOpcode::kInt32LessThan:
        cont->OverwriteAndNegateIfEqual(kSignedLessThan);
        return VisitWord32Compare(selector, value, cont);
      case IrOpcode::kInt32LessThanOrEqual:
        cont->OverwriteAndNegateIfEqual(kSignedLessThanOrEqual);
        return VisitWord32Compare(selector, value, cont);
      case IrOpcode::kUint32LessThan:
        cont->OverwriteAndNegateIfEqual(kUnsignedLessThan);
        return VisitWord32Compare(selector, value, cont);
      case IrOpcode::kUint32LessThanOrEqual:
        cont->OverwriteAndNegateIfEqual(kUnsignedLessThanOrEqual);
        return VisitWord32Compare(selector, value, cont);
#if V8_TARGET_ARCH_PPC64
1661
      case IrOpcode::kWord64Equal:
1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672
        cont->OverwriteAndNegateIfEqual(kEqual);
        return VisitWord64Compare(selector, value, cont);
      case IrOpcode::kInt64LessThan:
        cont->OverwriteAndNegateIfEqual(kSignedLessThan);
        return VisitWord64Compare(selector, value, cont);
      case IrOpcode::kInt64LessThanOrEqual:
        cont->OverwriteAndNegateIfEqual(kSignedLessThanOrEqual);
        return VisitWord64Compare(selector, value, cont);
      case IrOpcode::kUint64LessThan:
        cont->OverwriteAndNegateIfEqual(kUnsignedLessThan);
        return VisitWord64Compare(selector, value, cont);
1673 1674 1675
      case IrOpcode::kUint64LessThanOrEqual:
        cont->OverwriteAndNegateIfEqual(kUnsignedLessThanOrEqual);
        return VisitWord64Compare(selector, value, cont);
1676
#endif
1677 1678 1679 1680 1681 1682 1683 1684 1685
      case IrOpcode::kFloat32Equal:
        cont->OverwriteAndNegateIfEqual(kEqual);
        return VisitFloat32Compare(selector, value, cont);
      case IrOpcode::kFloat32LessThan:
        cont->OverwriteAndNegateIfEqual(kUnsignedLessThan);
        return VisitFloat32Compare(selector, value, cont);
      case IrOpcode::kFloat32LessThanOrEqual:
        cont->OverwriteAndNegateIfEqual(kUnsignedLessThanOrEqual);
        return VisitFloat32Compare(selector, value, cont);
1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700
      case IrOpcode::kFloat64Equal:
        cont->OverwriteAndNegateIfEqual(kEqual);
        return VisitFloat64Compare(selector, value, cont);
      case IrOpcode::kFloat64LessThan:
        cont->OverwriteAndNegateIfEqual(kUnsignedLessThan);
        return VisitFloat64Compare(selector, value, cont);
      case IrOpcode::kFloat64LessThanOrEqual:
        cont->OverwriteAndNegateIfEqual(kUnsignedLessThanOrEqual);
        return VisitFloat64Compare(selector, value, cont);
      case IrOpcode::kProjection:
        // Check if this is the overflow output projection of an
        // <Operation>WithOverflow node.
        if (ProjectionIndexOf(value->op()) == 1u) {
          // We cannot combine the <Operation>WithOverflow with this branch
          // unless the 0th projection (the use of the actual value of the
1701
          // <Operation> is either nullptr, which means there's no use of the
1702 1703 1704 1705
          // actual value, or was already defined, which means it is scheduled
          // *AFTER* this branch).
          Node* const node = value->InputAt(0);
          Node* const result = NodeProperties::FindProjection(node, 0);
1706
          if (result == nullptr || selector->IsDefined(result)) {
1707 1708 1709 1710 1711 1712 1713 1714 1715 1716
            switch (node->opcode()) {
              case IrOpcode::kInt32AddWithOverflow:
                cont->OverwriteAndNegateIfEqual(kOverflow);
                return VisitBinop<Int32BinopMatcher>(
                    selector, node, kPPC_AddWithOverflow32, kInt16Imm, cont);
              case IrOpcode::kInt32SubWithOverflow:
                cont->OverwriteAndNegateIfEqual(kOverflow);
                return VisitBinop<Int32BinopMatcher>(selector, node,
                                                     kPPC_SubWithOverflow32,
                                                     kInt16Imm_Negate, cont);
1717 1718 1719
              case IrOpcode::kInt32MulWithOverflow:
                cont->OverwriteAndNegateIfEqual(kNotEqual);
                return EmitInt32MulWithOverflow(selector, node, cont);
1720 1721 1722
#if V8_TARGET_ARCH_PPC64
              case IrOpcode::kInt64AddWithOverflow:
                cont->OverwriteAndNegateIfEqual(kOverflow);
1723
                return VisitBinop<Int64BinopMatcher>(selector, node, kPPC_Add64,
1724 1725 1726 1727 1728 1729
                                                     kInt16Imm, cont);
              case IrOpcode::kInt64SubWithOverflow:
                cont->OverwriteAndNegateIfEqual(kOverflow);
                return VisitBinop<Int64BinopMatcher>(selector, node, kPPC_Sub,
                                                     kInt16Imm_Negate, cont);
#endif
1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777
              default:
                break;
            }
          }
        }
        break;
      case IrOpcode::kInt32Sub:
        return VisitWord32Compare(selector, value, cont);
      case IrOpcode::kWord32And:
        // TODO(mbandy): opportunity for rlwinm?
        return VisitWordCompare(selector, value, kPPC_Tst32, cont, true,
                                kInt16Imm_Unsigned);
// TODO(mbrandy): Handle?
// case IrOpcode::kInt32Add:
// case IrOpcode::kWord32Or:
// case IrOpcode::kWord32Xor:
// case IrOpcode::kWord32Sar:
// case IrOpcode::kWord32Shl:
// case IrOpcode::kWord32Shr:
// case IrOpcode::kWord32Ror:
#if V8_TARGET_ARCH_PPC64
      case IrOpcode::kInt64Sub:
        return VisitWord64Compare(selector, value, cont);
      case IrOpcode::kWord64And:
        // TODO(mbandy): opportunity for rldic?
        return VisitWordCompare(selector, value, kPPC_Tst64, cont, true,
                                kInt16Imm_Unsigned);
// TODO(mbrandy): Handle?
// case IrOpcode::kInt64Add:
// case IrOpcode::kWord64Or:
// case IrOpcode::kWord64Xor:
// case IrOpcode::kWord64Sar:
// case IrOpcode::kWord64Shl:
// case IrOpcode::kWord64Shr:
// case IrOpcode::kWord64Ror:
#endif
      default:
        break;
    }
  }

  // Branch could not be combined with a compare, emit compare against 0.
  PPCOperandGenerator g(selector);
  VisitCompare(selector, opcode, g.UseRegister(value), g.TempImmediate(0),
               cont);
}


1778 1779
void VisitWord32CompareZero(InstructionSelector* selector, Node* user,
                            Node* value, FlagsContinuation* cont) {
1780 1781 1782 1783 1784
  VisitWordCompareZero(selector, user, value, kPPC_Cmp32, cont);
}


#if V8_TARGET_ARCH_PPC64
1785 1786
void VisitWord64CompareZero(InstructionSelector* selector, Node* user,
                            Node* value, FlagsContinuation* cont) {
1787 1788 1789 1790
  VisitWordCompareZero(selector, user, value, kPPC_Cmp64, cont);
}
#endif

1791 1792
}  // namespace

1793 1794 1795 1796 1797 1798 1799

void InstructionSelector::VisitBranch(Node* branch, BasicBlock* tbranch,
                                      BasicBlock* fbranch) {
  FlagsContinuation cont(kNotEqual, tbranch, fbranch);
  VisitWord32CompareZero(this, branch, branch->InputAt(0), &cont);
}

1800
void InstructionSelector::VisitDeoptimizeIf(Node* node) {
1801
  DeoptimizeParameters p = DeoptimizeParametersOf(node->op());
1802
  FlagsContinuation cont = FlagsContinuation::ForDeoptimize(
1803
      kNotEqual, p.kind(), p.reason(), node->InputAt(1));
1804
  VisitWord32CompareZero(this, node, node->InputAt(0), &cont);
1805 1806 1807
}

void InstructionSelector::VisitDeoptimizeUnless(Node* node) {
1808
  DeoptimizeParameters p = DeoptimizeParametersOf(node->op());
1809
  FlagsContinuation cont = FlagsContinuation::ForDeoptimize(
1810
      kEqual, p.kind(), p.reason(), node->InputAt(1));
1811
  VisitWord32CompareZero(this, node, node->InputAt(0), &cont);
1812
}
1813

1814
void InstructionSelector::VisitTrapIf(Node* node, Runtime::FunctionId func_id) {
1815 1816 1817
  FlagsContinuation cont =
      FlagsContinuation::ForTrap(kNotEqual, func_id, node->InputAt(1));
  VisitWord32CompareZero(this, node, node->InputAt(0), &cont);
1818
}
1819

1820 1821
void InstructionSelector::VisitTrapUnless(Node* node,
                                          Runtime::FunctionId func_id) {
1822 1823 1824
  FlagsContinuation cont =
      FlagsContinuation::ForTrap(kEqual, func_id, node->InputAt(1));
  VisitWord32CompareZero(this, node, node->InputAt(0), &cont);
1825
}
1826

1827
void InstructionSelector::VisitSwitch(Node* node, const SwitchInfo& sw) {
1828 1829 1830
  PPCOperandGenerator g(this);
  InstructionOperand value_operand = g.UseRegister(node->InputAt(0));

1831 1832
  // Emit either ArchTableSwitch or ArchLookupSwitch.
  size_t table_space_cost = 4 + sw.value_range;
1833
  size_t table_time_cost = 3;
1834 1835 1836
  size_t lookup_space_cost = 3 + 2 * sw.case_count;
  size_t lookup_time_cost = sw.case_count;
  if (sw.case_count > 0 &&
1837 1838
      table_space_cost + 3 * table_time_cost <=
          lookup_space_cost + 3 * lookup_time_cost &&
1839
      sw.min_value > std::numeric_limits<int32_t>::min()) {
1840
    InstructionOperand index_operand = value_operand;
1841
    if (sw.min_value) {
1842
      index_operand = g.TempRegister();
1843
      Emit(kPPC_Sub, index_operand, value_operand,
1844
           g.TempImmediate(sw.min_value));
1845
    }
1846 1847
    // Generate a table lookup.
    return EmitTableSwitch(sw, index_operand);
1848 1849 1850
  }

  // Generate a sequence of conditional jumps.
1851
  return EmitLookupSwitch(sw, value_operand);
1852 1853 1854
}


1855
void InstructionSelector::VisitWord32Equal(Node* const node) {
1856
  FlagsContinuation cont = FlagsContinuation::ForSet(kEqual, node);
1857 1858 1859 1860 1861 1862 1863 1864 1865
  Int32BinopMatcher m(node);
  if (m.right().Is(0)) {
    return VisitWord32CompareZero(this, m.node(), m.left().node(), &cont);
  }
  VisitWord32Compare(this, node, &cont);
}


void InstructionSelector::VisitInt32LessThan(Node* node) {
1866
  FlagsContinuation cont = FlagsContinuation::ForSet(kSignedLessThan, node);
1867 1868 1869 1870 1871
  VisitWord32Compare(this, node, &cont);
}


void InstructionSelector::VisitInt32LessThanOrEqual(Node* node) {
1872 1873
  FlagsContinuation cont =
      FlagsContinuation::ForSet(kSignedLessThanOrEqual, node);
1874 1875 1876 1877 1878
  VisitWord32Compare(this, node, &cont);
}


void InstructionSelector::VisitUint32LessThan(Node* node) {
1879
  FlagsContinuation cont = FlagsContinuation::ForSet(kUnsignedLessThan, node);
1880 1881 1882 1883 1884
  VisitWord32Compare(this, node, &cont);
}


void InstructionSelector::VisitUint32LessThanOrEqual(Node* node) {
1885 1886
  FlagsContinuation cont =
      FlagsContinuation::ForSet(kUnsignedLessThanOrEqual, node);
1887 1888 1889 1890 1891 1892
  VisitWord32Compare(this, node, &cont);
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Equal(Node* const node) {
1893
  FlagsContinuation cont = FlagsContinuation::ForSet(kEqual, node);
1894 1895 1896 1897 1898 1899 1900 1901 1902
  Int64BinopMatcher m(node);
  if (m.right().Is(0)) {
    return VisitWord64CompareZero(this, m.node(), m.left().node(), &cont);
  }
  VisitWord64Compare(this, node, &cont);
}


void InstructionSelector::VisitInt64LessThan(Node* node) {
1903
  FlagsContinuation cont = FlagsContinuation::ForSet(kSignedLessThan, node);
1904 1905 1906 1907 1908
  VisitWord64Compare(this, node, &cont);
}


void InstructionSelector::VisitInt64LessThanOrEqual(Node* node) {
1909 1910
  FlagsContinuation cont =
      FlagsContinuation::ForSet(kSignedLessThanOrEqual, node);
1911 1912 1913 1914
  VisitWord64Compare(this, node, &cont);
}


1915
void InstructionSelector::VisitUint64LessThan(Node* node) {
1916
  FlagsContinuation cont = FlagsContinuation::ForSet(kUnsignedLessThan, node);
1917 1918 1919 1920
  VisitWord64Compare(this, node, &cont);
}


1921
void InstructionSelector::VisitUint64LessThanOrEqual(Node* node) {
1922 1923
  FlagsContinuation cont =
      FlagsContinuation::ForSet(kUnsignedLessThanOrEqual, node);
1924 1925 1926 1927
  VisitWord64Compare(this, node, &cont);
}
#endif

1928 1929 1930 1931 1932 1933 1934 1935 1936
void InstructionSelector::VisitInt32MulWithOverflow(Node* node) {
  if (Node* ovf = NodeProperties::FindProjection(node, 1)) {
    FlagsContinuation cont = FlagsContinuation::ForSet(kNotEqual, ovf);
    return EmitInt32MulWithOverflow(this, node, &cont);
  }
  FlagsContinuation cont;
  EmitInt32MulWithOverflow(this, node, &cont);
}

1937

1938
void InstructionSelector::VisitFloat32Equal(Node* node) {
1939
  FlagsContinuation cont = FlagsContinuation::ForSet(kEqual, node);
1940 1941 1942 1943 1944
  VisitFloat32Compare(this, node, &cont);
}


void InstructionSelector::VisitFloat32LessThan(Node* node) {
1945
  FlagsContinuation cont = FlagsContinuation::ForSet(kUnsignedLessThan, node);
1946 1947 1948 1949 1950
  VisitFloat32Compare(this, node, &cont);
}


void InstructionSelector::VisitFloat32LessThanOrEqual(Node* node) {
1951 1952
  FlagsContinuation cont =
      FlagsContinuation::ForSet(kUnsignedLessThanOrEqual, node);
1953 1954 1955 1956
  VisitFloat32Compare(this, node, &cont);
}


1957
void InstructionSelector::VisitFloat64Equal(Node* node) {
1958
  FlagsContinuation cont = FlagsContinuation::ForSet(kEqual, node);
1959 1960 1961 1962 1963
  VisitFloat64Compare(this, node, &cont);
}


void InstructionSelector::VisitFloat64LessThan(Node* node) {
1964
  FlagsContinuation cont = FlagsContinuation::ForSet(kUnsignedLessThan, node);
1965 1966 1967 1968 1969
  VisitFloat64Compare(this, node, &cont);
}


void InstructionSelector::VisitFloat64LessThanOrEqual(Node* node) {
1970 1971
  FlagsContinuation cont =
      FlagsContinuation::ForSet(kUnsignedLessThanOrEqual, node);
1972 1973 1974 1975
  VisitFloat64Compare(this, node, &cont);
}


1976 1977 1978
void InstructionSelector::EmitPrepareArguments(
    ZoneVector<PushParameter>* arguments, const CallDescriptor* descriptor,
    Node* node) {
1979
  PPCOperandGenerator g(this);
1980 1981 1982 1983

  // Prepare for C function call.
  if (descriptor->IsCFunctionCall()) {
    Emit(kArchPrepareCallCFunction |
1984
             MiscField::encode(static_cast<int>(descriptor->ParameterCount())),
1985 1986 1987 1988
         0, nullptr, 0, nullptr);

    // Poke any stack arguments.
    int slot = kStackFrameExtraParamSlot;
1989 1990
    for (PushParameter input : (*arguments)) {
      Emit(kPPC_StoreToStackSlot, g.NoOutput(), g.UseRegister(input.node()),
1991 1992 1993 1994 1995
           g.TempImmediate(slot));
      ++slot;
    }
  } else {
    // Push any stack arguments.
1996
    int num_slots = static_cast<int>(descriptor->StackParameterCount());
1997
    int slot = 0;
1998
    for (PushParameter input : (*arguments)) {
1999
      if (slot == 0) {
2000 2001
        DCHECK(input.node());
        Emit(kPPC_PushFrame, g.NoOutput(), g.UseRegister(input.node()),
2002 2003
             g.TempImmediate(num_slots));
      } else {
2004
        // Skip any alignment holes in pushed nodes.
2005 2006
        if (input.node()) {
          Emit(kPPC_StoreToStackSlot, g.NoOutput(), g.UseRegister(input.node()),
2007 2008
               g.TempImmediate(slot));
        }
2009 2010 2011
      }
      ++slot;
    }
2012
  }
2013 2014 2015
}


2016
bool InstructionSelector::IsTailCallAddressImmediate() { return false; }
2017

2018
int InstructionSelector::GetTempsCountForTailCallFromJSFunction() { return 3; }
2019

2020 2021
void InstructionSelector::VisitFloat64ExtractLowWord32(Node* node) {
  PPCOperandGenerator g(this);
2022
  Emit(kPPC_DoubleExtractLowWord32, g.DefineAsRegister(node),
2023 2024 2025 2026 2027 2028
       g.UseRegister(node->InputAt(0)));
}


void InstructionSelector::VisitFloat64ExtractHighWord32(Node* node) {
  PPCOperandGenerator g(this);
2029
  Emit(kPPC_DoubleExtractHighWord32, g.DefineAsRegister(node),
2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040
       g.UseRegister(node->InputAt(0)));
}


void InstructionSelector::VisitFloat64InsertLowWord32(Node* node) {
  PPCOperandGenerator g(this);
  Node* left = node->InputAt(0);
  Node* right = node->InputAt(1);
  if (left->opcode() == IrOpcode::kFloat64InsertHighWord32 &&
      CanCover(node, left)) {
    left = left->InputAt(1);
2041
    Emit(kPPC_DoubleConstruct, g.DefineAsRegister(node), g.UseRegister(left),
2042 2043 2044
         g.UseRegister(right));
    return;
  }
2045
  Emit(kPPC_DoubleInsertLowWord32, g.DefineSameAsFirst(node),
2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056
       g.UseRegister(left), g.UseRegister(right));
}


void InstructionSelector::VisitFloat64InsertHighWord32(Node* node) {
  PPCOperandGenerator g(this);
  Node* left = node->InputAt(0);
  Node* right = node->InputAt(1);
  if (left->opcode() == IrOpcode::kFloat64InsertLowWord32 &&
      CanCover(node, left)) {
    left = left->InputAt(1);
2057
    Emit(kPPC_DoubleConstruct, g.DefineAsRegister(node), g.UseRegister(right),
2058 2059 2060
         g.UseRegister(left));
    return;
  }
2061
  Emit(kPPC_DoubleInsertHighWord32, g.DefineSameAsFirst(node),
2062 2063 2064
       g.UseRegister(left), g.UseRegister(right));
}

2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087
void InstructionSelector::VisitAtomicLoad(Node* node) {
  LoadRepresentation load_rep = LoadRepresentationOf(node->op());
  PPCOperandGenerator g(this);
  Node* base = node->InputAt(0);
  Node* index = node->InputAt(1);
  ArchOpcode opcode = kArchNop;
  switch (load_rep.representation()) {
    case MachineRepresentation::kWord8:
      opcode = load_rep.IsSigned() ? kAtomicLoadInt8 : kAtomicLoadUint8;
      break;
    case MachineRepresentation::kWord16:
      opcode = load_rep.IsSigned() ? kAtomicLoadInt16 : kAtomicLoadUint16;
      break;
    case MachineRepresentation::kWord32:
      opcode = kAtomicLoadWord32;
      break;
    default:
      UNREACHABLE();
      return;
  }
  Emit(opcode | AddressingModeField::encode(kMode_MRR),
      g.DefineAsRegister(node), g.UseRegister(base), g.UseRegister(index));
}
2088

2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119
void InstructionSelector::VisitAtomicStore(Node* node) {
  MachineRepresentation rep = AtomicStoreRepresentationOf(node->op());
  PPCOperandGenerator g(this);
  Node* base = node->InputAt(0);
  Node* index = node->InputAt(1);
  Node* value = node->InputAt(2);
  ArchOpcode opcode = kArchNop;
  switch (rep) {
    case MachineRepresentation::kWord8:
      opcode = kAtomicStoreWord8;
      break;
    case MachineRepresentation::kWord16:
      opcode = kAtomicStoreWord16;
      break;
    case MachineRepresentation::kWord32:
      opcode = kAtomicStoreWord32;
      break;
    default:
      UNREACHABLE();
      return;
  }

  InstructionOperand inputs[4];
  size_t input_count = 0;
  inputs[input_count++] = g.UseUniqueRegister(base);
  inputs[input_count++] = g.UseUniqueRegister(index);
  inputs[input_count++] = g.UseUniqueRegister(value);
  Emit(opcode | AddressingModeField::encode(kMode_MRR),
      0, nullptr, input_count, inputs);
}

2120 2121 2122 2123 2124 2125
void InstructionSelector::VisitAtomicExchange(Node* node) {
  PPCOperandGenerator g(this);
  Node* base = node->InputAt(0);
  Node* index = node->InputAt(1);
  Node* value = node->InputAt(2);
  ArchOpcode opcode = kArchNop;
2126
  MachineType type = AtomicOpRepresentationOf(node->op());
2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152
  if (type == MachineType::Int8()) {
    opcode = kAtomicExchangeInt8;
  } else if (type == MachineType::Uint8()) {
    opcode = kAtomicExchangeUint8;
  } else if (type == MachineType::Int16()) {
    opcode = kAtomicExchangeInt16;
  } else if (type == MachineType::Uint16()) {
    opcode = kAtomicExchangeUint16;
  } else if (type == MachineType::Int32() || type == MachineType::Uint32()) {
    opcode = kAtomicExchangeWord32;
  } else {
    UNREACHABLE();
    return;
  }

  AddressingMode addressing_mode = kMode_MRR;
  InstructionOperand inputs[3];
  size_t input_count = 0;
  inputs[input_count++] = g.UseUniqueRegister(base);
  inputs[input_count++] = g.UseUniqueRegister(index);
  inputs[input_count++] = g.UseUniqueRegister(value);
  InstructionOperand outputs[1];
  outputs[0] = g.UseUniqueRegister(node);
  InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
  Emit(code, 1, outputs, input_count, inputs);
}
2153

2154 2155 2156 2157
void InstructionSelector::VisitAtomicCompareExchange(Node* node) {
  UNIMPLEMENTED();
}

2158 2159 2160 2161 2162 2163 2164 2165 2166 2167
void InstructionSelector::VisitAtomicAdd(Node* node) { UNIMPLEMENTED(); }

void InstructionSelector::VisitAtomicSub(Node* node) { UNIMPLEMENTED(); }

void InstructionSelector::VisitAtomicAnd(Node* node) { UNIMPLEMENTED(); }

void InstructionSelector::VisitAtomicOr(Node* node) { UNIMPLEMENTED(); }

void InstructionSelector::VisitAtomicXor(Node* node) { UNIMPLEMENTED(); }

2168 2169 2170 2171 2172 2173 2174 2175
void InstructionSelector::VisitInt32AbsWithOverflow(Node* node) {
  UNREACHABLE();
}

void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
  UNREACHABLE();
}

2176 2177 2178
// static
MachineOperatorBuilder::Flags
InstructionSelector::SupportedMachineOperatorFlags() {
2179 2180
  return MachineOperatorBuilder::kFloat32RoundDown |
         MachineOperatorBuilder::kFloat64RoundDown |
2181
         MachineOperatorBuilder::kFloat32RoundUp |
2182
         MachineOperatorBuilder::kFloat64RoundUp |
2183
         MachineOperatorBuilder::kFloat32RoundTruncate |
2184
         MachineOperatorBuilder::kFloat64RoundTruncate |
2185
         MachineOperatorBuilder::kFloat64RoundTiesAway |
2186 2187
         MachineOperatorBuilder::kWord32Popcnt |
         MachineOperatorBuilder::kWord64Popcnt;
2188 2189 2190
  // We omit kWord32ShiftIsSafe as s[rl]w use 0x3f as a mask rather than 0x1f.
}

2191 2192 2193 2194 2195 2196 2197
// static
MachineOperatorBuilder::AlignmentRequirements
InstructionSelector::AlignmentRequirements() {
  return MachineOperatorBuilder::AlignmentRequirements::
      FullUnalignedAccessSupport();
}

2198 2199 2200
}  // namespace compiler
}  // namespace internal
}  // namespace v8