Commit 6ae6d3f8 authored by mbrandy's avatar mbrandy Committed by Commit bot

PPC: [turbofan] Optimize loading 64-bit SMIs.

Especially when loading and untagging SMIs within code stubs,
instances of the following pattern appear in the generated code:

    ld    <dst>, <offset>(<base>)
    sradi <dst>,<dst>,32

This CL changes that code to:

    lwa   <dst>, <SmiWordOffset(offset)>(<base>)

R=joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1855533002

Cr-Commit-Position: refs/heads/master@{#35216}
parent d8cd323d
......@@ -863,6 +863,30 @@ void InstructionSelector::VisitWord32PairSar(Node* node) {
#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Sar(Node* node) {
PPCOperandGenerator g(this);
Int64BinopMatcher m(node);
if (CanCover(m.node(), m.left().node()) && m.left().IsLoad() &&
m.right().Is(32)) {
// Just load and sign-extend the interesting 4 bytes instead. This happens,
// for example, when we're loading and untagging SMIs.
BaseWithIndexAndDisplacement64Matcher mleft(m.left().node(), true);
if (mleft.matches() && mleft.index() == nullptr) {
int64_t offset = 0;
Node* displacement = mleft.displacement();
if (displacement != nullptr) {
Int64Matcher mdisplacement(displacement);
DCHECK(mdisplacement.HasValue());
offset = mdisplacement.Value();
}
offset = SmiWordOffset(offset);
if (g.CanBeImmediate(offset, kInt16Imm_4ByteAligned)) {
Emit(kPPC_LoadWordS32 | AddressingModeField::encode(kMode_MRI),
g.DefineAsRegister(node), g.UseRegister(mleft.base()),
g.TempImmediate(offset));
return;
}
}
}
VisitRRO(this, kPPC_ShiftRightAlg64, node, kShift64Imm);
}
#endif
......
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