PPC64: Implemented the RoundUint64ToFloat64 TurboFan operator.

R=ahaas@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com, dstence@us.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1440733002

Cr-Commit-Position: refs/heads/master@{#31949}

src/compiler/ppc/code-generator-ppc.cc

@@ -1095,6 +1095,11 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       __ ConvertInt64ToDouble(i.InputRegister(0), i.OutputDoubleRegister());
       DCHECK_EQ(LeaveRC, i.OutputRCBit());
       break;
+    case kPPC_Uint64ToDouble:
+      __ ConvertUnsignedInt64ToDouble(i.InputRegister(0),
+                                      i.OutputDoubleRegister());
+      DCHECK_EQ(LeaveRC, i.OutputRCBit());
+      break;
 #endif
     case kPPC_Int32ToDouble:
       __ ConvertIntToDouble(i.InputRegister(0), i.OutputDoubleRegister());

src/compiler/ppc/instruction-codes-ppc.h

@@ -80,6 +80,7 @@ namespace compiler {
   V(PPC_Int64ToInt32)              \
   V(PPC_Int64ToFloat32)            \
   V(PPC_Int64ToDouble)             \
+  V(PPC_Uint64ToDouble)            \
   V(PPC_Int32ToDouble)             \
   V(PPC_Uint32ToDouble)            \
   V(PPC_Float32ToDouble)           \

src/compiler/ppc/instruction-selector-ppc.cc

@@ -974,7 +974,7 @@ void InstructionSelector::VisitRoundInt64ToFloat64(Node* node) {
 
 
 void InstructionSelector::VisitRoundUint64ToFloat64(Node* node) {
-  UNIMPLEMENTED();
+  VisitRR(this, kPPC_Uint64ToDouble, node);
 }
 #endif
 

src/ppc/assembler-ppc.cc

@@ -2163,6 +2163,12 @@ void Assembler::fcfid(const DoubleRegister frt, const DoubleRegister frb,
 }
 
 
+void Assembler::fcfidu(const DoubleRegister frt, const DoubleRegister frb,
+                       RCBit rc) {
+  emit(EXT4 | FCFIDU | frt.code() * B21 | frb.code() * B11 | rc);
+}
+
+
 void Assembler::fcfids(const DoubleRegister frt, const DoubleRegister frb,
                        RCBit rc) {
   emit(EXT3 | FCFID | frt.code() * B21 | frb.code() * B11 | rc);

src/ppc/assembler-ppc.h

@@ -1050,6 +1050,8 @@ class Assembler : public AssemblerBase {
             RCBit rc = LeaveRC);
   void fcfid(const DoubleRegister frt, const DoubleRegister frb,
              RCBit rc = LeaveRC);
+  void fcfidu(const DoubleRegister frt, const DoubleRegister frb,
+              RCBit rc = LeaveRC);
   void fcfids(const DoubleRegister frt, const DoubleRegister frb,
               RCBit rc = LeaveRC);
   void fctid(const DoubleRegister frt, const DoubleRegister frb,

src/ppc/constants-ppc.h

@@ -292,7 +292,8 @@ enum OpcodeExt4 {
   MTFSF = 711 << 1,   // move to FPSCR fields XFL-form
   FCFID = 846 << 1,   // Floating convert from integer doubleword
   FCTID = 814 << 1,   // Floating convert from integer doubleword
-  FCTIDZ = 815 << 1   // Floating convert from integer doubleword
+  FCTIDZ = 815 << 1,  // Floating convert from integer doubleword
+  FCFIDU = 974 << 1   // Floating convert from integer doubleword unsigned
 };
 
 enum OpcodeExt5 {

src/ppc/disasm-ppc.cc

@@ -945,6 +945,10 @@ void Decoder::DecodeExt4(Instruction* instr) {
       Format(instr, "fcfid'.  'Dt, 'Db");
       break;
     }
+    case FCFIDU: {
+      Format(instr, "fcfidu'. 'Dt, 'Db");
+      break;
+    }
     case FCTID: {
       Format(instr, "fctid   'Dt, 'Db");
       break;

src/ppc/macro-assembler-ppc.cc

@@ -671,6 +671,13 @@ void MacroAssembler::ConvertInt64ToDouble(Register src,
 }
 
 
+void MacroAssembler::ConvertUnsignedInt64ToDouble(Register src,
+                                                  DoubleRegister double_dst) {
+  MovInt64ToDouble(double_dst, src);
+  fcfidu(double_dst, double_dst);
+}
+
+
 void MacroAssembler::ConvertInt64ToFloat(Register src,
                                          DoubleRegister double_dst) {
   MovInt64ToDouble(double_dst, src);

src/ppc/macro-assembler-ppc.h

@@ -388,6 +388,7 @@ class MacroAssembler : public Assembler {
 
 #if V8_TARGET_ARCH_PPC64
   void ConvertInt64ToDouble(Register src, DoubleRegister double_dst);
+  void ConvertUnsignedInt64ToDouble(Register src, DoubleRegister double_dst);
   void ConvertInt64ToFloat(Register src, DoubleRegister double_dst);
 #endif
 

src/ppc/simulator-ppc.cc

@@ -2892,6 +2892,15 @@ void Simulator::ExecuteExt4(Instruction* instr) {
       set_d_register_from_double(frt, frt_val);
       return;
     }
+    case FCFIDU: {
+      int frt = instr->RTValue();
+      int frb = instr->RBValue();
+      double t_val = get_double_from_d_register(frb);
+      uint64_t* frb_val_p = reinterpret_cast<uint64_t*>(&t_val);
+      double frt_val = static_cast<double>(*frb_val_p);
+      set_d_register_from_double(frt, frt_val);
+      return;
+    }
     case FCTID: {
       int frt = instr->RTValue();
       int frb = instr->RBValue();