- 07 Apr, 2022 1 commit
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Lu Yahan authored
Port d36f596e Change-Id: I13c9d23bb06841e1f6cbb07c68968fb3cc9eb01a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3573784 Auto-Submit: Yahan Lu <yahan@iscas.ac.cn> Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Commit-Queue: ji qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#79836}
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- 25 Mar, 2022 1 commit
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Lu Yahan authored
Change-Id: Iac021f8666058042f5c26cf07d0f3810a1d451fc Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3528374 Auto-Submit: Yahan Lu <yahan@iscas.ac.cn> Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#79617}
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- 17 Mar, 2022 1 commit
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Yuxiang Cao authored
Bug: v8:12707 Change-Id: I411950dc92336f73f10614e75bd64647d4137857 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3523995Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Reviewed-by:
Yahan Lu <yahan@iscas.ac.cn> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#79503}
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- 14 Mar, 2022 1 commit
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Leszek Swirski authored
Modernise the RegList interface to be a proper class, rather than a typedef to an integer, and add proper methods onto it rather than ad-hoc bit manipulation. In particular, this makes RegList typesafe, adding a DoubleRegList for DoubleRegisters. The Arm64 CPURegList isn't updated to use (or extend) the new RegList interface, because of its weird type-erasing semantics (it can store Registers and VRegisters). Maybe in the future we'll want to get rid of CPURegList entirely and use RegList/DoubleRegList directly. Change-Id: I3cb2a4d386cb92a4dcd2edbdd3fba9ef71f354d6 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3516747 Commit-Queue: Leszek Swirski <leszeks@chromium.org> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Camillo Bruni <cbruni@chromium.org> Reviewed-by:
Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/main@{#79460}
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- 08 Mar, 2022 1 commit
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Lu Yahan authored
and delete extra asm_comment Change-Id: Ia22f4bc622387e7c9a1c830b9f213d9554f0029e Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3507121Reviewed-by:
Clemens Backes <clemensb@chromium.org> Auto-Submit: Yahan Lu <yahan@iscas.ac.cn> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#79401}
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- 23 Feb, 2022 1 commit
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Lu Yahan authored
Change-Id: I4b83907b735994a729b57b9c4a75d3672ce78b15 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3482916Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Auto-Submit: Yahan Lu <yahan@iscas.ac.cn> Reviewed-by:
Yahan Lu <yahan@iscas.ac.cn> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#79218}
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- 22 Feb, 2022 1 commit
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Yuxiang Cao authored
Implement vector widening floating-point instructions: add/subtract/multiply/multiply-add/reduction instructions, eg. `vfwadd.vf`, `vfwmacc.vf`, `vfwredosum.vs`. Add tests and simulator support for all newly added instructions. Bug: v8:11976 Change-Id: I0909eeab24ba075c5a21743bb49538f154ce8aa2 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3442257Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#79205}
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- 21 Feb, 2022 1 commit
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Lu Yahan authored
Building with Gcc-10 causes error "explicit specialization in non-namespace scope". This change fixes it. Bug: v8:12649 Change-Id: I36b2b042b336c2dfd32ba5541fdbbdb8dc8b4fd7 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3473997Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Commit-Queue: ji qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#79185}
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- 10 Jan, 2022 1 commit
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Yujie Wang authored
- Implement `kRiscvF32x4RecipApprox`, `kRiscvF32x4RecipSqrtApprox`, `kRiscvF32x4Qfma`, `kRiscvF32x4Qfms`, `kRiscvF64x2Qfma` and `kRiscvF64x2Qfms` in `code-generator-riscv64.cc` - Reuse lane-select, min-max and trunc instrctions in `instruction-selector-riscv64.cc` Bug: v8:11976 Change-Id: I8566f7e082a3d7071ec9fc64c742da82425a4d4d Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3364077Reviewed-by:
Yahan Lu <yahan@iscas.ac.cn> Reviewed-by:
Clemens Backes <clemensb@chromium.org> Reviewed-by:
Tobias Tebbi <tebbi@chromium.org> Cr-Commit-Position: refs/heads/main@{#78524}
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- 27 Dec, 2021 1 commit
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Yujie Wang authored
- Add I8x16_Popcnt for WASM SIMD - Add vcpop_m and vfirst_m for riscv64 simulator Bug: v8:11976 Change-Id: I2b945bb947da0998663cac86f867f09d386b81a4 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3356201Reviewed-by:
Yahan Lu <yahan@iscas.ac.cn> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#78444}
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- 23 Dec, 2021 1 commit
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Lu Yahan authored
Change-Id: I7e61221775a616943886cdb369eb9bbe5e110a32 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3347499Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Commit-Queue: ji qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#78436}
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- 22 Dec, 2021 1 commit
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Lu Yahan authored
This commit allows using unaligned load/store, which is more efficient for 2 bytes,4 bytes and 8 bytes memory access. Use RISCV_HAS_NO_UNALIGNED to control whether enable the fast path or not. Change-Id: I1d321e6e5fa5bc31541c8dbfe582881d80743483 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3329803Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#78427}
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- 08 Dec, 2021 1 commit
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Lu Yahan authored
Add func UseImmediate64(int64_t imm) into instruction-selector-impl Bug: v8:11976 Change-Id: I274ab59cc6d9a9cdc8b4081a7c418c56c3e8f5b7 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3312453Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Reviewed-by:
Maya Lekova <mslekova@chromium.org> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#78288}
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- 25 Nov, 2021 1 commit
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Lu Yahan authored
Bug: v8:11976 Change-Id: Ifdce8e668c4b0fe20180c8d28b9c1d4abe705a67 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3297354 Commit-Queue: ji qiu <qiuji@iscas.ac.cn> Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#78078}
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- 16 Nov, 2021 1 commit
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Lu Yahan authored
Fix node build failed Change-Id: I3f465bcdaa17b0f1a6c497e9ab5ef9e50cbe5017 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3281721Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Commit-Queue: ji qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#77917}
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- 12 Nov, 2021 1 commit
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Yujie Wang authored
- Add Wasm SIMD packing instruction: `LiftoffAssembler::emit_i8x16_{s,u}convert_i16x8` - Add Wasm SIMD unpacking instructions: `LiftoffAssembler::emit_i64x2_{s,u}convert_i32x4_{low,high}` `LiftoffAssembler::emit_i32x4_{s,u}convert_i16x8_{low,high}` `LiftoffAssembler::emit_i64x2_{s,u}convert_i32x4_{low,high}` - Add RVV instrucions: `vzext_vf{2,4,8}` and `vsext_vf{2,4,8}` - Fixed simulator for `vslidedown_vi` Bug: v8:11976 Change-Id: Idd383bc566589ce183f4fcef2201d2ccfe03519f Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3273812Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Reviewed-by:
Yahan Lu <yahan@iscas.ac.cn> Commit-Queue: ji qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#77865}
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- 03 Nov, 2021 1 commit
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Lu Yahan authored
Port 4de20cb1 Change-Id: I8801bbcf9647c1abcb9cc5fb41720009e002d153 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3257964 Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Commit-Queue: ji qiu <qiuji@iscas.ac.cn> Auto-Submit: Yahan Lu <yahan@iscas.ac.cn> Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#77667}
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- 02 Nov, 2021 1 commit
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Lu Yahan authored
Port e127f584 Change-Id: Id0eb9205c3e94cb504340110ff6a42bc94a80cc1 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3251133 Auto-Submit: Yahan Lu <yahan@iscas.ac.cn> Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#77634}
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- 28 Oct, 2021 1 commit
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Yujie Wang authored
Implement `LiftoffAssembler::emit_i16x8_sconvert_i32x4` for riscv. Add tests for rvv integer and floating-point instructions. Add simulator support for rvv instructions, e.g. `vfmadd`, `vnclip`. Fixed order of operands for `vfdiv.vv`. Bug: v8:11976 Change-Id: I0691ac66771468533c5994be1fc8a86b09d3c738 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3225319Reviewed-by:
Yahan Lu <yahan@iscas.ac.cn> Reviewed-by:
Michael Lippautz <mlippautz@chromium.org> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#77595}
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- 08 Oct, 2021 1 commit
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Lu Yahan authored
Change-Id: Iba439f2de9da359baeebd23482880013939b3066 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3212059 Auto-Submit: Yahan Lu <yahan@iscas.ac.cn> Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Commit-Queue: ji qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#77294}
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- 26 Sep, 2021 1 commit
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Lu Yahan authored
Change-Id: Ifa2236b650f78ad851930e69e0387d8952f197c1 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3178142 Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Reviewed-by:
Brice Dobry <brice.dobry@futurewei.com> Cr-Commit-Position: refs/heads/main@{#77072}
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- 17 Sep, 2021 1 commit
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Lu Yahan authored
vragther require that the destination vector register group cannot overlap with the source vector register groups, otherwise an illegal instruction exception is raised. Change-Id: I6d23ea80edc4a80be961531ded855ff372ca0da0 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3161777 Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Reviewed-by:
Ji Qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#76895}
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- 15 Sep, 2021 1 commit
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Lu Yahan authored
Bug: v8:11976 Change-Id: I19e1ef43f073c8155dbc2890de0f331782eb7aac Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3156588 Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
Ji Qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#76835}
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- 07 Sep, 2021 1 commit
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Lu Yahan authored
- Add vsetivli/I8x16Add/vl/vse8 - In Rvv, Vector regs is different from Float Regs. But in this cl, in order to facilitate modification, it is assumed that the vector register and float register share a set of register codes. - Because v0 is mask reg, we can't allocate it . And transfer float into vector reg, so i delete ft0 from AllocateReg. Bug: v8:11976 Change-Id: I66185d1f5ead985489bcbdf671b131f02a6bd7c2 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3005768 Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
Thibaud Michaud <thibaudm@chromium.org> Reviewed-by:
Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Cr-Commit-Position: refs/heads/main@{#76700}
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- 02 Sep, 2021 1 commit
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QiuJi authored
Also fix several out of date comments. Change-Id: I15ee6c718ad50f231cd0a8e5c6416ccb58375140 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3121693 Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
Brice Dobry <brice.dobry@futurewei.com> Cr-Commit-Position: refs/heads/main@{#76633}
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- 27 Aug, 2021 1 commit
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Lu Yahan authored
This is causing a warning on newer build configs (crrev.com/c/3117087) Change-Id: I8cf7644861c27b9959283510163ecf8acdb6bdc8 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3124174 Auto-Submit: Yahan Lu <yahan@iscas.ac.cn> Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
Ji Qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#76523}
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- 24 Aug, 2021 1 commit
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Lu Yahan authored
Bug: v8:12132 Change-Id: Ib81c4141a07ad5269eb0abda839ebc42b8170170 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3114159 Auto-Submit: Yahan Lu <yahan@iscas.ac.cn> Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
Ji Qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#76447}
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- 17 Aug, 2021 1 commit
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Yu Yin authored
Fix build failed with: is_component_build = true use_goma = true Change-Id: Ia06175c091e94e36aa71c134b056b4d6b88e5c96 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3098826Reviewed-by:
Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
Zhao Jiazhong <zhaojiazhong-hf@loongson.cn> Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn> Cr-Commit-Position: refs/heads/master@{#76331}
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- 06 Aug, 2021 1 commit
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Derek Tu authored
Lets the macro-assembler compile RISC-V C-Extension instructions when the corresponding flag is set during runtime. Change-Id: I443d026653b9945ac7ccff41b0ca3f7db9b65775 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3039384Reviewed-by:
Brice Dobry <brice.dobry@futurewei.com> Reviewed-by:
Ji Qiu <qiuji@iscas.ac.cn> Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/master@{#76128}
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- 19 Jul, 2021 1 commit
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Lu Yahan authored
When run jalr and pc is contained in Builtin code range, sim will print "Call to builtin". This cl reduces the print of "Call to builtin" which only be printed when call builtin and return to builtin. Change-Id: Ic84101e892ed661cf41ac4d8d83bfff1ef7b4d5f Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3030382 Auto-Submit: Yahan Lu <yahan@iscas.ac.cn> Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
Ji Qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/master@{#75772}
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- 08 Jul, 2021 1 commit
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QiuJi authored
Change-Id: I1e90914aba634579a39a269b9a92881d488d4299 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3005769 Commit-Queue: Brice Dobry <brice.dobry@futurewei.com> Reviewed-by:
Brice Dobry <brice.dobry@futurewei.com> Cr-Commit-Position: refs/heads/master@{#75622}
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- 18 Jun, 2021 1 commit
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Dan Elphick authored
The adding of base:: was mostly prepared using git grep and sed: git grep -l <pattern> | grep -v base/vector.h | \ xargs sed -i 's/\b<pattern>\b/base::<pattern>/ with lots of manual clean-ups due to the resulting v8::internal::base::Vectors. #includes were fixed using: git grep -l "src/utils/vector.h" | \ axargs sed -i 's!src/utils/vector.h!src/base/vector.h!' Bug: v8:11879 Change-Id: I3e6d622987fee4478089c40539724c19735bd625 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2968412Reviewed-by:
Clemens Backes <clemensb@chromium.org> Reviewed-by:
Hannes Payer <hpayer@chromium.org> Commit-Queue: Dan Elphick <delphick@chromium.org> Cr-Commit-Position: refs/heads/master@{#75243}
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- 17 Jun, 2021 1 commit
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Lu Yahan authored
Change-Id: I0a614fa6c381770f56037f0401db008a37c71dca Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2966209 Auto-Submit: Yahan Lu <yahan@iscas.ac.cn> Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
Ji Qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/master@{#75199}
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- 16 Jun, 2021 1 commit
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Lu Yahan authored
- 2944844: [sparkplug][arm][arm64[ia32] Callee-saved registers for RecordWrite - Delete kTestReg due to 2945538 - 2949104: [runtime] Rename Builtins::Name to Builtin Change-Id: I33d12df7cbee6842a05c1dbe3e6158be1ff4cbc7 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2952865 Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Reviewed-by:
Brice Dobry <brice.dobry@futurewei.com> Reviewed-by:
Ji Qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/master@{#75168}
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- 28 May, 2021 1 commit
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Lu Yahan authored
And add s10 to scratch_register_list. Clean up t* register used in macroassembler Bug: v8:7703 Change-Id: Ib8477cd7528b8c2a2297da3f46659f30af45286e Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2914246Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Brice Dobry <brice.dobry@futurewei.com> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/master@{#74841}
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- 27 May, 2021 1 commit
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Derek Tu authored
Adds the following CB type RISC-V instructions to the assembler: c.beqz, c.bnez, c.andi, c.srai, c.srli. Also removes sext_xlen from RVC instructions c.xor, c.or, c.and. Change-Id: I96ce4693019c28235ccd4f85d0a68ca89a3f4096 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2912922Reviewed-by:
Brice Dobry <brice.dobry@futurewei.com> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Commit-Queue: Brice Dobry <brice.dobry@futurewei.com> Cr-Commit-Position: refs/heads/master@{#74801}
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- 11 May, 2021 1 commit
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Lu Yahan authored
Change-Id: I89ceb023d109f3ad69c0d679135c52cd278b4af3 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2878150 Auto-Submit: Yahan Lu <yahan@iscas.ac.cn> Commit-Queue: Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Cr-Commit-Position: refs/heads/master@{#74494}
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- 30 Apr, 2021 1 commit
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Clemens Backes authored
cpplint rules change over time, and we change the exact rules we enable for v8. This CL removes NOLINT annotations which are not needed according to the currently enabled rules. R=jkummerow@chromium.org Bug: v8:11717 Change-Id: I29e8dfca88f871b5d6b4c6422d036157021514da Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2862762Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/master@{#74302}
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- 16 Apr, 2021 1 commit
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Yahan Lu authored
Optimize FPUCanonicalizeNaN Float Round reutrn qNan when input is Nan FMaxMin return qNan with Nan inputs Change-Id: I7568be3d27d030e49f292a956b3084b54bdf8577 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2814725 Commit-Queue: Brice Dobry <brice.dobry@futurewei.com> Reviewed-by:
Brice Dobry <brice.dobry@futurewei.com> Reviewed-by:
Michael Stanton <mvstanton@chromium.org> Cr-Commit-Position: refs/heads/master@{#74006}
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- 12 Apr, 2021 1 commit
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Yahan Lu authored
Skip wasm/simd test for riscv64 Add buitin info when call a builtin. Port 064ca18c Change-Id: I1150de98a95231abf9d5def9e95ad38a8a42bbb3 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2814128Reviewed-by:
Brice Dobry <brice.dobry@futurewei.com> Commit-Queue: Brice Dobry <brice.dobry@futurewei.com> Cr-Commit-Position: refs/heads/master@{#73908}
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