[riscv64] Implement VSADDU

Change-Id: Ifa2236b650f78ad851930e69e0387d8952f197c1
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3178142
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Brice Dobry <brice.dobry@futurewei.com>
Cr-Commit-Position: refs/heads/main@{#77072}

src/codegen/riscv64/assembler-riscv64.cc

@@ -2569,9 +2569,9 @@ DEFINE_OPIVX(vsub, VSUB_FUNCT6)
 DEFINE_OPIVX(vsadd, VSADD_FUNCT6)
 DEFINE_OPIVV(vsadd, VSADD_FUNCT6)
 DEFINE_OPIVI(vsadd, VSADD_FUNCT6)
-DEFINE_OPIVX(vsaddu, VSADD_FUNCT6)
-DEFINE_OPIVV(vsaddu, VSADD_FUNCT6)
-DEFINE_OPIVI(vsaddu, VSADD_FUNCT6)
+DEFINE_OPIVX(vsaddu, VSADDU_FUNCT6)
+DEFINE_OPIVV(vsaddu, VSADDU_FUNCT6)
+DEFINE_OPIVI(vsaddu, VSADDU_FUNCT6)
 DEFINE_OPIVX(vssub, VSSUB_FUNCT6)
 DEFINE_OPIVV(vssub, VSSUB_FUNCT6)
 DEFINE_OPIVX(vssubu, VSSUBU_FUNCT6)

src/codegen/riscv64/assembler-riscv64.h

@@ -790,8 +790,8 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
   DEFINE_OPIVV(vsadd, VSADD_FUNCT6)
   DEFINE_OPIVI(vsadd, VSADD_FUNCT6)
   DEFINE_OPIVX(vsaddu, VSADD_FUNCT6)
-  DEFINE_OPIVV(vsaddu, VSADD_FUNCT6)
-  DEFINE_OPIVI(vsaddu, VSADD_FUNCT6)
+  DEFINE_OPIVV(vsaddu, VSADDU_FUNCT6)
+  DEFINE_OPIVI(vsaddu, VSADDU_FUNCT6)
   DEFINE_OPIVX(vssub, VSSUB_FUNCT6)
   DEFINE_OPIVV(vssub, VSSUB_FUNCT6)
   DEFINE_OPIVX(vssubu, VSSUBU_FUNCT6)

src/diagnostics/riscv64/disasm-riscv64.cc

@@ -1914,6 +1914,9 @@ void Decoder::DecodeRvvIVV(Instruction* instr) {
     case RO_V_VSADD_VV:
       Format(instr, "vsadd.vv  'vd, 'vs2, 'vs1'vm");
       break;
+    case RO_V_VSADDU_VV:
+      Format(instr, "vsaddu.vv 'vd, 'vs2, 'vs1'vm");
+      break;
     case RO_V_VSUB_VV:
       Format(instr, "vsub.vv   'vd, 'vs2, 'vs1'vm");
       break;
@@ -1998,6 +2001,9 @@ void Decoder::DecodeRvvIVI(Instruction* instr) {
     case RO_V_VSADD_VI:
       Format(instr, "vsadd.vi  'vd, 'vs2, 'simm5'vm");
       break;
+    case RO_V_VSADDU_VI:
+      Format(instr, "vsaddu.vi 'vd, 'vs2, 'simm5'vm");
+      break;
     case RO_V_VRSUB_VI:
       Format(instr, "vrsub.vi  'vd, 'vs2, 'simm5'vm");
       break;
@@ -2076,6 +2082,9 @@ void Decoder::DecodeRvvIVX(Instruction* instr) {
     case RO_V_VSADD_VX:
       Format(instr, "vsadd.vx  'vd, 'vs2, 'rs1'vm");
       break;
+    case RO_V_VSADDU_VX:
+      Format(instr, "vsaddu.vx 'vd, 'vs2, 'rs1'vm");
+      break;
     case RO_V_VSUB_VX:
       Format(instr, "vsub.vx   'vd, 'vs2, 'rs1'vm");
       break;

src/execution/riscv64/simulator-riscv64.cc

@@ -4316,6 +4316,12 @@ void Simulator::DecodeRvvIVV() {
       RVV_VI_LOOP_END
       break;
     }
+    case RO_V_VSADDU_VV:
+      RVV_VI_VV_ULOOP({
+        vd = vs2 + vs1;
+        vd |= -(vd < vs2);
+      })
+      break;
     case RO_V_VSUB_VV: {
       RVV_VI_VV_LOOP({ vd = vs2 - vs1; })
       break;
@@ -4543,6 +4549,13 @@ void Simulator::DecodeRvvIVI() {
       RVV_VI_LOOP_END
       break;
     }
+    case RO_V_VSADDU_VI:{
+      RVV_VI_VI_ULOOP({
+        vd = vs2 + uimm5;
+        vd |= -(vd < vs2);
+      })
+      break;
+    }
     case RO_V_VRSUB_VI: {
       RVV_VI_VI_LOOP({ vd = vs2 - simm5; })
       break;
@@ -4681,6 +4694,13 @@ void Simulator::DecodeRvvIVX() {
       RVV_VI_LOOP_END
       break;
     }
+    case RO_V_VSADDU_VX: {
+      RVV_VI_VX_ULOOP({
+        vd = vs2 + rs1;
+        vd |= -(vd < vs2);
+      })
+      break;
+    }
     case RO_V_VSUB_VX: {
       RVV_VI_VX_LOOP({ vd = vs2 - rs1; })
       break;