Commit 080bc4de authored by Lu Yahan's avatar Lu Yahan Committed by V8 LUCI CQ

[riscv64] Fix unreachable break

This is causing a warning on newer build configs (crrev.com/c/3117087)

Change-Id: I8cf7644861c27b9959283510163ecf8acdb6bdc8
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3124174
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: 's avatarJi Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#76523}
parent c9261f6a
......@@ -377,7 +377,7 @@ int Assembler::target_at(int pos, bool is_internal) {
} else {
return pos + imm13;
}
} break;
}
case JAL: {
int32_t imm21 = JumpOffset(instr);
if (imm21 == kEndOfJumpChain) {
......@@ -386,7 +386,7 @@ int Assembler::target_at(int pos, bool is_internal) {
} else {
return pos + imm21;
}
} break;
}
case JALR: {
int32_t imm12 = instr >> 20;
if (imm12 == kEndOfJumpChain) {
......@@ -395,7 +395,7 @@ int Assembler::target_at(int pos, bool is_internal) {
} else {
return pos + imm12;
}
} break;
}
case LUI: {
Address pc = reinterpret_cast<Address>(buffer_start_ + pos);
pc = target_address_at(pc);
......@@ -409,7 +409,7 @@ int Assembler::target_at(int pos, bool is_internal) {
DCHECK(pos > delta);
return pos - delta;
}
} break;
}
case AUIPC: {
Instr instr_auipc = instr;
Instr instr_I = instr_at(pos + 4);
......@@ -417,18 +417,18 @@ int Assembler::target_at(int pos, bool is_internal) {
int32_t offset = BrachlongOffset(instr_auipc, instr_I);
if (offset == kEndOfJumpChain) return kEndOfChain;
return offset + pos;
} break;
}
case RO_C_J: {
int32_t offset = instruction->RvcImm11CJValue();
if (offset == kEndOfJumpChain) return kEndOfChain;
return offset + pos;
} break;
}
case RO_C_BNEZ:
case RO_C_BEQZ: {
int32_t offset = instruction->RvcImm8BValue();
if (offset == kEndOfJumpChain) return kEndOfChain;
return pos + offset;
} break;
}
default: {
if (instr == kEndOfJumpChain) {
return kEndOfChain;
......@@ -437,7 +437,7 @@ int Assembler::target_at(int pos, bool is_internal) {
((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14;
return (imm18 + pos);
}
} break;
}
}
}
......@@ -2766,7 +2766,6 @@ int Assembler::RelocateInternalReference(RelocInfo::Mode rmode, Address pc,
return 8; // Number of instructions patched.
} else {
UNIMPLEMENTED();
return 1;
}
}
......
......@@ -2452,7 +2452,6 @@ void TurboAssembler::CompareI(Register rd, Register rs, const Operand& rt,
break;
case cc_always:
UNREACHABLE();
break;
default:
UNREACHABLE();
}
......@@ -3018,7 +3017,6 @@ bool TurboAssembler::BranchShortCheck(int32_t offset, Label* L, Condition cond,
DCHECK_EQ(offset, 0);
return BranchShortHelper(0, L, cond, rs, rt);
}
return false;
}
void TurboAssembler::BranchShort(int32_t offset, Condition cond, Register rs,
......@@ -3134,7 +3132,6 @@ bool TurboAssembler::BranchAndLinkShortCheck(int32_t offset, Label* L,
DCHECK_EQ(offset, 0);
return BranchAndLinkShortHelper(0, L, cond, rs, rt);
}
return false;
}
void TurboAssembler::LoadFromConstantsTable(Register destination,
......
......@@ -106,7 +106,6 @@ class RiscvOperandConverter final : public InstructionOperandConverter {
constant.ToDelayedStringConstant());
case Constant::kRpoNumber:
UNREACHABLE(); // TODO(titzer): RPO immediates
break;
}
UNREACHABLE();
}
......@@ -1919,7 +1918,6 @@ void AssembleBranchToLabels(CodeGenerator* gen, TurboAssembler* tasm,
break;
default:
UNSUPPORTED_COND(instr->arch_opcode(), condition);
break;
}
} else if (instr->arch_opcode() == kRiscvMulOvf32) {
// Overflow occurs if overflow register is not zero
......@@ -1932,7 +1930,6 @@ void AssembleBranchToLabels(CodeGenerator* gen, TurboAssembler* tasm,
break;
default:
UNSUPPORTED_COND(kRiscvMulOvf32, condition);
break;
}
} else if (instr->arch_opcode() == kRiscvCmp) {
cc = FlagsConditionToConditionCmp(condition);
......@@ -2597,7 +2594,6 @@ void CodeGenerator::AssembleMove(InstructionOperand* source,
}
case Constant::kRpoNumber:
UNREACHABLE(); // TODO(titzer): loading RPO numbers
break;
}
if (destination->IsStackSlot()) __ Sd(dst, g.ToMemOperand(destination));
} else if (src.type() == Constant::kFloat32) {
......
......@@ -563,7 +563,6 @@ void InstructionSelector::VisitStore(Node* node) {
break;
#else
UNREACHABLE();
break;
#endif
case MachineRepresentation::kMapWord: // Fall through.
case MachineRepresentation::kNone:
......
......@@ -1882,7 +1882,7 @@ const char* NameConverter::NameOfXMMRegister(int reg) const {
const char* NameConverter::NameOfByteCPURegister(int reg) const {
UNREACHABLE(); // RISC-V does not have the concept of a byte register.
return "nobytereg";
//return "nobytereg";
}
const char* NameConverter::NameInCode(byte* addr) const {
......
......@@ -172,7 +172,6 @@ bool RiscvDebugger::GetValue(const char* desc, int64_t* value) {
} else {
return SScanF(desc, "%" SCNu64, reinterpret_cast<uint64_t*>(value)) == 1;
}
return false;
}
#define REG_INFO(name) \
......@@ -1424,7 +1423,6 @@ void Simulator::SoftwareInterrupt() {
break;
default:
UNREACHABLE();
break;
}
}
switch (redirection->type()) {
......@@ -1459,7 +1457,6 @@ void Simulator::SoftwareInterrupt() {
}
default:
UNREACHABLE();
break;
}
if (::v8::internal::FLAG_trace_sim) {
switch (redirection->type()) {
......@@ -1473,7 +1470,6 @@ void Simulator::SoftwareInterrupt() {
break;
default:
UNREACHABLE();
break;
}
}
} else if (redirection->type() == ExternalReference::DIRECT_API_CALL) {
......
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