[riscv64] Add tests for RVV VI VF instructions
Implement `LiftoffAssembler::emit_i16x8_sconvert_i32x4` for riscv. Add tests for rvv integer and floating-point instructions. Add simulator support for rvv instructions, e.g. `vfmadd`, `vnclip`. Fixed order of operands for `vfdiv.vv`. Bug: v8:11976 Change-Id: I0691ac66771468533c5994be1fc8a86b09d3c738 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3225319Reviewed-by:Yahan Lu <yahan@iscas.ac.cn> Reviewed-by:
Michael Lippautz <mlippautz@chromium.org> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#77595}
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