Commit 899b5443 authored by Lu Yahan's avatar Lu Yahan Committed by V8 LUCI CQ

[riscv6] Add check into vrgather

vragther require that the destination vector register group cannot overlap with the source vector
register groups, otherwise an illegal instruction exception is raised.

Change-Id: I6d23ea80edc4a80be961531ded855ff372ca0da0
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3161777
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: 's avatarJi Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#76895}
parent 36e73519
......@@ -2506,6 +2506,25 @@ void Assembler::vmadc_vi(VRegister vd, uint8_t imm5, VRegister vs2) {
GenInstrV(VMADC_FUNCT6, vd, imm5, vs2, Mask);
}
void Assembler::vrgather_vv(VRegister vd, VRegister vs2, VRegister vs1,
MaskType mask) {
DCHECK_NE(vd, vs1);
DCHECK_NE(vd, vs2);
GenInstrV(VRGATHER_FUNCT6, OP_IVV, vd, vs1, vs2, mask);
}
void Assembler::vrgather_vi(VRegister vd, VRegister vs2, int8_t imm5,
MaskType mask) {
DCHECK_NE(vd, vs2);
GenInstrV(VRGATHER_FUNCT6, vd, imm5, vs2, mask);
}
void Assembler::vrgather_vx(VRegister vd, VRegister vs2, Register rs1,
MaskType mask) {
DCHECK_NE(vd, vs2);
GenInstrV(VRGATHER_FUNCT6, OP_IVX, vd, rs1, vs2, mask);
}
#define DEFINE_OPIVV(name, funct6) \
void Assembler::name##_vv(VRegister vd, VRegister vs2, VRegister vs1, \
MaskType mask) { \
......@@ -2576,9 +2595,6 @@ DEFINE_OPIVI(vor, VOR_FUNCT6)
DEFINE_OPIVV(vxor, VXOR_FUNCT6)
DEFINE_OPIVX(vxor, VXOR_FUNCT6)
DEFINE_OPIVI(vxor, VXOR_FUNCT6)
DEFINE_OPIVV(vrgather, VRGATHER_FUNCT6)
DEFINE_OPIVX(vrgather, VRGATHER_FUNCT6)
DEFINE_OPIVI(vrgather, VRGATHER_FUNCT6)
DEFINE_OPIVX(vslidedown, VSLIDEDOWN_FUNCT6)
DEFINE_OPIVI(vslidedown, VSLIDEDOWN_FUNCT6)
......
......@@ -4459,6 +4459,8 @@ void Simulator::DecodeRvvIVV() {
}
case RO_V_VRGATHER_VV: {
RVV_VI_GENERAL_LOOP_BASE
CHECK_NE(rvv_vs1_reg(), rvv_vd_reg());
CHECK_NE(rvv_vs2_reg(), rvv_vd_reg());
switch (rvv_vsew()) {
case E8: {
auto vs1 = Rvvelt<uint8_t>(rvv_vs1_reg(), i);
......
......@@ -1718,17 +1718,21 @@ void LiftoffAssembler::emit_i8x16_shuffle(LiftoffRegister dst,
vmerge_vx(kSimd128ScratchReg, kScratchReg, kSimd128ScratchReg);
VU.set(kScratchReg, E8, m1);
VRegister temp =
GetUnusedRegister(kFpReg, LiftoffRegList::ForRegs(lhs, rhs)).fp().toV();
if (dst_v == lhs_v) {
vmv_vv(kSimd128ScratchReg2, lhs_v);
lhs_v = kSimd128ScratchReg2;
vmv_vv(temp, lhs_v);
lhs_v = temp;
} else if (dst_v == rhs_v) {
vmv_vv(kSimd128ScratchReg2, rhs_v);
rhs_v = kSimd128ScratchReg2;
vmv_vv(temp, rhs_v);
rhs_v = temp;
}
vrgather_vv(dst_v, lhs_v, kSimd128ScratchReg);
vadd_vi(kSimd128ScratchReg, kSimd128ScratchReg, -16);
vrgather_vv(kSimd128ScratchReg, rhs_v, kSimd128ScratchReg);
vor_vv(dst_v, dst_v, kSimd128ScratchReg);
vadd_vi(kSimd128ScratchReg, kSimd128ScratchReg,
-16); // The indices in range [16, 31] select the i - 16-th element
// of rhs
vrgather_vv(kSimd128ScratchReg2, rhs_v, kSimd128ScratchReg);
vor_vv(dst_v, dst_v, kSimd128ScratchReg2);
}
void LiftoffAssembler::emit_i8x16_popcnt(LiftoffRegister dst,
......@@ -2520,7 +2524,7 @@ void LiftoffAssembler::emit_i64x2_add(LiftoffRegister dst, LiftoffRegister lhs,
void LiftoffAssembler::emit_i64x2_sub(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
VU.set(kScratchReg, E8, m1);
VU.set(kScratchReg, E64, m1);
vsub_vv(dst.fp().toV(), lhs.fp().toV(), rhs.fp().toV());
}
......
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