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    • Junliang Yan's avatar
      PPC/s390: [deoptimizer] Change deopt entries into builtins · 5d5ed19f
      Junliang Yan authored 
      Port 7f58ced7

Original Commit Message:

    While the overall goal of this commit is to change deoptimization
    entries into builtins, there are multiple related things happening:

    - Deoptimization entries, formerly stubs (i.e. Code objects generated
      at runtime, guaranteed to be immovable), have been converted into
      builtins. The major restriction is that we now need to preserve the
      kRootRegister, which was formerly used on most architectures to pass
      the deoptimization id. The solution differs based on platform.
    - Renamed DEOPT_ENTRIES_OR_FOR_TESTING code kind to FOR_TESTING.
    - Removed heap/ support for immovable Code generation.
    - Removed the DeserializerData class (no longer needed).
    - arm64: to preserve 4-byte deopt exits, introduced a new optimization
      in which the final jump to the deoptimization entry is generated
      once per Code object, and deopt exits can continue to emit a
      near-call.
    - arm,ia32,x64: change to fixed-size deopt exits. This reduces exit
      sizes by 4/8, 5, and 5 bytes, respectively.

    On arm the deopt exit size is reduced from 12 (or 16) bytes to 8 bytes
    by using the same strategy as on arm64 (recalc deopt id from return
    address). Before:

     e300a002       movw r10, <id>
     e59fc024       ldr ip, [pc, <entry offset>]
     e12fff3c       blx ip

    After:

     e59acb35       ldr ip, [r10, <entry offset>]
     e12fff3c       blx ip

    On arm64 the deopt exit size remains 4 bytes (or 8 bytes in same cases
    with CFI). Additionally, up to 4 builtin jumps are emitted per Code
    object (max 32 bytes added overhead per Code object). Before:

     9401cdae       bl <entry offset>

    After:

     # eager deoptimization entry jump.
     f95b1f50       ldr x16, [x26, <eager entry offset>]
     d61f0200       br x16
     # lazy deoptimization entry jump.
     f95b2b50       ldr x16, [x26, <lazy entry offset>]
     d61f0200       br x16
     # the deopt exit.
     97fffffc       bl <eager deoptimization entry jump offset>

    On ia32 the deopt exit size is reduced from 10 to 5 bytes. Before:

     bb00000000     mov ebx,<id>
     e825f5372b     call <entry>

    After:

     e8ea2256ba     call <entry>

    On x64 the deopt exit size is reduced from 12 to 7 bytes. Before:

     49c7c511000000 REX.W movq r13,<id>
     e8ea2f0700     call <entry>

    After:

     41ff9560360000 call [r13+<entry offset>]

R=jgruber@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com, miladfar@ca.ibm.com
BUG=
LOG=N

Change-Id: I49e4c92759043e46beb3c76c97823285b16feeef
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2486225Reviewed-by: 's avatarMilad Fa <mfarazma@redhat.com>
Commit-Queue: Junliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/master@{#70637}
      5d5ed19f
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    • Milad Farazmand's avatar
      PPC/s390: [wasm-simd] Support returning Simd128 on caller's stack · 9b317d2d
      Milad Farazmand authored 
      Port 360c9294

Original Commit Message:

    In Liftoff, we were missing kS128 cases to load to/from stack.

    For the x64 and ARM64 instruction selector, the calculation of
    reverse_slot is incorrect for 128-bit values:

    - reverse_slot += 2 (size of 128-bit values, 2 pointers)
    - this copies from slot -2 into register
    - but the value starts at slot -1, it occupies slots -1 and -2
    - we end up copying slot -2 (most significant half) of the register, and
    also slot -3, which is where rsi was store (Wasm instance addr)
    - the test ends up with a different result every time

    The calculation of reverse_slot is changed to follow how ia32 and ARM
    does it, which is to start with

    - reverse_slot = 0
    - in the code-generator, add 1 to the slot
    - then after emitting Peek operation, reverse_slot += 2

    The fixes for x64 and ARM64 are in both instruction-selector and
    code-generator.

    ia32 and ARM didn't support writing kSimd128 values yet, it was only a
    missing check in code-generator, so add that in.

    For ARM, the codegen is more involved, vld1 does not support addressing
    with an offset, so we have to do the addition into a scratch register.

    Also adding a test for returning multiple v128. V128 is not exposed to
    JavaScript, so we use a Wasm function call, and then an involved chain
    of extract lanes, returning 6 i32 which we verify the values of. It
    extracts the first and last lane of the i32x4 value in order to catch
    bugs where we write or read to a wrong stack slot (off by 1).

    The simd-scalar-lowering for kCall was only handling single s128 return,
    we adopt the way i64-lowering handles kCall, so that is can now handle
    any kinds of calls with s128 in the descriptor.

R=zhin@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com
BUG=
LOG=N

Change-Id: I1ad9595d7820f04687c9d79941ad04c6eb207897
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2363118Reviewed-by: 's avatarJunliang Yan <jyan@ca.ibm.com>
Reviewed-by: 's avatarZhi An Ng <zhin@chromium.org>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#69461}
      9b317d2d
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