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Commit 5f6124f9 authored by Milad Fa's avatar Milad Fa Committed by Commit Bot
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s390: [wasm-simd] Remove some I64x2 instructions not in proposal 

Port 2c38a477

Original Commit Message:

    These instructions are not in the proposal, and will be unlikely to be
    requested (poor performance, insufficient use cases). As we get more
    instruction suggestions, these are sitting around on useful opcodes and
    we have to play musical chairs every time we prototype a new
    instruction.

R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com
BUG=
LOG=N

Change-Id: Ia926a4b01ed6bc9b362adce68b9301e3fc86d942
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2466625Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#70484}
parent 3593ee83
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src/compiler/backend/s390/code-generator-s390.cc
View file @ 5f6124f9
......@@ -3420,24 +3420,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Condition(3));
break;
}
case kS390_I64x2MinS: {
__ vmn(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(3));
break;
}
case kS390_I32x4MinS: {
__ vmn(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_I64x2MinU: {
__ vmnl(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(3));
break;
}
case kS390_I32x4MinU: {
__ vmnl(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
......@@ -3468,24 +3456,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Condition(0));
break;
}
case kS390_I64x2MaxS: {
__ vmx(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(3));
break;
}
case kS390_I32x4MaxS: {
__ vmx(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_I64x2MaxU: {
__ vmxl(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(3));
break;
}
case kS390_I32x4MaxU: {
__ vmxl(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
......@@ -3550,14 +3526,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Condition(0), Condition(0), Condition(2));
break;
}
case kS390_I64x2Ne: {
__ vceq(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(3));
__ vno(i.OutputSimd128Register(), i.OutputSimd128Register(),
i.OutputSimd128Register(), Condition(0), Condition(0),
Condition(3));
break;
}
case kS390_I32x4Ne: {
__ vceq(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(2));
......@@ -3594,25 +3562,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Condition(2));
break;
}
case kS390_I64x2GtS: {
__ vch(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(3));
break;
}
case kS390_I32x4GtS: {
__ vch(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(2));
break;
}
case kS390_I64x2GeS: {
__ vceq(kScratchDoubleReg, i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(3));
__ vch(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(3));
__ vo(i.OutputSimd128Register(), i.OutputSimd128Register(),
kScratchDoubleReg, Condition(0), Condition(0), Condition(3));
break;
}
case kS390_I32x4GeS: {
__ vceq(kScratchDoubleReg, i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(2));
......@@ -3622,25 +3576,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
kScratchDoubleReg, Condition(0), Condition(0), Condition(2));
break;
}
case kS390_I64x2GtU: {
__ vchl(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(3));
break;
}
case kS390_I32x4GtU: {
__ vchl(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(2));
break;
}
case kS390_I64x2GeU: {
__ vceq(kScratchDoubleReg, i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(3));
__ vchl(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(3));
__ vo(i.OutputSimd128Register(), i.OutputSimd128Register(),
kScratchDoubleReg, Condition(0), Condition(0), Condition(3));
break;
}
case kS390_I32x4GeU: {
__ vceq(kScratchDoubleReg, i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(2));
......@@ -3865,7 +3805,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
// vector boolean unops
case kS390_V64x2AnyTrue:
case kS390_V32x4AnyTrue:
case kS390_V16x8AnyTrue:
case kS390_V8x16AnyTrue: {
......@@ -3891,10 +3830,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vtm(kScratchDoubleReg, kScratchDoubleReg, Condition(0), Condition(0), \
Condition(0)); \
__ locgr(Condition(8), dst, temp);
case kS390_V64x2AllTrue: {
SIMD_ALL_TRUE(3)
break;
}
case kS390_V32x4AllTrue: {
SIMD_ALL_TRUE(2)
break;
......
src/compiler/backend/s390/instruction-codes-s390.h
View file @ 5f6124f9
......@@ -261,15 +261,6 @@ namespace compiler {
V(S390_I64x2ReplaceLane) \
V(S390_I64x2ExtractLane) \
V(S390_I64x2Eq) \
V(S390_I64x2Ne) \
V(S390_I64x2GtS) \
V(S390_I64x2GeS) \
V(S390_I64x2GtU) \
V(S390_I64x2GeU) \
V(S390_I64x2MinS) \
V(S390_I64x2MinU) \
V(S390_I64x2MaxS) \
V(S390_I64x2MaxU) \
V(S390_I32x4Splat) \
V(S390_I32x4ExtractLane) \
V(S390_I32x4ReplaceLane) \
......@@ -367,11 +358,9 @@ namespace compiler {
V(S390_I8x16BitMask) \
V(S390_I8x16Shuffle) \
V(S390_I8x16Swizzle) \
V(S390_V64x2AnyTrue) \
V(S390_V32x4AnyTrue) \
V(S390_V16x8AnyTrue) \
V(S390_V8x16AnyTrue) \
V(S390_V64x2AllTrue) \
V(S390_V32x4AllTrue) \
V(S390_V16x8AllTrue) \
V(S390_V8x16AllTrue) \
......
src/compiler/backend/s390/instruction-scheduler-s390.cc
View file @ 5f6124f9
......@@ -207,15 +207,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kS390_I64x2ReplaceLane:
case kS390_I64x2ExtractLane:
case kS390_I64x2Eq:
case kS390_I64x2Ne:
case kS390_I64x2GtS:
case kS390_I64x2GeS:
case kS390_I64x2GtU:
case kS390_I64x2GeU:
case kS390_I64x2MinS:
case kS390_I64x2MinU:
case kS390_I64x2MaxS:
case kS390_I64x2MaxU:
case kS390_I32x4Splat:
case kS390_I32x4ExtractLane:
case kS390_I32x4ReplaceLane:
......@@ -313,11 +304,9 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kS390_I8x16BitMask:
case kS390_I8x16Shuffle:
case kS390_I8x16Swizzle:
case kS390_V64x2AnyTrue:
case kS390_V32x4AnyTrue:
case kS390_V16x8AnyTrue:
case kS390_V8x16AnyTrue:
case kS390_V64x2AllTrue:
case kS390_V32x4AllTrue:
case kS390_V16x8AllTrue:
case kS390_V8x16AllTrue:
......
src/compiler/backend/s390/instruction-selector-s390.cc
View file @ 5f6124f9
......@@ -2559,15 +2559,6 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
V(I64x2Sub) \
V(I64x2Mul) \
V(I64x2Eq) \
V(I64x2Ne) \
V(I64x2GtS) \
V(I64x2GeS) \
V(I64x2GtU) \
V(I64x2GeU) \
V(I64x2MinS) \
V(I64x2MinU) \
V(I64x2MaxS) \
V(I64x2MaxU) \
V(I32x4Add) \
V(I32x4AddHoriz) \
V(I32x4Sub) \
......@@ -2677,11 +2668,9 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
V(I8x16ShrU)
#define SIMD_BOOL_LIST(V) \
V(V64x2AnyTrue) \
V(V32x4AnyTrue) \
V(V16x8AnyTrue) \
V(V8x16AnyTrue) \
V(V64x2AllTrue) \
V(V32x4AllTrue) \
V(V16x8AllTrue) \
V(V8x16AllTrue)
......
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