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Commit 2c38a477 authored by Ng Zhi An's avatar Ng Zhi An Committed by Commit Bot
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[wasm-simd] Remove some I64x2 instructions not in proposal 

These instructions are not in the proposal, and will be unlikely to be
requested (poor performance, insufficient use cases). As we get more
instruction suggestions, these are sitting around on useful opcodes and
we have to play musical chairs every time we prototype a new
instruction.

Bug: v8:10933
Change-Id: Ic7ce4e514c343d821f76b8c071e41f9bddfbd1ce
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2457669Reviewed-by: 's avatarBill Budge <bbudge@chromium.org>
Reviewed-by: 's avatarGeorg Neis <neis@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#70455}
parent 5e5eaf79
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Showing with 2 additions and 502 deletions
src/compiler/backend/arm64/code-generator-arm64.cc
View file @ 2c38a477
......@@ -2146,21 +2146,10 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
SIMD_BINOP_CASE(kArm64I64x2Eq, Cmeq, 2D);
case kArm64I64x2Ne: {
VRegister dst = i.OutputSimd128Register().V2D();
__ Cmeq(dst, i.InputSimd128Register(0).V2D(),
i.InputSimd128Register(1).V2D());
__ Mvn(dst, dst);
break;
}
SIMD_BINOP_CASE(kArm64I64x2GtS, Cmgt, 2D);
SIMD_BINOP_CASE(kArm64I64x2GeS, Cmge, 2D);
case kArm64I64x2ShrU: {
ASSEMBLE_SIMD_SHIFT_RIGHT(Ushr, 6, V2D, Ushl, X);
break;
}
SIMD_BINOP_CASE(kArm64I64x2GtU, Cmhi, 2D);
SIMD_BINOP_CASE(kArm64I64x2GeU, Cmhs, 2D);
case kArm64I32x4Splat: {
__ Dup(i.OutputSimd128Register().V4S(), i.InputRegister32(0));
break;
......@@ -2586,17 +2575,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
SIMD_UNOP_CASE(kArm64S8x8Reverse, Rev64, 16B);
SIMD_UNOP_CASE(kArm64S8x4Reverse, Rev32, 16B);
SIMD_UNOP_CASE(kArm64S8x2Reverse, Rev16, 16B);
case kArm64V64x2AllTrue: {
UseScratchRegisterScope scope(tasm());
VRegister temp1 = scope.AcquireV(kFormat2D);
VRegister temp2 = scope.AcquireV(kFormatS);
__ Cmeq(temp1, i.InputSimd128Register(0).V2D(), 0);
__ Umaxv(temp2, temp1.V4S());
__ Umov(i.OutputRegister32(), temp2, 0);
__ Add(i.OutputRegister32(), i.OutputRegister32(), 1);
break;
}
case kArm64LoadSplat: {
VectorFormat f = VectorFormatFillQ(MiscField::decode(opcode));
__ ld1r(i.OutputSimd128Register().Format(f), i.MemoryOperand(0));
......
src/compiler/backend/arm64/instruction-codes-arm64.h
View file @ 2c38a477
......@@ -227,12 +227,7 @@ namespace compiler {
V(Arm64I64x2Sub) \
V(Arm64I64x2Mul) \
V(Arm64I64x2Eq) \
V(Arm64I64x2Ne) \
V(Arm64I64x2GtS) \
V(Arm64I64x2GeS) \
V(Arm64I64x2ShrU) \
V(Arm64I64x2GtU) \
V(Arm64I64x2GeU) \
V(Arm64I32x4Splat) \
V(Arm64I32x4ExtractLane) \
V(Arm64I32x4ReplaceLane) \
......@@ -365,7 +360,6 @@ namespace compiler {
V(Arm64S8x4Reverse) \
V(Arm64S8x2Reverse) \
V(Arm64V128AnyTrue) \
V(Arm64V64x2AllTrue) \
V(Arm64V32x4AllTrue) \
V(Arm64V16x8AllTrue) \
V(Arm64V8x16AllTrue) \
......
src/compiler/backend/arm64/instruction-scheduler-arm64.cc
View file @ 2c38a477
......@@ -193,12 +193,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArm64I64x2Sub:
case kArm64I64x2Mul:
case kArm64I64x2Eq:
case kArm64I64x2Ne:
case kArm64I64x2GtS:
case kArm64I64x2GeS:
case kArm64I64x2ShrU:
case kArm64I64x2GtU:
case kArm64I64x2GeU:
case kArm64I32x4Splat:
case kArm64I32x4ExtractLane:
case kArm64I32x4ReplaceLane:
......@@ -335,7 +330,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArm64S8x4Reverse:
case kArm64S8x2Reverse:
case kArm64V128AnyTrue:
case kArm64V64x2AllTrue:
case kArm64V32x4AllTrue:
case kArm64V16x8AllTrue:
case kArm64V8x16AllTrue:
......
src/compiler/backend/arm64/instruction-selector-arm64.cc
View file @ 2c38a477
......@@ -3238,8 +3238,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16Neg, kArm64I8x16Neg) \
V(I8x16Abs, kArm64I8x16Abs) \
V(S128Not, kArm64S128Not) \
V(V64x2AnyTrue, kArm64V128AnyTrue) \
V(V64x2AllTrue, kArm64V64x2AllTrue) \
V(V32x4AnyTrue, kArm64V128AnyTrue) \
V(V32x4AllTrue, kArm64V32x4AllTrue) \
V(V16x8AnyTrue, kArm64V128AnyTrue) \
......@@ -3286,11 +3284,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I64x2Add, kArm64I64x2Add) \
V(I64x2Sub, kArm64I64x2Sub) \
V(I64x2Eq, kArm64I64x2Eq) \
V(I64x2Ne, kArm64I64x2Ne) \
V(I64x2GtS, kArm64I64x2GtS) \
V(I64x2GeS, kArm64I64x2GeS) \
V(I64x2GtU, kArm64I64x2GtU) \
V(I64x2GeU, kArm64I64x2GeU) \
V(I32x4AddHoriz, kArm64I32x4AddHoriz) \
V(I32x4Mul, kArm64I32x4Mul) \
V(I32x4MinS, kArm64I32x4MinS) \
......
src/compiler/backend/instruction-selector.cc
View file @ 2c38a477
......@@ -2000,28 +2000,10 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsSimd128(node), VisitI64x2Sub(node);
case IrOpcode::kI64x2Mul:
return MarkAsSimd128(node), VisitI64x2Mul(node);
case IrOpcode::kI64x2MinS:
return MarkAsSimd128(node), VisitI64x2MinS(node);
case IrOpcode::kI64x2MaxS:
return MarkAsSimd128(node), VisitI64x2MaxS(node);
case IrOpcode::kI64x2Eq:
return MarkAsSimd128(node), VisitI64x2Eq(node);
case IrOpcode::kI64x2Ne:
return MarkAsSimd128(node), VisitI64x2Ne(node);
case IrOpcode::kI64x2GtS:
return MarkAsSimd128(node), VisitI64x2GtS(node);
case IrOpcode::kI64x2GeS:
return MarkAsSimd128(node), VisitI64x2GeS(node);
case IrOpcode::kI64x2ShrU:
return MarkAsSimd128(node), VisitI64x2ShrU(node);
case IrOpcode::kI64x2MinU:
return MarkAsSimd128(node), VisitI64x2MinU(node);
case IrOpcode::kI64x2MaxU:
return MarkAsSimd128(node), VisitI64x2MaxU(node);
case IrOpcode::kI64x2GtU:
return MarkAsSimd128(node), VisitI64x2GtU(node);
case IrOpcode::kI64x2GeU:
return MarkAsSimd128(node), VisitI64x2GeU(node);
case IrOpcode::kI32x4Splat:
return MarkAsSimd128(node), VisitI32x4Splat(node);
case IrOpcode::kI32x4ExtractLane:
......@@ -2234,10 +2216,6 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsSimd128(node), VisitI8x16Swizzle(node);
case IrOpcode::kI8x16Shuffle:
return MarkAsSimd128(node), VisitI8x16Shuffle(node);
case IrOpcode::kV64x2AnyTrue:
return MarkAsWord32(node), VisitV64x2AnyTrue(node);
case IrOpcode::kV64x2AllTrue:
return MarkAsWord32(node), VisitV64x2AllTrue(node);
case IrOpcode::kV32x4AnyTrue:
return MarkAsWord32(node), VisitV32x4AnyTrue(node);
case IrOpcode::kV32x4AllTrue:
......@@ -2679,22 +2657,11 @@ void InstructionSelector::VisitI64x2ExtractLane(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2ReplaceLane(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI64x2Eq(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2Ne(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2GtS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2GeS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2GtU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2GeU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitV64x2AnyTrue(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitV64x2AllTrue(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF64x2Qfma(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF64x2Qfms(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Qfma(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Qfms(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM64
void InstructionSelector::VisitI64x2MinS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2MaxS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2MinU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2MaxU(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_S390X
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM64 && \
......
src/compiler/backend/x64/code-generator-x64.cc
View file @ 2c38a477
......@@ -2787,179 +2787,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ Paddq(left, tmp2); // left == dst
break;
}
case kX64I64x2MinS: {
if (CpuFeatures::IsSupported(SSE4_2)) {
CpuFeatureScope sse_scope_4_2(tasm(), SSE4_2);
XMMRegister dst = i.OutputSimd128Register();
XMMRegister src0 = i.InputSimd128Register(0);
XMMRegister src1 = i.InputSimd128Register(1);
XMMRegister tmp = i.TempSimd128Register(0);
DCHECK_EQ(tmp, xmm0);
__ movaps(tmp, src1);
__ pcmpgtq(tmp, src0);
__ movaps(dst, src1);
__ blendvpd(dst, src0); // implicit use of xmm0 as mask
} else {
CpuFeatureScope sse_scope_4_1(tasm(), SSE4_1);
XMMRegister dst = i.OutputSimd128Register();
XMMRegister src = i.InputSimd128Register(1);
XMMRegister tmp = i.TempSimd128Register(0);
Register tmp1 = i.TempRegister(1);
Register tmp2 = i.TempRegister(2);
DCHECK_EQ(dst, i.InputSimd128Register(0));
// backup src since we cannot change it
__ movaps(tmp, src);
// compare the lower quardwords
__ movq(tmp1, dst);
__ movq(tmp2, tmp);
__ cmpq(tmp1, tmp2);
// tmp2 now has the min of lower quadwords
__ cmovq(less_equal, tmp2, tmp1);
// tmp1 now has the higher quadword
// must do this before movq, movq clears top quadword
__ pextrq(tmp1, dst, 1);
// save tmp2 into dst
__ movq(dst, tmp2);
// tmp2 now has the higher quadword
__ pextrq(tmp2, tmp, 1);
// compare higher quadwords
__ cmpq(tmp1, tmp2);
// tmp2 now has the min of higher quadwords
__ cmovq(less_equal, tmp2, tmp1);
__ movq(tmp, tmp2);
// dst = [tmp[0], dst[0]]
__ punpcklqdq(dst, tmp);
}
break;
}
case kX64I64x2MaxS: {
CpuFeatureScope sse_scope_4_2(tasm(), SSE4_2);
XMMRegister dst = i.OutputSimd128Register();
XMMRegister src = i.InputSimd128Register(1);
XMMRegister tmp = i.TempSimd128Register(0);
DCHECK_EQ(dst, i.InputSimd128Register(0));
DCHECK_EQ(tmp, xmm0);
__ movaps(tmp, src);
__ pcmpgtq(tmp, dst);
__ blendvpd(dst, src); // implicit use of xmm0 as mask
break;
}
case kX64I64x2Eq: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ Pcmpeqq(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64I64x2Ne: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
XMMRegister tmp = i.TempSimd128Register(0);
__ Pcmpeqq(i.OutputSimd128Register(), i.InputSimd128Register(1));
__ Pcmpeqq(tmp, tmp);
__ Pxor(i.OutputSimd128Register(), tmp);
break;
}
case kX64I64x2GtS: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ Pcmpgtq(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64I64x2GeS: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
XMMRegister dst = i.OutputSimd128Register();
XMMRegister src = i.InputSimd128Register(1);
XMMRegister tmp = i.TempSimd128Register(0);
__ Movaps(tmp, src);
__ Pcmpgtq(tmp, dst);
__ Pcmpeqd(dst, dst);
__ Pxor(dst, tmp);
break;
}
case kX64I64x2ShrU: {
// Take shift value modulo 2^6.
ASSEMBLE_SIMD_SHIFT(Psrlq, 6);
break;
}
case kX64I64x2MinU: {
CpuFeatureScope sse_scope_4_2(tasm(), SSE4_2);
CpuFeatureScope sse_scope_4_1(tasm(), SSE4_1);
XMMRegister dst = i.OutputSimd128Register();
XMMRegister src0 = i.InputSimd128Register(0);
XMMRegister src1 = i.InputSimd128Register(1);
XMMRegister tmp0 = i.TempSimd128Register(0);
XMMRegister tmp1 = i.TempSimd128Register(1);
DCHECK_EQ(tmp1, xmm0);
__ movaps(dst, src1);
__ movaps(tmp0, src0);
__ pcmpeqd(tmp1, tmp1);
__ psllq(tmp1, 63);
__ pxor(tmp0, tmp1);
__ pxor(tmp1, dst);
__ pcmpgtq(tmp1, tmp0);
__ blendvpd(dst, src0); // implicit use of xmm0 as mask
break;
}
case kX64I64x2MaxU: {
CpuFeatureScope sse_scope_4_2(tasm(), SSE4_2);
CpuFeatureScope sse_scope_4_1(tasm(), SSE4_1);
XMMRegister dst = i.OutputSimd128Register();
XMMRegister src = i.InputSimd128Register(1);
XMMRegister dst_tmp = i.TempSimd128Register(0);
XMMRegister tmp = i.TempSimd128Register(1);
DCHECK_EQ(dst, i.InputSimd128Register(0));
DCHECK_EQ(tmp, xmm0);
__ movaps(dst_tmp, dst);
__ pcmpeqd(tmp, tmp);
__ psllq(tmp, 63);
__ pxor(dst_tmp, tmp);
__ pxor(tmp, src);
__ pcmpgtq(tmp, dst_tmp);
__ blendvpd(dst, src); // implicit use of xmm0 as mask
break;
}
case kX64I64x2GtU: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
XMMRegister dst = i.OutputSimd128Register();
XMMRegister src = i.InputSimd128Register(1);
XMMRegister tmp = i.TempSimd128Register(0);
__ Pcmpeqd(kScratchDoubleReg, kScratchDoubleReg);
__ Psllq(kScratchDoubleReg, 63);
__ Movaps(tmp, src);
__ Pxor(tmp, kScratchDoubleReg);
__ Pxor(dst, kScratchDoubleReg);
__ Pcmpgtq(dst, tmp);
break;
}
case kX64I64x2GeU: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_2);
XMMRegister dst = i.OutputSimd128Register();
XMMRegister src = i.InputSimd128Register(1);
XMMRegister tmp = i.TempSimd128Register(0);
__ Pcmpeqd(kScratchDoubleReg, kScratchDoubleReg);
__ Psllq(kScratchDoubleReg, 63);
__ Movaps(tmp, src);
__ Pxor(dst, kScratchDoubleReg);
__ Pxor(tmp, kScratchDoubleReg);
__ Pcmpgtq(tmp, dst);
__ Pcmpeqd(dst, dst);
__ Pxor(dst, tmp);
break;
}
case kX64I32x4Splat: {
XMMRegister dst = i.OutputSimd128Register();
if (HasRegisterInput(instr, 0)) {
......@@ -4023,7 +3860,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ Por(dst, kScratchDoubleReg);
break;
}
case kX64V64x2AnyTrue:
case kX64V32x4AnyTrue:
case kX64V16x8AnyTrue:
case kX64V8x16AnyTrue: {
......@@ -4039,10 +3875,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
// comparison instruction used matters, e.g. given 0xff00, pcmpeqb returns
// 0x0011, pcmpeqw returns 0x0000, ptest will set ZF to 0 and 1
// respectively.
case kX64V64x2AllTrue: {
ASSEMBLE_SIMD_ALL_TRUE(Pcmpeqq);
break;
}
case kX64V32x4AllTrue: {
ASSEMBLE_SIMD_ALL_TRUE(Pcmpeqd);
break;
......
src/compiler/backend/x64/instruction-codes-x64.h
View file @ 2c38a477
......@@ -210,17 +210,8 @@ namespace compiler {
V(X64I64x2Add) \
V(X64I64x2Sub) \
V(X64I64x2Mul) \
V(X64I64x2MinS) \
V(X64I64x2MaxS) \
V(X64I64x2Eq) \
V(X64I64x2Ne) \
V(X64I64x2GtS) \
V(X64I64x2GeS) \
V(X64I64x2ShrU) \
V(X64I64x2MinU) \
V(X64I64x2MaxU) \
V(X64I64x2GtU) \
V(X64I64x2GeU) \
V(X64I32x4Splat) \
V(X64I32x4ExtractLane) \
V(X64I32x4ReplaceLane) \
......@@ -364,8 +355,6 @@ namespace compiler {
V(X64S8x8Reverse) \
V(X64S8x4Reverse) \
V(X64S8x2Reverse) \
V(X64V64x2AnyTrue) \
V(X64V64x2AllTrue) \
V(X64V32x4AnyTrue) \
V(X64V32x4AllTrue) \
V(X64V16x8AnyTrue) \
......
src/compiler/backend/x64/instruction-scheduler-x64.cc
View file @ 2c38a477
......@@ -182,17 +182,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kX64I64x2Add:
case kX64I64x2Sub:
case kX64I64x2Mul:
case kX64I64x2MinS:
case kX64I64x2MaxS:
case kX64I64x2Eq:
case kX64I64x2Ne:
case kX64I64x2GtS:
case kX64I64x2GeS:
case kX64I64x2ShrU:
case kX64I64x2MinU:
case kX64I64x2MaxU:
case kX64I64x2GtU:
case kX64I64x2GeU:
case kX64I32x4Splat:
case kX64I32x4ExtractLane:
case kX64I32x4ReplaceLane:
......@@ -297,8 +288,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kX64S128Zero:
case kX64S128AllOnes:
case kX64S128AndNot:
case kX64V64x2AnyTrue:
case kX64V64x2AllTrue:
case kX64V32x4AnyTrue:
case kX64V32x4AllTrue:
case kX64V16x8AnyTrue:
......
src/compiler/backend/x64/instruction-selector-x64.cc
View file @ 2c38a477
......@@ -2759,7 +2759,6 @@ VISIT_ATOMIC_BINOP(Xor)
V(I64x2Add) \
V(I64x2Sub) \
V(I64x2Eq) \
V(I64x2GtS) \
V(I32x4Add) \
V(I32x4AddHoriz) \
V(I32x4Sub) \
......@@ -2812,10 +2811,6 @@ VISIT_ATOMIC_BINOP(Xor)
V(S128Xor)
#define SIMD_BINOP_ONE_TEMP_LIST(V) \
V(I64x2Ne) \
V(I64x2GeS) \
V(I64x2GtU) \
V(I64x2GeU) \
V(I32x4Ne) \
V(I32x4GtU) \
V(I16x8Ne) \
......@@ -2865,13 +2860,11 @@ VISIT_ATOMIC_BINOP(Xor)
V(I8x16ShrU)
#define SIMD_ANYTRUE_LIST(V) \
V(V64x2AnyTrue) \
V(V32x4AnyTrue) \
V(V16x8AnyTrue) \
V(V8x16AnyTrue)
#define SIMD_ALLTRUE_LIST(V) \
V(V64x2AllTrue) \
V(V32x4AllTrue) \
V(V16x8AllTrue) \
V(V8x16AllTrue)
......@@ -3101,48 +3094,6 @@ void InstructionSelector::VisitI64x2Mul(Node* node) {
g.UseUniqueRegister(node->InputAt(1)), arraysize(temps), temps);
}
void InstructionSelector::VisitI64x2MinS(Node* node) {
X64OperandGenerator g(this);
if (this->IsSupported(SSE4_2)) {
InstructionOperand temps[] = {g.TempFpRegister(xmm0)};
Emit(kX64I64x2MinS, g.DefineAsRegister(node),
g.UseUniqueRegister(node->InputAt(0)),
g.UseUniqueRegister(node->InputAt(1)), arraysize(temps), temps);
} else {
InstructionOperand temps[] = {g.TempSimd128Register(), g.TempRegister(),
g.TempRegister()};
Emit(kX64I64x2MinS, g.DefineSameAsFirst(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)),
arraysize(temps), temps);
}
}
void InstructionSelector::VisitI64x2MaxS(Node* node) {
X64OperandGenerator g(this);
InstructionOperand temps[] = {g.TempFpRegister(xmm0)};
Emit(kX64I64x2MaxS, g.DefineSameAsFirst(node),
g.UseRegister(node->InputAt(0)), g.UseUniqueRegister(node->InputAt(1)),
arraysize(temps), temps);
}
void InstructionSelector::VisitI64x2MinU(Node* node) {
X64OperandGenerator g(this);
InstructionOperand temps[] = {g.TempSimd128Register(),
g.TempFpRegister(xmm0)};
Emit(kX64I64x2MinU, g.DefineAsRegister(node),
g.UseUniqueRegister(node->InputAt(0)),
g.UseUniqueRegister(node->InputAt(1)), arraysize(temps), temps);
}
void InstructionSelector::VisitI64x2MaxU(Node* node) {
X64OperandGenerator g(this);
InstructionOperand temps[] = {g.TempSimd128Register(),
g.TempFpRegister(xmm0)};
Emit(kX64I64x2MaxU, g.DefineSameAsFirst(node),
g.UseRegister(node->InputAt(0)), g.UseUniqueRegister(node->InputAt(1)),
arraysize(temps), temps);
}
void InstructionSelector::VisitI32x4SConvertF32x4(Node* node) {
X64OperandGenerator g(this);
InstructionOperand temps[] = {g.TempSimd128Register()};
......
src/compiler/machine-operator.cc
View file @ 2c38a477
......@@ -384,17 +384,8 @@ ShiftKind ShiftKindOf(Operator const* op) {
V(I64x2Add, Operator::kCommutative, 2, 0, 1) \
V(I64x2Sub, Operator::kNoProperties, 2, 0, 1) \
V(I64x2Mul, Operator::kCommutative, 2, 0, 1) \
V(I64x2MinS, Operator::kCommutative, 2, 0, 1) \
V(I64x2MaxS, Operator::kCommutative, 2, 0, 1) \
V(I64x2Eq, Operator::kCommutative, 2, 0, 1) \
V(I64x2Ne, Operator::kCommutative, 2, 0, 1) \
V(I64x2GtS, Operator::kNoProperties, 2, 0, 1) \
V(I64x2GeS, Operator::kNoProperties, 2, 0, 1) \
V(I64x2ShrU, Operator::kNoProperties, 2, 0, 1) \
V(I64x2MinU, Operator::kCommutative, 2, 0, 1) \
V(I64x2MaxU, Operator::kCommutative, 2, 0, 1) \
V(I64x2GtU, Operator::kNoProperties, 2, 0, 1) \
V(I64x2GeU, Operator::kNoProperties, 2, 0, 1) \
V(I32x4Splat, Operator::kNoProperties, 1, 0, 1) \
V(I32x4SConvertF32x4, Operator::kNoProperties, 1, 0, 1) \
V(I32x4SConvertI16x8Low, Operator::kNoProperties, 1, 0, 1) \
......@@ -492,8 +483,6 @@ ShiftKind ShiftKindOf(Operator const* op) {
V(S128Not, Operator::kNoProperties, 1, 0, 1) \
V(S128Select, Operator::kNoProperties, 3, 0, 1) \
V(S128AndNot, Operator::kNoProperties, 2, 0, 1) \
V(V64x2AnyTrue, Operator::kNoProperties, 1, 0, 1) \
V(V64x2AllTrue, Operator::kNoProperties, 1, 0, 1) \
V(V32x4AnyTrue, Operator::kNoProperties, 1, 0, 1) \
V(V32x4AllTrue, Operator::kNoProperties, 1, 0, 1) \
V(V16x8AnyTrue, Operator::kNoProperties, 1, 0, 1) \
......
src/compiler/machine-operator.h
View file @ 2c38a477
......@@ -646,17 +646,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* I64x2Add();
const Operator* I64x2Sub();
const Operator* I64x2Mul();
const Operator* I64x2MinS();
const Operator* I64x2MaxS();
const Operator* I64x2Eq();
const Operator* I64x2Ne();
const Operator* I64x2GtS();
const Operator* I64x2GeS();
const Operator* I64x2ShrU();
const Operator* I64x2MinU();
const Operator* I64x2MaxU();
const Operator* I64x2GtU();
const Operator* I64x2GeU();
const Operator* I32x4Splat();
const Operator* I32x4ExtractLane(int32_t);
......@@ -775,8 +766,6 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* I8x16Swizzle();
const Operator* I8x16Shuffle(const uint8_t shuffle[16]);
const Operator* V64x2AnyTrue();
const Operator* V64x2AllTrue();
const Operator* V32x4AnyTrue();
const Operator* V32x4AllTrue();
const Operator* V16x8AnyTrue();
......
src/compiler/opcodes.h
View file @ 2c38a477
......@@ -828,17 +828,8 @@
V(I64x2Add) \
V(I64x2Sub) \
V(I64x2Mul) \
V(I64x2MinS) \
V(I64x2MaxS) \
V(I64x2Eq) \
V(I64x2Ne) \
V(I64x2GtS) \
V(I64x2GeS) \
V(I64x2ShrU) \
V(I64x2MinU) \
V(I64x2MaxU) \
V(I64x2GtU) \
V(I64x2GeU) \
V(I32x4Splat) \
V(I32x4ExtractLane) \
V(I32x4ReplaceLane) \
......@@ -959,8 +950,6 @@
V(S128AndNot) \
V(I8x16Swizzle) \
V(I8x16Shuffle) \
V(V64x2AnyTrue) \
V(V64x2AllTrue) \
V(V32x4AnyTrue) \
V(V32x4AllTrue) \
V(V16x8AnyTrue) \
......
src/compiler/wasm-compiler.cc
View file @ 2c38a477
......@@ -4584,51 +4584,12 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode, Node* const* inputs) {
case wasm::kExprI64x2Mul:
return graph()->NewNode(mcgraph()->machine()->I64x2Mul(), inputs[0],
inputs[1]);
case wasm::kExprI64x2MinS:
return graph()->NewNode(mcgraph()->machine()->I64x2MinS(), inputs[0],
inputs[1]);
case wasm::kExprI64x2MaxS:
return graph()->NewNode(mcgraph()->machine()->I64x2MaxS(), inputs[0],
inputs[1]);
case wasm::kExprI64x2Eq:
return graph()->NewNode(mcgraph()->machine()->I64x2Eq(), inputs[0],
inputs[1]);
case wasm::kExprI64x2Ne:
return graph()->NewNode(mcgraph()->machine()->I64x2Ne(), inputs[0],
inputs[1]);
case wasm::kExprI64x2LtS:
return graph()->NewNode(mcgraph()->machine()->I64x2GtS(), inputs[1],
inputs[0]);
case wasm::kExprI64x2LeS:
return graph()->NewNode(mcgraph()->machine()->I64x2GeS(), inputs[1],
inputs[0]);
case wasm::kExprI64x2GtS:
return graph()->NewNode(mcgraph()->machine()->I64x2GtS(), inputs[0],
inputs[1]);
case wasm::kExprI64x2GeS:
return graph()->NewNode(mcgraph()->machine()->I64x2GeS(), inputs[0],
inputs[1]);
case wasm::kExprI64x2ShrU:
return graph()->NewNode(mcgraph()->machine()->I64x2ShrU(), inputs[0],
inputs[1]);
case wasm::kExprI64x2MinU:
return graph()->NewNode(mcgraph()->machine()->I64x2MinU(), inputs[0],
inputs[1]);
case wasm::kExprI64x2MaxU:
return graph()->NewNode(mcgraph()->machine()->I64x2MaxU(), inputs[0],
inputs[1]);
case wasm::kExprI64x2LtU:
return graph()->NewNode(mcgraph()->machine()->I64x2GtU(), inputs[1],
inputs[0]);
case wasm::kExprI64x2LeU:
return graph()->NewNode(mcgraph()->machine()->I64x2GeU(), inputs[1],
inputs[0]);
case wasm::kExprI64x2GtU:
return graph()->NewNode(mcgraph()->machine()->I64x2GtU(), inputs[0],
inputs[1]);
case wasm::kExprI64x2GeU:
return graph()->NewNode(mcgraph()->machine()->I64x2GeU(), inputs[0],
inputs[1]);
case wasm::kExprI32x4Splat:
return graph()->NewNode(mcgraph()->machine()->I32x4Splat(), inputs[0]);
case wasm::kExprI32x4SConvertF32x4:
......@@ -4934,10 +4895,6 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode, Node* const* inputs) {
case wasm::kExprS128AndNot:
return graph()->NewNode(mcgraph()->machine()->S128AndNot(), inputs[0],
inputs[1]);
case wasm::kExprV64x2AnyTrue:
return graph()->NewNode(mcgraph()->machine()->V64x2AnyTrue(), inputs[0]);
case wasm::kExprV64x2AllTrue:
return graph()->NewNode(mcgraph()->machine()->V64x2AllTrue(), inputs[0]);
case wasm::kExprV32x4AnyTrue:
return graph()->NewNode(mcgraph()->machine()->V32x4AnyTrue(), inputs[0]);
case wasm::kExprV32x4AllTrue:
......
src/wasm/wasm-opcodes-inl.h
View file @ 2c38a477
......@@ -35,7 +35,6 @@ namespace wasm {
#define CASE_S64x2_OP(name, str) CASE_OP(S64x2##name, "s64x2." str)
#define CASE_S32x4_OP(name, str) CASE_OP(S32x4##name, "s32x4." str)
#define CASE_S16x8_OP(name, str) CASE_OP(S16x8##name, "s16x8." str)
#define CASE_V64x2_OP(name, str) CASE_OP(V64x2##name, "v64x2." str)
#define CASE_V32x4_OP(name, str) CASE_OP(V32x4##name, "v32x4." str)
#define CASE_V16x8_OP(name, str) CASE_OP(V16x8##name, "v16x8." str)
#define CASE_V8x16_OP(name, str) CASE_OP(V8x16##name, "v8x16." str)
......@@ -235,7 +234,8 @@ constexpr const char* WasmOpcodes::OpcodeName(WasmOpcode opcode) {
CASE_SIMD_OP(Neg, "neg")
CASE_SIMDF_OP(Sqrt, "sqrt")
CASE_SIMD_OP(Eq, "eq")
CASE_SIMD_OP(Ne, "ne")
CASE_SIMDF_OP(Ne, "ne")
CASE_SIMDI_OP(Ne, "ne")
CASE_SIMD_OP(Add, "add")
CASE_SIMD_OP(Sub, "sub")
CASE_SIMD_OP(Mul, "mul")
......@@ -267,17 +267,11 @@ constexpr const char* WasmOpcodes::OpcodeName(WasmOpcode opcode) {
CASE_SIGN_OP(I8x16, ExtractLane, "extract_lane")
CASE_SIMDI_OP(ReplaceLane, "replace_lane")
CASE_SIGN_OP(SIMDI, Min, "min")
CASE_SIGN_OP(I64x2, Min, "min")
CASE_SIGN_OP(SIMDI, Max, "max")
CASE_SIGN_OP(I64x2, Max, "max")
CASE_SIGN_OP(SIMDI, Lt, "lt")
CASE_SIGN_OP(I64x2, Lt, "lt")
CASE_SIGN_OP(SIMDI, Le, "le")
CASE_SIGN_OP(I64x2, Le, "le")
CASE_SIGN_OP(SIMDI, Gt, "gt")
CASE_SIGN_OP(I64x2, Gt, "gt")
CASE_SIGN_OP(SIMDI, Ge, "ge")
CASE_SIGN_OP(I64x2, Ge, "ge")
CASE_CONVERT_OP(Convert, I64x2, I32x4Low, "i32", "convert")
CASE_CONVERT_OP(Convert, I64x2, I32x4High, "i32", "convert")
CASE_SIGN_OP(SIMDI, Shr, "shr")
......@@ -300,8 +294,6 @@ constexpr const char* WasmOpcodes::OpcodeName(WasmOpcode opcode) {
CASE_I8x16_OP(Shuffle, "shuffle")
CASE_SIMDV_OP(AnyTrue, "any_true")
CASE_SIMDV_OP(AllTrue, "all_true")
CASE_V64x2_OP(AnyTrue, "any_true")
CASE_V64x2_OP(AllTrue, "all_true")
CASE_SIMDF_OP(Qfma, "qfma")
CASE_SIMDF_OP(Qfms, "qfms")
......
src/wasm/wasm-opcodes.h
View file @ 2c38a477
......@@ -469,22 +469,7 @@ bool V8_EXPORT_PRIVATE IsJSCompatibleSignature(const FunctionSig* sig,
#define FOREACH_SIMD_POST_MVP_OPCODE(V) \
V(I8x16Mul, 0xfd75, s_ss) \
V(I16x8Q15MulRSatS, 0xfd9c, s_ss) \
V(V64x2AnyTrue, 0xfdc2, i_s) \
V(V64x2AllTrue, 0xfdc3, i_s) \
V(I64x2Eq, 0xfdc0, s_ss) \
V(I64x2Ne, 0xfdc4, s_ss) \
V(I64x2LtS, 0xfdc5, s_ss) \
V(I64x2LtU, 0xfdc6, s_ss) \
V(I64x2GtS, 0xfdd2, s_ss) \
V(I64x2GtU, 0xfdd3, s_ss) \
V(I64x2LeS, 0xfda5, s_ss) \
V(I64x2LeU, 0xfda6, s_ss) \
V(I64x2GeS, 0xfdcf, s_ss) \
V(I64x2GeU, 0xfdd0, s_ss) \
V(I64x2MinS, 0xfdd6, s_ss) \
V(I64x2MinU, 0xfdd7, s_ss) \
V(I64x2MaxS, 0xfde2, s_ss) \
V(I64x2MaxU, 0xfdee, s_ss) \
V(F32x4Qfma, 0xfdb4, s_sss) \
V(F32x4Qfms, 0xfdd4, s_sss) \
V(F64x2Qfma, 0xfdfe, s_sss) \
......
test/cctest/wasm/test-run-wasm-simd.cc
View file @ 2c38a477
......@@ -995,44 +995,6 @@ WASM_SIMD_TEST(I64x2Sub) {
WASM_SIMD_TEST_NO_LOWERING(I64x2Eq) {
RunI64x2BinOpTest(execution_tier, lower_simd, kExprI64x2Eq, Equal);
}
WASM_SIMD_TEST_NO_LOWERING(I64x2Ne) {
RunI64x2BinOpTest(execution_tier, lower_simd, kExprI64x2Ne, NotEqual);
}
WASM_SIMD_TEST_NO_LOWERING(I64x2LtS) {
RunI64x2BinOpTest(execution_tier, lower_simd, kExprI64x2LtS, Less);
}
WASM_SIMD_TEST_NO_LOWERING(I64x2LeS) {
RunI64x2BinOpTest(execution_tier, lower_simd, kExprI64x2LeS, LessEqual);
}
WASM_SIMD_TEST_NO_LOWERING(I64x2GtS) {
RunI64x2BinOpTest(execution_tier, lower_simd, kExprI64x2GtS, Greater);
}
WASM_SIMD_TEST_NO_LOWERING(I64x2GeS) {
RunI64x2BinOpTest(execution_tier, lower_simd, kExprI64x2GeS, GreaterEqual);
}
WASM_SIMD_TEST_NO_LOWERING(I64x2LtU) {
RunI64x2BinOpTest(execution_tier, lower_simd, kExprI64x2LtU, UnsignedLess);
}
WASM_SIMD_TEST_NO_LOWERING(I64x2LeU) {
RunI64x2BinOpTest(execution_tier, lower_simd, kExprI64x2LeU,
UnsignedLessEqual);
}
WASM_SIMD_TEST_NO_LOWERING(I64x2GtU) {
RunI64x2BinOpTest(execution_tier, lower_simd, kExprI64x2GtU, UnsignedGreater);
}
WASM_SIMD_TEST_NO_LOWERING(I64x2GeU) {
RunI64x2BinOpTest(execution_tier, lower_simd, kExprI64x2GeU,
UnsignedGreaterEqual);
}
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X
WASM_SIMD_TEST(F64x2Splat) {
......@@ -1409,26 +1371,6 @@ WASM_SIMD_TEST(I64x2Mul) {
base::MulWithWraparound);
}
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_S390X
WASM_SIMD_TEST_NO_LOWERING(I64x2MinS) {
RunI64x2BinOpTest(execution_tier, lower_simd, kExprI64x2MinS, Minimum);
}
WASM_SIMD_TEST_NO_LOWERING(I64x2MaxS) {
RunI64x2BinOpTest(execution_tier, lower_simd, kExprI64x2MaxS, Maximum);
}
WASM_SIMD_TEST_NO_LOWERING(I64x2MinU) {
RunI64x2BinOpTest(execution_tier, lower_simd, kExprI64x2MinU,
UnsignedMinimum);
}
WASM_SIMD_TEST_NO_LOWERING(I64x2MaxU) {
RunI64x2BinOpTest(execution_tier, lower_simd, kExprI64x2MaxU,
UnsignedMaximum);
}
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_S390X
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X
WASM_SIMD_TEST_NO_LOWERING(F64x2Qfma) {
FLAG_SCOPE(wasm_simd_post_mvp);
......@@ -3109,9 +3051,6 @@ WASM_SIMD_TEST(S8x16MultiShuffleFuzz) {
CHECK_EQ(1, r.Call()); \
}
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
WASM_SIMD_BOOL_REDUCTION_TEST(64x2, 2, WASM_I64V)
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
WASM_SIMD_BOOL_REDUCTION_TEST(32x4, 4, WASM_I32V)
WASM_SIMD_BOOL_REDUCTION_TEST(16x8, 8, WASM_I32V)
WASM_SIMD_BOOL_REDUCTION_TEST(8x16, 16, WASM_I32V)
......@@ -3637,9 +3576,6 @@ WASM_SIMD_TEST_NO_LOWERING(S128LoadMem64Zero) {
DCHECK_EQ(1, r.Call(5)); \
DCHECK_EQ(0, r.Call(0)); \
}
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
WASM_SIMD_ANYTRUE_TEST(64x2, 2, 0xffffffffffffffff, int64_t)
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
WASM_SIMD_ANYTRUE_TEST(32x4, 4, 0xffffffff, int32_t)
WASM_SIMD_ANYTRUE_TEST(16x8, 8, 0xffff, int32_t)
WASM_SIMD_ANYTRUE_TEST(8x16, 16, 0xff, int32_t)
......@@ -3670,9 +3606,6 @@ WASM_SIMD_TEST(V32x4AnytrueWithNegativeZero) {
DCHECK_EQ(1, r.Call(0x1)); \
DCHECK_EQ(0, r.Call(0)); \
}
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
WASM_SIMD_ALLTRUE_TEST(64x2, 2, 0xffffffffffffffff, int64_t)
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
WASM_SIMD_ALLTRUE_TEST(32x4, 4, 0xffffffff, int32_t)
WASM_SIMD_ALLTRUE_TEST(16x8, 8, 0xffff, int32_t)
WASM_SIMD_ALLTRUE_TEST(8x16, 16, 0xff, int32_t)
......
test/common/wasm/wasm-interpreter.cc
View file @ 2c38a477
......@@ -2188,12 +2188,6 @@ class WasmInterpreterInternals {
BINOP_CASE(I64x2Add, i64x2, int2, 2, base::AddWithWraparound(a, b))
BINOP_CASE(I64x2Sub, i64x2, int2, 2, base::SubWithWraparound(a, b))
BINOP_CASE(I64x2Mul, i64x2, int2, 2, base::MulWithWraparound(a, b))
BINOP_CASE(I64x2MinS, i64x2, int2, 2, a < b ? a : b)
BINOP_CASE(I64x2MinU, i64x2, int2, 2,
static_cast<uint64_t>(a) < static_cast<uint64_t>(b) ? a : b)
BINOP_CASE(I64x2MaxS, i64x2, int2, 2, a > b ? a : b)
BINOP_CASE(I64x2MaxU, i64x2, int2, 2,
static_cast<uint64_t>(a) > static_cast<uint64_t>(b) ? a : b)
BINOP_CASE(I32x4Add, i32x4, int4, 4, base::AddWithWraparound(a, b))
BINOP_CASE(I32x4Sub, i32x4, int4, 4, base::SubWithWraparound(a, b))
BINOP_CASE(I32x4Mul, i32x4, int4, 4, base::MulWithWraparound(a, b))
......@@ -2331,19 +2325,6 @@ class WasmInterpreterInternals {
CMPOP_CASE(F32x4Lt, f32x4, float4, int4, 4, a < b)
CMPOP_CASE(F32x4Le, f32x4, float4, int4, 4, a <= b)
CMPOP_CASE(I64x2Eq, i64x2, int2, int2, 2, a == b)
CMPOP_CASE(I64x2Ne, i64x2, int2, int2, 2, a != b)
CMPOP_CASE(I64x2GtS, i64x2, int2, int2, 2, a > b)
CMPOP_CASE(I64x2GeS, i64x2, int2, int2, 2, a >= b)
CMPOP_CASE(I64x2LtS, i64x2, int2, int2, 2, a < b)
CMPOP_CASE(I64x2LeS, i64x2, int2, int2, 2, a <= b)
CMPOP_CASE(I64x2GtU, i64x2, int2, int2, 2,
static_cast<uint64_t>(a) > static_cast<uint64_t>(b))
CMPOP_CASE(I64x2GeU, i64x2, int2, int2, 2,
static_cast<uint64_t>(a) >= static_cast<uint64_t>(b))
CMPOP_CASE(I64x2LtU, i64x2, int2, int2, 2,
static_cast<uint64_t>(a) < static_cast<uint64_t>(b))
CMPOP_CASE(I64x2LeU, i64x2, int2, int2, 2,
static_cast<uint64_t>(a) <= static_cast<uint64_t>(b))
CMPOP_CASE(I32x4Eq, i32x4, int4, int4, 4, a == b)
CMPOP_CASE(I32x4Ne, i32x4, int4, int4, 4, a != b)
CMPOP_CASE(I32x4GtS, i32x4, int4, int4, 4, a > b)
......@@ -2607,7 +2588,6 @@ class WasmInterpreterInternals {
Push(WasmValue(Simd128(res)));
return true;
}
case kExprV64x2AnyTrue:
case kExprV32x4AnyTrue:
case kExprV16x8AnyTrue:
case kExprV8x16AnyTrue: {
......@@ -2626,7 +2606,6 @@ class WasmInterpreterInternals {
Push(WasmValue(res)); \
return true; \
}
REDUCTION_CASE(V64x2AllTrue, i64x2, int2, 2, &)
REDUCTION_CASE(V32x4AllTrue, i32x4, int4, 4, &)
REDUCTION_CASE(V16x8AllTrue, i16x8, int8, 8, &)
REDUCTION_CASE(V8x16AllTrue, i8x16, int16, 16, &)
......
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