S390: [wasm-simd] Prototype i32x4.dot_i16x8_s

Test and Instruction Selection changes are not included and must
be added when opcode is added to SIMD proposal.

Bug: v8:10583
Change-Id: I140d3477d4f3281b24974090c25807eb86af757f
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2261162
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Reviewed-by: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Junliang Yan <jyan@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#68566}

src/compiler/backend/s390/code-generator-s390.cc

@@ -4298,6 +4298,17 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
              Condition(0), Condition(2));
       break;
     }
+    case kS390_I32x4DotI16x8S: {
+      Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
+      __ vme(kScratchDoubleReg, i.InputSimd128Register(0),
+             i.InputSimd128Register(1), Condition(0), Condition(0),
+             Condition(1));
+      __ vmo(tempFPReg1, i.InputSimd128Register(0), i.InputSimd128Register(1),
+             Condition(0), Condition(0), Condition(1));
+      __ va(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
+            Condition(0), Condition(0), Condition(2));
+      break;
+    }
     case kS390_StoreCompressTagged: {
       CHECK(!instr->HasOutput());
       size_t index = 0;

src/compiler/backend/s390/instruction-codes-s390.h

@@ -299,6 +299,7 @@ namespace compiler {
   V(S390_I32x4UConvertI16x8High)            \
   V(S390_I32x4Abs)                          \
   V(S390_I32x4BitMask)                      \
+  V(S390_I32x4DotI16x8S)                    \
   V(S390_I16x8Splat)                        \
   V(S390_I16x8ExtractLaneU)                 \
   V(S390_I16x8ExtractLaneS)                 \

src/compiler/backend/s390/instruction-scheduler-s390.cc

@@ -245,6 +245,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kS390_I32x4UConvertI16x8High:
     case kS390_I32x4Abs:
     case kS390_I32x4BitMask:
+    case kS390_I32x4DotI16x8S:
     case kS390_I16x8Splat:
     case kS390_I16x8ExtractLaneU:
     case kS390_I16x8ExtractLaneS:

src/execution/s390/simulator-s390.cc

@@ -761,6 +761,8 @@ void Simulator::EvalTableInit() {
   V(va, VA, 0xE7F3)       /* type = VRR_C VECTOR ADD  */                       \
   V(vs, VS, 0xE7F7)       /* type = VRR_C VECTOR SUBTRACT  */                  \
   V(vml, VML, 0xE7A2)     /* type = VRR_C VECTOR MULTIPLY LOW  */              \
+  V(vme, VME, 0xE7A6)     /* type = VRR_C VECTOR MULTIPLY EVEN  */             \
+  V(vmo, VMO, 0xE7A7)     /* type = VRR_C VECTOR MULTIPLY ODD  */              \
   V(vnc, VNC, 0xE769)     /* type = VRR_C VECTOR AND WITH COMPLEMENT */        \
   V(vsum, VSUM, 0xE764)   /* type = VRR_C VECTOR SUM ACROSS WORD  */           \
   V(vsumg, VSUMG, 0xE765) /* type = VRR_C VECTOR SUM ACROSS DOUBLEWORD  */     \
@@ -3186,6 +3188,56 @@ EVALUATE(VML) {
   return length;
 }
 
+#define VECTOR_MULTIPLY_EVEN_ODD_TYPE(r1, r2, r3, input_type, result_type, \
+                                      is_odd)                              \
+  size_t i = 0, j = 0, k = 0;                                              \
+  size_t lane_size = sizeof(input_type);                                   \
+  if (is_odd) {                                                            \
+    i = 1;                                                                 \
+    j = lane_size;                                                         \
+  }                                                                        \
+  for (; j < kSimd128Size; i += 2, j += lane_size * 2, k++) {              \
+    input_type src0 = get_simd_register_by_lane<input_type>(r2, i);        \
+    input_type src1 = get_simd_register_by_lane<input_type>(r3, i);        \
+    set_simd_register_by_lane<result_type>(r1, k, src0 * src1);            \
+  }
+#define VECTOR_MULTIPLY_EVEN_ODD(r1, r2, r3, is_odd)                      \
+  switch (m4) {                                                           \
+    case 0: {                                                             \
+      VECTOR_MULTIPLY_EVEN_ODD_TYPE(r1, r2, r3, int8_t, int16_t, is_odd)  \
+      break;                                                              \
+    }                                                                     \
+    case 1: {                                                             \
+      VECTOR_MULTIPLY_EVEN_ODD_TYPE(r1, r2, r3, int16_t, int32_t, is_odd) \
+      break;                                                              \
+    }                                                                     \
+    case 2: {                                                             \
+      VECTOR_MULTIPLY_EVEN_ODD_TYPE(r1, r2, r3, int32_t, int64_t, is_odd) \
+      break;                                                              \
+    }                                                                     \
+    default:                                                              \
+      UNREACHABLE();                                                      \
+  }
+EVALUATE(VME) {
+  DCHECK_OPCODE(VME);
+  DECODE_VRR_C_INSTRUCTION(r1, r2, r3, m6, m5, m4);
+  USE(m5);
+  USE(m6);
+  VECTOR_MULTIPLY_EVEN_ODD(r1, r2, r3, false)
+  return length;
+}
+
+EVALUATE(VMO) {
+  DCHECK_OPCODE(VMO);
+  DECODE_VRR_C_INSTRUCTION(r1, r2, r3, m6, m5, m4);
+  USE(m5);
+  USE(m6);
+  VECTOR_MULTIPLY_EVEN_ODD(r1, r2, r3, true)
+  return length;
+}
+#undef VECTOR_MULTIPLY_EVEN_ODD
+#undef VECTOR_MULTIPLY_EVEN_ODD_TYPE
+
 EVALUATE(VNC) {
   DCHECK(VNC);
   DECODE_VRR_C_INSTRUCTION(r1, r2, r3, m6, m5, m4);