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  20. 19 Jul, 2019 1 commit
  21. 12 Nov, 2018 1 commit
  22. 29 Aug, 2018 1 commit
    • Deepti Gandluri's avatar
      [compiler] Remove AtomicNarrow machine operators, macroize tests · 9a0f2546
      Deepti Gandluri authored
      The AtomicNarrow operations are currently used for wider 64-bit
      operations, that only operate on 32-bits of data or less
      (Ex:I64AtomicAdd8U). Removing these because this can be handled
      in int64-lowering by zeroing the higher order node.
      Explicitly zeroing these in code-gen is not
      required because -
      
       - The spec requires only the data exchange to be atomic, for narrow
         ops this uses only the low word.
       - The return values are not in memory, so are not visible to other
         workers/threads
      
      BUG:v8:6532
      
      Change-Id: I90a795ab6c21c70cb096f59a137de653c9c6a178
      Reviewed-on: https://chromium-review.googlesource.com/1194428Reviewed-by: 's avatarBen Titzer <titzer@chromium.org>
      Reviewed-by: 's avatarBen Smith <binji@chromium.org>
      Commit-Queue: Deepti Gandluri <gdeepti@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#55499}
      9a0f2546
  23. 25 Aug, 2018 1 commit
  24. 14 Aug, 2018 2 commits
    • Benedikt Meurer's avatar
      [turbofan] Further optimize DataView accesses. · 5fecd146
      Benedikt Meurer authored
      This adds support for unaligned load/store access to the DataView
      backing store and uses byteswap operations to fix up the endianess
      when necessary. This changes the Word32ReverseBytes operator to be
      a required operator and adds the missing support on the Intel and
      ARM platforms (on 64-bit platforms the Word64ReverseBytes operator
      is also mandatory now).
      
      This further improves the performance on the dataviewperf.js test
      mentioned in the tracking bug by up to 40%, and at the same time
      reduces the code complexity in the EffectControlLinearizer.
      
      Bug: chromium:225811
      Change-Id: I7c1ec826faf46a144a5a9068f8f815a5fd040997
      Reviewed-on: https://chromium-review.googlesource.com/1174252Reviewed-by: 's avatarSigurd Schneider <sigurds@chromium.org>
      Commit-Queue: Benedikt Meurer <bmeurer@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#55111}
      5fecd146
    • Leszek Swirski's avatar
      Revert "[turbofan] Further optimize DataView accesses." · 6a62d88e
      Leszek Swirski authored
      This reverts commit c46915b9.
      
      Reason for revert: Disasm failures https://ci.chromium.org/p/v8/builders/luci.v8.ci/V8%20Linux%20-%20debug/21727 
      
      Original change's description:
      > [turbofan] Further optimize DataView accesses.
      > 
      > This adds support for unaligned load/store access to the DataView
      > backing store and uses byteswap operations to fix up the endianess
      > when necessary. This changes the Word32ReverseBytes operator to be
      > a required operator and adds the missing support on the Intel and
      > ARM platforms (on 64-bit platforms the Word64ReverseBytes operator
      > is also mandatory now).
      > 
      > This further improves the performance on the dataviewperf.js test
      > mentioned in the tracking bug by up to 40%, and at the same time
      > reduces the code complexity in the EffectControlLinearizer.
      > 
      > Bug: chromium:225811
      > Change-Id: I296170b828c2ccc1c317ed37840b564aa14cdec2
      > Reviewed-on: https://chromium-review.googlesource.com/1172777
      > Commit-Queue: Benedikt Meurer <bmeurer@chromium.org>
      > Reviewed-by: Sigurd Schneider <sigurds@chromium.org>
      > Cr-Commit-Position: refs/heads/master@{#55099}
      
      TBR=sigurds@chromium.org,bmeurer@chromium.org
      
      Change-Id: If7a62e3a1a4ad26823fcbd2ab6eb4c053ad11c49
      No-Presubmit: true
      No-Tree-Checks: true
      No-Try: true
      Bug: chromium:225811
      Reviewed-on: https://chromium-review.googlesource.com/1174171Reviewed-by: 's avatarLeszek Swirski <leszeks@chromium.org>
      Commit-Queue: Leszek Swirski <leszeks@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#55107}
      6a62d88e
  25. 13 Aug, 2018 1 commit
    • Benedikt Meurer's avatar
      [turbofan] Further optimize DataView accesses. · c46915b9
      Benedikt Meurer authored
      This adds support for unaligned load/store access to the DataView
      backing store and uses byteswap operations to fix up the endianess
      when necessary. This changes the Word32ReverseBytes operator to be
      a required operator and adds the missing support on the Intel and
      ARM platforms (on 64-bit platforms the Word64ReverseBytes operator
      is also mandatory now).
      
      This further improves the performance on the dataviewperf.js test
      mentioned in the tracking bug by up to 40%, and at the same time
      reduces the code complexity in the EffectControlLinearizer.
      
      Bug: chromium:225811
      Change-Id: I296170b828c2ccc1c317ed37840b564aa14cdec2
      Reviewed-on: https://chromium-review.googlesource.com/1172777
      Commit-Queue: Benedikt Meurer <bmeurer@chromium.org>
      Reviewed-by: 's avatarSigurd Schneider <sigurds@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#55099}
      c46915b9
  26. 29 Jan, 2018 1 commit
  27. 20 Dec, 2017 1 commit
    • Andreas Haas's avatar
      [arm][turbofan] Implement on-stack returns. · 9c7b6e1e
      Andreas Haas authored
      This is the implementation of crrev.com/c/766371 for arm.
      
      Original description:
      
      Add the ability to return (multiple) return values on the stack:
      
      - Extend stack frames with a new buffer region for return slots.
        This region is located at the end of a caller's frame such that
        its slots can be indexed as caller frame slots in a callee
        (located beyond its parameters) and assigned return values.
      - Adjust stack frame constructon and deconstruction accordingly.
      - Extend linkage computation to support register plus stack returns.
      - Reserve return slots in caller frame when respective calls occur.
      - Introduce and generate architecture instructions ('peek') for
        reading back results from return slots in the caller.
      - Aggressive tests.
      - Some minor clean-up.
      
      R=v8-arm-ports@googlegroups.com
      
      Change-Id: I7d61424a184d5778baf1d1270013f4e0c7ec68b4
      Reviewed-on: https://chromium-review.googlesource.com/836608Reviewed-by: 's avatarJaroslav Sevcik <jarin@chromium.org>
      Commit-Queue: Andreas Haas <ahaas@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#50237}
      9c7b6e1e
  28. 20 Jul, 2017 1 commit
  29. 13 Jun, 2017 1 commit
  30. 21 May, 2017 1 commit
    • gdeepti's avatar
      [wasm] Swap the implementation of SIMD compare ops using Gt/Ge insteas of Lt/Le · eeefc74a
      gdeepti authored
      Currently SIMD integer comparison ops are implemented using Lt/Le, this is
      sub-optimal on Intel, because all compares are done using pcmpgt(d/w/b) that
      clobber the destination register, and will need additional instructions to
      when using Lt/Le as the base implementation. This CL proposes moving to Gt/Ge
      as the underlying implementation as this will only require swapping operands
      on MIPS and is consistent with x86/ARM instructions.
      
      BUG=v8:6020
      
      R=bbudge@chromium.org, bmeurer@chromium.org, bradnelson@chromium.org
      
      Review-Url: https://codereview.chromium.org/2874403002
      Cr-Commit-Position: refs/heads/master@{#45440}
      eeefc74a
  31. 09 May, 2017 1 commit
  32. 24 Apr, 2017 1 commit
  33. 21 Apr, 2017 1 commit
    • bbudge's avatar
      [WASM SIMD] Remove opcodes that are slow on some platforms. · dddfcfd0
      bbudge authored
      These can be synthesized from existing operations and scheduled for
      better performance than if we have to generate blocks of instructions
      that take many cycles to complete.
      - Remove F32x4RecipRefine, F32x4RecipSqrtRefine. Clients are better off
        synthesizing these from splats, multiplies and adds.
      - Remove F32x4Div, F32x4Sqrt, F32x4MinNum, F32x4MaxNum. Clients are
        better off synthesizing these or using the reciprocal approximations,
        possibly with a refinement step.
      
      LOG=N
      BUG=v8:6020
      
      Review-Url: https://codereview.chromium.org/2827143002
      Cr-Commit-Position: refs/heads/master@{#44784}
      dddfcfd0
  34. 19 Apr, 2017 1 commit
    • bbudge's avatar
      [WASM SIMD] Implement primitive shuffles. · 5806d862
      bbudge authored
      - Adds unary Reverse shuffles (swizzles): S32x2Reverse, S16x4Reverse,
        S16x2Reverse, S8x8Reverse, S8x4Reverse, S8x2Reverse. Reversals are
        done within the sub-vectors that prefix the opcode name, e.g. S8x2
        reverses the 8 consecutive pairs in an S8x16 vector.
      
      - Adds binary Zip (interleave) left and right half-shuffles to return a
        single vector: S32x4ZipLeft, S32x4ZipRightS16x8ZipLeft, S16x8ZipRight,
        S8x16ZipLeft, S8x16ZipRight.
      
      - Adds binary Unzip (de-interleave) left and right half shuffles to return
        a single vector: S32x4UnzipLeft, S32x4UnzipRight, S16x8UnzipLeft,
        S16x8UnzipRight, S8x16UnzipLeft, S8x16UnzipRight.
      
      - Adds binary Transpose left and right half shuffles to return
        a single vector: S32x4TransposeLeft, S32x4TransposeRight,
        S16x8TransposeLeft, S16xTransposeRight, S8x16TransposeLeft,
        S8x16TransposeRight.
      
      - Adds binary Concat (concatenate) byte shuffle: S8x16Concat #bytes to
        paste two vectors together.
      
      LOG=N
      BUG=v8:6020
      
      Review-Url: https://codereview.chromium.org/2801183002
      Cr-Commit-Position: refs/heads/master@{#44734}
      5806d862
  35. 10 Apr, 2017 1 commit
    • bbudge's avatar
      [WASM SIMD] Implement packing and unpacking integer conversions. · dbfc0300
      bbudge authored
      - Adds WASM opcodes I32x4SConvertI16x8Low, I32x4SConvertI16x8High,
        I32x4UConvertI16x8Low, I32x4UConvertI16x8High, which unpack half of
        an I16x8 register into a whole I32x4 register, with signed or unsigned
        extension. Having separate Low/High opcodes works around the difficulty
        of having multiple output registers, which would be necessary if we unpacked
        the entire I16x8 register.
      
      - Adds WASM opcodes I16x8SConvertI8x16Low, I16x8SConvertI8x16High,
        I16x8UConvertI8x16Low, I16x8UConvertI8x16High, similarly to above.
      
      - Adds WASM opcodes I16x8SConvertI32x4, I16x8UConvertI32x4,
        I8x16SConvert16x8, I8x16UConvertI16x8, which pack two source registers
        into a single destination register with signed or unsigned saturation. These
        could have been separated into half operations, but this is simpler to
        implement with SSE, AVX, and is acceptable on ARM. It also avoids adding
        operations that only modify half of their destination register.
      
      - Implements these opcodes for ARM.
      
      LOG=N
      BUG=v8:6020
      
      Review-Url: https://codereview.chromium.org/2800523002
      Cr-Commit-Position: refs/heads/master@{#44541}
      dbfc0300
  36. 29 Mar, 2017 1 commit
  37. 24 Mar, 2017 1 commit