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Commit dbfc0300 authored by bbudge's avatar bbudge Committed by Commit bot
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[WASM SIMD] Implement packing and unpacking integer conversions. 

- Adds WASM opcodes I32x4SConvertI16x8Low, I32x4SConvertI16x8High,
  I32x4UConvertI16x8Low, I32x4UConvertI16x8High, which unpack half of
  an I16x8 register into a whole I32x4 register, with signed or unsigned
  extension. Having separate Low/High opcodes works around the difficulty
  of having multiple output registers, which would be necessary if we unpacked
  the entire I16x8 register.

- Adds WASM opcodes I16x8SConvertI8x16Low, I16x8SConvertI8x16High,
  I16x8UConvertI8x16Low, I16x8UConvertI8x16High, similarly to above.

- Adds WASM opcodes I16x8SConvertI32x4, I16x8UConvertI32x4,
  I8x16SConvert16x8, I8x16UConvertI16x8, which pack two source registers
  into a single destination register with signed or unsigned saturation. These
  could have been separated into half operations, but this is simpler to
  implement with SSE, AVX, and is acceptable on ARM. It also avoids adding
  operations that only modify half of their destination register.

- Implements these opcodes for ARM.

LOG=N
BUG=v8:6020

Review-Url: https://codereview.chromium.org/2800523002
Cr-Commit-Position: refs/heads/master@{#44541}
parent 5f7e6331
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Showing with 481 additions and 48 deletions
src/compiler/arm/code-generator-arm.cc
View file @ dbfc0300
......@@ -1668,6 +1668,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vcvt_s32_f32(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kArmI32x4SConvertI16x8Low: {
__ vmovl(NeonS16, i.OutputSimd128Register(),
i.InputSimd128Register(0).low());
break;
}
case kArmI32x4SConvertI16x8High: {
__ vmovl(NeonS16, i.OutputSimd128Register(),
i.InputSimd128Register(0).high());
break;
}
case kArmI32x4Neg: {
__ vneg(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
......@@ -1733,6 +1743,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vcvt_u32_f32(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kArmI32x4UConvertI16x8Low: {
__ vmovl(NeonU16, i.OutputSimd128Register(),
i.InputSimd128Register(0).low());
break;
}
case kArmI32x4UConvertI16x8High: {
__ vmovl(NeonU16, i.OutputSimd128Register(),
i.InputSimd128Register(0).high());
break;
}
case kArmI32x4ShrU: {
__ vshr(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt5(1));
......@@ -1772,6 +1792,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputRegister(2), NeonS16, i.InputInt8(1));
break;
}
case kArmI16x8SConvertI8x16Low: {
__ vmovl(NeonS8, i.OutputSimd128Register(),
i.InputSimd128Register(0).low());
break;
}
case kArmI16x8SConvertI8x16High: {
__ vmovl(NeonS8, i.OutputSimd128Register(),
i.InputSimd128Register(0).high());
break;
}
case kArmI16x8Neg: {
__ vneg(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
......@@ -1786,6 +1816,25 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputInt4(1));
break;
}
case kArmI16x8SConvertI32x4: {
Simd128Register dst = i.OutputSimd128Register(),
src0 = i.InputSimd128Register(0),
src1 = i.InputSimd128Register(1);
// Take care not to overwrite a source register before it's used.
if (dst.is(src0) && dst.is(src1)) {
__ vqmovn(NeonS16, dst.low(), src0);
__ vmov(dst.high(), dst.low());
} else if (dst.is(src0)) {
// dst is src0, so narrow src0 first.
__ vqmovn(NeonS16, dst.low(), src0);
__ vqmovn(NeonS16, dst.high(), src1);
} else {
// dst may alias src1, so narrow src1 first.
__ vqmovn(NeonS16, dst.high(), src1);
__ vqmovn(NeonS16, dst.low(), src0);
}
break;
}
case kArmI16x8Add: {
__ vadd(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
......@@ -1843,11 +1892,40 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(0));
break;
}
case kArmI16x8UConvertI8x16Low: {
__ vmovl(NeonU8, i.OutputSimd128Register(),
i.InputSimd128Register(0).low());
break;
}
case kArmI16x8UConvertI8x16High: {
__ vmovl(NeonU8, i.OutputSimd128Register(),
i.InputSimd128Register(0).high());
break;
}
case kArmI16x8ShrU: {
__ vshr(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt4(1));
break;
}
case kArmI16x8UConvertI32x4: {
Simd128Register dst = i.OutputSimd128Register(),
src0 = i.InputSimd128Register(0),
src1 = i.InputSimd128Register(1);
// Take care not to overwrite a source register before it's used.
if (dst.is(src0) && dst.is(src1)) {
__ vqmovn(NeonU16, dst.low(), src0);
__ vmov(dst.high(), dst.low());
} else if (dst.is(src0)) {
// dst is src0, so narrow src0 first.
__ vqmovn(NeonU16, dst.low(), src0);
__ vqmovn(NeonU16, dst.high(), src1);
} else {
// dst may alias src1, so narrow src1 first.
__ vqmovn(NeonU16, dst.high(), src1);
__ vqmovn(NeonU16, dst.low(), src0);
}
break;
}
case kArmI16x8AddSaturateU: {
__ vqadd(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
......@@ -1906,6 +1984,25 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputInt3(1));
break;
}
case kArmI8x16SConvertI16x8: {
Simd128Register dst = i.OutputSimd128Register(),
src0 = i.InputSimd128Register(0),
src1 = i.InputSimd128Register(1);
// Take care not to overwrite a source register before it's used.
if (dst.is(src0) && dst.is(src1)) {
__ vqmovn(NeonS8, dst.low(), src0);
__ vmov(dst.high(), dst.low());
} else if (dst.is(src0)) {
// dst is src0, so narrow src0 first.
__ vqmovn(NeonS8, dst.low(), src0);
__ vqmovn(NeonS8, dst.high(), src1);
} else {
// dst may alias src1, so narrow src1 first.
__ vqmovn(NeonS8, dst.high(), src1);
__ vqmovn(NeonS8, dst.low(), src0);
}
break;
}
case kArmI8x16Add: {
__ vadd(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
......@@ -1967,6 +2064,25 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputInt3(1));
break;
}
case kArmI8x16UConvertI16x8: {
Simd128Register dst = i.OutputSimd128Register(),
src0 = i.InputSimd128Register(0),
src1 = i.InputSimd128Register(1);
// Take care not to overwrite a source register before it's used.
if (dst.is(src0) && dst.is(src1)) {
__ vqmovn(NeonU8, dst.low(), src0);
__ vmov(dst.high(), dst.low());
} else if (dst.is(src0)) {
// dst is src0, so narrow src0 first.
__ vqmovn(NeonU8, dst.low(), src0);
__ vqmovn(NeonU8, dst.high(), src1);
} else {
// dst may alias src1, so narrow src1 first.
__ vqmovn(NeonU8, dst.high(), src1);
__ vqmovn(NeonU8, dst.low(), src0);
}
break;
}
case kArmI8x16AddSaturateU: {
__ vqadd(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
......
src/compiler/arm/instruction-codes-arm.h
View file @ dbfc0300
......@@ -148,6 +148,8 @@ namespace compiler {
V(ArmI32x4ExtractLane) \
V(ArmI32x4ReplaceLane) \
V(ArmI32x4SConvertF32x4) \
V(ArmI32x4SConvertI16x8Low) \
V(ArmI32x4SConvertI16x8High) \
V(ArmI32x4Neg) \
V(ArmI32x4Shl) \
V(ArmI32x4ShrS) \
......@@ -161,6 +163,8 @@ namespace compiler {
V(ArmI32x4LtS) \
V(ArmI32x4LeS) \
V(ArmI32x4UConvertF32x4) \
V(ArmI32x4UConvertI16x8Low) \
V(ArmI32x4UConvertI16x8High) \
V(ArmI32x4ShrU) \
V(ArmI32x4MinU) \
V(ArmI32x4MaxU) \
......@@ -169,9 +173,12 @@ namespace compiler {
V(ArmI16x8Splat) \
V(ArmI16x8ExtractLane) \
V(ArmI16x8ReplaceLane) \
V(ArmI16x8SConvertI8x16Low) \
V(ArmI16x8SConvertI8x16High) \
V(ArmI16x8Neg) \
V(ArmI16x8Shl) \
V(ArmI16x8ShrS) \
V(ArmI16x8SConvertI32x4) \
V(ArmI16x8Add) \
V(ArmI16x8AddSaturateS) \
V(ArmI16x8Sub) \
......@@ -183,7 +190,10 @@ namespace compiler {
V(ArmI16x8Ne) \
V(ArmI16x8LtS) \
V(ArmI16x8LeS) \
V(ArmI16x8UConvertI8x16Low) \
V(ArmI16x8UConvertI8x16High) \
V(ArmI16x8ShrU) \
V(ArmI16x8UConvertI32x4) \
V(ArmI16x8AddSaturateU) \
V(ArmI16x8SubSaturateU) \
V(ArmI16x8MinU) \
......@@ -196,6 +206,7 @@ namespace compiler {
V(ArmI8x16Neg) \
V(ArmI8x16Shl) \
V(ArmI8x16ShrS) \
V(ArmI8x16SConvertI16x8) \
V(ArmI8x16Add) \
V(ArmI8x16AddSaturateS) \
V(ArmI8x16Sub) \
......@@ -208,6 +219,7 @@ namespace compiler {
V(ArmI8x16LtS) \
V(ArmI8x16LeS) \
V(ArmI8x16ShrU) \
V(ArmI8x16UConvertI16x8) \
V(ArmI8x16AddSaturateU) \
V(ArmI8x16SubSaturateU) \
V(ArmI8x16MinU) \
......
src/compiler/arm/instruction-scheduler-arm.cc
View file @ dbfc0300
......@@ -132,6 +132,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmI32x4ExtractLane:
case kArmI32x4ReplaceLane:
case kArmI32x4SConvertF32x4:
case kArmI32x4SConvertI16x8Low:
case kArmI32x4SConvertI16x8High:
case kArmI32x4Neg:
case kArmI32x4Shl:
case kArmI32x4ShrS:
......@@ -145,6 +147,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmI32x4LtS:
case kArmI32x4LeS:
case kArmI32x4UConvertF32x4:
case kArmI32x4UConvertI16x8Low:
case kArmI32x4UConvertI16x8High:
case kArmI32x4ShrU:
case kArmI32x4MinU:
case kArmI32x4MaxU:
......@@ -153,9 +157,12 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmI16x8Splat:
case kArmI16x8ExtractLane:
case kArmI16x8ReplaceLane:
case kArmI16x8SConvertI8x16Low:
case kArmI16x8SConvertI8x16High:
case kArmI16x8Neg:
case kArmI16x8Shl:
case kArmI16x8ShrS:
case kArmI16x8SConvertI32x4:
case kArmI16x8Add:
case kArmI16x8AddSaturateS:
case kArmI16x8Sub:
......@@ -167,9 +174,12 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmI16x8Ne:
case kArmI16x8LtS:
case kArmI16x8LeS:
case kArmI16x8UConvertI8x16Low:
case kArmI16x8UConvertI8x16High:
case kArmI16x8ShrU:
case kArmI16x8UConvertI32x4:
case kArmI16x8AddSaturateU:
case kArmI16x8SubSaturateU:
case kArmI16x8ShrU:
case kArmI16x8MinU:
case kArmI16x8MaxU:
case kArmI16x8LtU:
......@@ -180,6 +190,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmI8x16Neg:
case kArmI8x16Shl:
case kArmI8x16ShrS:
case kArmI8x16SConvertI16x8:
case kArmI8x16Add:
case kArmI8x16AddSaturateS:
case kArmI8x16Sub:
......@@ -191,6 +202,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmI8x16Ne:
case kArmI8x16LtS:
case kArmI8x16LeS:
case kArmI8x16UConvertI16x8:
case kArmI8x16AddSaturateU:
case kArmI8x16SubSaturateU:
case kArmI8x16ShrU:
......
src/compiler/arm/instruction-selector-arm.cc
View file @ dbfc0300
......@@ -2320,27 +2320,35 @@ void InstructionSelector::VisitAtomicCompareExchange(Node* node) {
V(S1x8Zero) \
V(S1x16Zero)
#define SIMD_UNOP_LIST(V) \
V(F32x4SConvertI32x4, kArmF32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kArmF32x4UConvertI32x4) \
V(F32x4Abs, kArmF32x4Abs) \
V(F32x4Neg, kArmF32x4Neg) \
V(F32x4RecipApprox, kArmF32x4RecipApprox) \
V(F32x4RecipSqrtApprox, kArmF32x4RecipSqrtApprox) \
V(I32x4SConvertF32x4, kArmI32x4SConvertF32x4) \
V(I32x4Neg, kArmI32x4Neg) \
V(I32x4UConvertF32x4, kArmI32x4UConvertF32x4) \
V(I16x8Neg, kArmI16x8Neg) \
V(I8x16Neg, kArmI8x16Neg) \
V(S128Not, kArmS128Not) \
V(S1x4Not, kArmS128Not) \
V(S1x4AnyTrue, kArmS1x4AnyTrue) \
V(S1x4AllTrue, kArmS1x4AllTrue) \
V(S1x8Not, kArmS128Not) \
V(S1x8AnyTrue, kArmS1x8AnyTrue) \
V(S1x8AllTrue, kArmS1x8AllTrue) \
V(S1x16Not, kArmS128Not) \
V(S1x16AnyTrue, kArmS1x16AnyTrue) \
#define SIMD_UNOP_LIST(V) \
V(F32x4SConvertI32x4, kArmF32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kArmF32x4UConvertI32x4) \
V(F32x4Abs, kArmF32x4Abs) \
V(F32x4Neg, kArmF32x4Neg) \
V(F32x4RecipApprox, kArmF32x4RecipApprox) \
V(F32x4RecipSqrtApprox, kArmF32x4RecipSqrtApprox) \
V(I32x4SConvertF32x4, kArmI32x4SConvertF32x4) \
V(I32x4SConvertI16x8Low, kArmI32x4SConvertI16x8Low) \
V(I32x4SConvertI16x8High, kArmI32x4SConvertI16x8High) \
V(I32x4Neg, kArmI32x4Neg) \
V(I32x4UConvertF32x4, kArmI32x4UConvertF32x4) \
V(I32x4UConvertI16x8Low, kArmI32x4UConvertI16x8Low) \
V(I32x4UConvertI16x8High, kArmI32x4UConvertI16x8High) \
V(I16x8SConvertI8x16Low, kArmI16x8SConvertI8x16Low) \
V(I16x8SConvertI8x16High, kArmI16x8SConvertI8x16High) \
V(I16x8Neg, kArmI16x8Neg) \
V(I16x8UConvertI8x16Low, kArmI16x8UConvertI8x16Low) \
V(I16x8UConvertI8x16High, kArmI16x8UConvertI8x16High) \
V(I8x16Neg, kArmI8x16Neg) \
V(S128Not, kArmS128Not) \
V(S1x4Not, kArmS128Not) \
V(S1x4AnyTrue, kArmS1x4AnyTrue) \
V(S1x4AllTrue, kArmS1x4AllTrue) \
V(S1x8Not, kArmS128Not) \
V(S1x8AnyTrue, kArmS1x8AnyTrue) \
V(S1x8AllTrue, kArmS1x8AllTrue) \
V(S1x16Not, kArmS128Not) \
V(S1x16AnyTrue, kArmS1x16AnyTrue) \
V(S1x16AllTrue, kArmS1x16AllTrue)
#define SIMD_SHIFT_OP_LIST(V) \
......@@ -2379,6 +2387,7 @@ void InstructionSelector::VisitAtomicCompareExchange(Node* node) {
V(I32x4MaxU, kArmI32x4MaxU) \
V(I32x4LtU, kArmI32x4LtU) \
V(I32x4LeU, kArmI32x4LeU) \
V(I16x8SConvertI32x4, kArmI16x8SConvertI32x4) \
V(I16x8Add, kArmI16x8Add) \
V(I16x8AddSaturateS, kArmI16x8AddSaturateS) \
V(I16x8Sub, kArmI16x8Sub) \
......@@ -2390,12 +2399,14 @@ void InstructionSelector::VisitAtomicCompareExchange(Node* node) {
V(I16x8Ne, kArmI16x8Ne) \
V(I16x8LtS, kArmI16x8LtS) \
V(I16x8LeS, kArmI16x8LeS) \
V(I16x8UConvertI32x4, kArmI16x8UConvertI32x4) \
V(I16x8AddSaturateU, kArmI16x8AddSaturateU) \
V(I16x8SubSaturateU, kArmI16x8SubSaturateU) \
V(I16x8MinU, kArmI16x8MinU) \
V(I16x8MaxU, kArmI16x8MaxU) \
V(I16x8LtU, kArmI16x8LtU) \
V(I16x8LeU, kArmI16x8LeU) \
V(I8x16SConvertI16x8, kArmI8x16SConvertI16x8) \
V(I8x16Add, kArmI8x16Add) \
V(I8x16AddSaturateS, kArmI8x16AddSaturateS) \
V(I8x16Sub, kArmI8x16Sub) \
......@@ -2407,6 +2418,7 @@ void InstructionSelector::VisitAtomicCompareExchange(Node* node) {
V(I8x16Ne, kArmI8x16Ne) \
V(I8x16LtS, kArmI8x16LtS) \
V(I8x16LeS, kArmI8x16LeS) \
V(I8x16UConvertI16x8, kArmI8x16UConvertI16x8) \
V(I8x16AddSaturateU, kArmI8x16AddSaturateU) \
V(I8x16SubSaturateU, kArmI8x16SubSaturateU) \
V(I8x16MinU, kArmI8x16MinU) \
......
src/compiler/instruction-selector.cc
View file @ dbfc0300
......@@ -1528,6 +1528,10 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsSimd128(node), VisitI32x4ReplaceLane(node);
case IrOpcode::kI32x4SConvertF32x4:
return MarkAsSimd128(node), VisitI32x4SConvertF32x4(node);
case IrOpcode::kI32x4SConvertI16x8Low:
return MarkAsSimd128(node), VisitI32x4SConvertI16x8Low(node);
case IrOpcode::kI32x4SConvertI16x8High:
return MarkAsSimd128(node), VisitI32x4SConvertI16x8High(node);
case IrOpcode::kI32x4Neg:
return MarkAsSimd128(node), VisitI32x4Neg(node);
case IrOpcode::kI32x4Shl:
......@@ -1554,6 +1558,10 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsSimd1x4(node), VisitI32x4LeS(node);
case IrOpcode::kI32x4UConvertF32x4:
return MarkAsSimd128(node), VisitI32x4UConvertF32x4(node);
case IrOpcode::kI32x4UConvertI16x8Low:
return MarkAsSimd128(node), VisitI32x4UConvertI16x8Low(node);
case IrOpcode::kI32x4UConvertI16x8High:
return MarkAsSimd128(node), VisitI32x4UConvertI16x8High(node);
case IrOpcode::kI32x4ShrU:
return MarkAsSimd128(node), VisitI32x4ShrU(node);
case IrOpcode::kI32x4MinU:
......@@ -1570,12 +1578,18 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsWord32(node), VisitI16x8ExtractLane(node);
case IrOpcode::kI16x8ReplaceLane:
return MarkAsSimd128(node), VisitI16x8ReplaceLane(node);
case IrOpcode::kI16x8SConvertI8x16Low:
return MarkAsSimd128(node), VisitI16x8SConvertI8x16Low(node);
case IrOpcode::kI16x8SConvertI8x16High:
return MarkAsSimd128(node), VisitI16x8SConvertI8x16High(node);
case IrOpcode::kI16x8Neg:
return MarkAsSimd128(node), VisitI16x8Neg(node);
case IrOpcode::kI16x8Shl:
return MarkAsSimd128(node), VisitI16x8Shl(node);
case IrOpcode::kI16x8ShrS:
return MarkAsSimd128(node), VisitI16x8ShrS(node);
case IrOpcode::kI16x8SConvertI32x4:
return MarkAsSimd128(node), VisitI16x8SConvertI32x4(node);
case IrOpcode::kI16x8Add:
return MarkAsSimd128(node), VisitI16x8Add(node);
case IrOpcode::kI16x8AddSaturateS:
......@@ -1598,8 +1612,14 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsSimd1x8(node), VisitI16x8LtS(node);
case IrOpcode::kI16x8LeS:
return MarkAsSimd1x8(node), VisitI16x8LeS(node);
case IrOpcode::kI16x8UConvertI8x16Low:
return MarkAsSimd128(node), VisitI16x8UConvertI8x16Low(node);
case IrOpcode::kI16x8UConvertI8x16High:
return MarkAsSimd128(node), VisitI16x8UConvertI8x16High(node);
case IrOpcode::kI16x8ShrU:
return MarkAsSimd128(node), VisitI16x8ShrU(node);
case IrOpcode::kI16x8UConvertI32x4:
return MarkAsSimd128(node), VisitI16x8UConvertI32x4(node);
case IrOpcode::kI16x8AddSaturateU:
return MarkAsSimd128(node), VisitI16x8AddSaturateU(node);
case IrOpcode::kI16x8SubSaturateU:
......@@ -1624,6 +1644,8 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsSimd128(node), VisitI8x16Shl(node);
case IrOpcode::kI8x16ShrS:
return MarkAsSimd128(node), VisitI8x16ShrS(node);
case IrOpcode::kI8x16SConvertI16x8:
return MarkAsSimd128(node), VisitI8x16SConvertI16x8(node);
case IrOpcode::kI8x16Add:
return MarkAsSimd128(node), VisitI8x16Add(node);
case IrOpcode::kI8x16AddSaturateS:
......@@ -1648,6 +1670,8 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsSimd1x16(node), VisitI8x16LeS(node);
case IrOpcode::kI8x16ShrU:
return MarkAsSimd128(node), VisitI8x16ShrU(node);
case IrOpcode::kI8x16UConvertI16x8:
return MarkAsSimd128(node), VisitI8x16UConvertI16x8(node);
case IrOpcode::kI8x16AddSaturateU:
return MarkAsSimd128(node), VisitI8x16AddSaturateU(node);
case IrOpcode::kI8x16SubSaturateU:
......@@ -2139,6 +2163,14 @@ void InstructionSelector::VisitI32x4SConvertF32x4(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI32x4SConvertI16x8Low(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI32x4SConvertI16x8High(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI32x4Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4LtS(Node* node) { UNIMPLEMENTED(); }
......@@ -2149,6 +2181,14 @@ void InstructionSelector::VisitI32x4UConvertF32x4(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI32x4UConvertI16x8Low(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI32x4UConvertI16x8High(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI32x4LtU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4LeU(Node* node) { UNIMPLEMENTED(); }
......@@ -2159,12 +2199,24 @@ void InstructionSelector::VisitI16x8ExtractLane(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8ReplaceLane(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8SConvertI8x16Low(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8SConvertI8x16High(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8Shl(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8ShrS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8SConvertI32x4(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8Add(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8AddSaturateS(Node* node) {
......@@ -2191,8 +2243,20 @@ void InstructionSelector::VisitI16x8LtS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8LeS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8UConvertI8x16Low(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8UConvertI8x16High(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8ShrU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8UConvertI32x4(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8AddSaturateU(Node* node) {
UNIMPLEMENTED();
}
......@@ -2221,6 +2285,10 @@ void InstructionSelector::VisitI8x16Shl(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16ShrS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16SConvertI16x8(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI8x16Add(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16AddSaturateS(Node* node) {
......@@ -2249,6 +2317,10 @@ void InstructionSelector::VisitI8x16LeS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16ShrU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16UConvertI16x8(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI8x16AddSaturateU(Node* node) {
UNIMPLEMENTED();
}
......
src/compiler/machine-operator.cc
View file @ dbfc0300
......@@ -254,6 +254,8 @@ MachineType AtomicCompareExchangeRepresentationOf(Operator const* op) {
V(F32x4Le, Operator::kNoProperties, 2, 0, 1) \
V(I32x4Splat, Operator::kNoProperties, 1, 0, 1) \
V(I32x4SConvertF32x4, Operator::kNoProperties, 1, 0, 1) \
V(I32x4SConvertI16x8Low, Operator::kNoProperties, 1, 0, 1) \
V(I32x4SConvertI16x8High, Operator::kNoProperties, 1, 0, 1) \
V(I32x4Neg, Operator::kNoProperties, 1, 0, 1) \
V(I32x4Add, Operator::kCommutative, 2, 0, 1) \
V(I32x4Sub, Operator::kNoProperties, 2, 0, 1) \
......@@ -265,12 +267,17 @@ MachineType AtomicCompareExchangeRepresentationOf(Operator const* op) {
V(I32x4LtS, Operator::kNoProperties, 2, 0, 1) \
V(I32x4LeS, Operator::kNoProperties, 2, 0, 1) \
V(I32x4UConvertF32x4, Operator::kNoProperties, 1, 0, 1) \
V(I32x4UConvertI16x8Low, Operator::kNoProperties, 1, 0, 1) \
V(I32x4UConvertI16x8High, Operator::kNoProperties, 1, 0, 1) \
V(I32x4MinU, Operator::kCommutative, 2, 0, 1) \
V(I32x4MaxU, Operator::kCommutative, 2, 0, 1) \
V(I32x4LtU, Operator::kNoProperties, 2, 0, 1) \
V(I32x4LeU, Operator::kNoProperties, 2, 0, 1) \
V(I16x8Splat, Operator::kNoProperties, 1, 0, 1) \
V(I16x8SConvertI8x16Low, Operator::kNoProperties, 1, 0, 1) \
V(I16x8SConvertI8x16High, Operator::kNoProperties, 1, 0, 1) \
V(I16x8Neg, Operator::kNoProperties, 1, 0, 1) \
V(I16x8SConvertI32x4, Operator::kNoProperties, 2, 0, 1) \
V(I16x8Add, Operator::kCommutative, 2, 0, 1) \
V(I16x8AddSaturateS, Operator::kCommutative, 2, 0, 1) \
V(I16x8Sub, Operator::kNoProperties, 2, 0, 1) \
......@@ -282,6 +289,9 @@ MachineType AtomicCompareExchangeRepresentationOf(Operator const* op) {
V(I16x8Ne, Operator::kCommutative, 2, 0, 1) \
V(I16x8LtS, Operator::kNoProperties, 2, 0, 1) \
V(I16x8LeS, Operator::kNoProperties, 2, 0, 1) \
V(I16x8UConvertI8x16Low, Operator::kNoProperties, 1, 0, 1) \
V(I16x8UConvertI8x16High, Operator::kNoProperties, 1, 0, 1) \
V(I16x8UConvertI32x4, Operator::kNoProperties, 2, 0, 1) \
V(I16x8AddSaturateU, Operator::kCommutative, 2, 0, 1) \
V(I16x8SubSaturateU, Operator::kNoProperties, 2, 0, 1) \
V(I16x8MinU, Operator::kCommutative, 2, 0, 1) \
......@@ -290,6 +300,7 @@ MachineType AtomicCompareExchangeRepresentationOf(Operator const* op) {
V(I16x8LeU, Operator::kNoProperties, 2, 0, 1) \
V(I8x16Splat, Operator::kNoProperties, 1, 0, 1) \
V(I8x16Neg, Operator::kNoProperties, 1, 0, 1) \
V(I8x16SConvertI16x8, Operator::kNoProperties, 2, 0, 1) \
V(I8x16Add, Operator::kCommutative, 2, 0, 1) \
V(I8x16AddSaturateS, Operator::kCommutative, 2, 0, 1) \
V(I8x16Sub, Operator::kNoProperties, 2, 0, 1) \
......@@ -301,6 +312,7 @@ MachineType AtomicCompareExchangeRepresentationOf(Operator const* op) {
V(I8x16Ne, Operator::kCommutative, 2, 0, 1) \
V(I8x16LtS, Operator::kNoProperties, 2, 0, 1) \
V(I8x16LeS, Operator::kNoProperties, 2, 0, 1) \
V(I8x16UConvertI16x8, Operator::kNoProperties, 2, 0, 1) \
V(I8x16AddSaturateU, Operator::kCommutative, 2, 0, 1) \
V(I8x16SubSaturateU, Operator::kNoProperties, 2, 0, 1) \
V(I8x16MinU, Operator::kCommutative, 2, 0, 1) \
......
src/compiler/machine-operator.h
View file @ dbfc0300
......@@ -465,6 +465,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* I32x4ExtractLane(int32_t);
const Operator* I32x4ReplaceLane(int32_t);
const Operator* I32x4SConvertF32x4();
const Operator* I32x4SConvertI16x8Low();
const Operator* I32x4SConvertI16x8High();
const Operator* I32x4Neg();
const Operator* I32x4Shl(int32_t);
const Operator* I32x4ShrS(int32_t);
......@@ -479,6 +481,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* I32x4LeS();
const Operator* I32x4UConvertF32x4();
const Operator* I32x4UConvertI16x8Low();
const Operator* I32x4UConvertI16x8High();
const Operator* I32x4ShrU(int32_t);
const Operator* I32x4MinU();
const Operator* I32x4MaxU();
......@@ -488,9 +492,12 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* I16x8Splat();
const Operator* I16x8ExtractLane(int32_t);
const Operator* I16x8ReplaceLane(int32_t);
const Operator* I16x8SConvertI8x16Low();
const Operator* I16x8SConvertI8x16High();
const Operator* I16x8Neg();
const Operator* I16x8Shl(int32_t);
const Operator* I16x8ShrS(int32_t);
const Operator* I16x8SConvertI32x4();
const Operator* I16x8Add();
const Operator* I16x8AddSaturateS();
const Operator* I16x8Sub();
......@@ -503,7 +510,10 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* I16x8LtS();
const Operator* I16x8LeS();
const Operator* I16x8UConvertI8x16Low();
const Operator* I16x8UConvertI8x16High();
const Operator* I16x8ShrU(int32_t);
const Operator* I16x8UConvertI32x4();
const Operator* I16x8AddSaturateU();
const Operator* I16x8SubSaturateU();
const Operator* I16x8MinU();
......@@ -517,6 +527,7 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* I8x16Neg();
const Operator* I8x16Shl(int32_t);
const Operator* I8x16ShrS(int32_t);
const Operator* I8x16SConvertI16x8();
const Operator* I8x16Add();
const Operator* I8x16AddSaturateS();
const Operator* I8x16Sub();
......@@ -530,6 +541,7 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* I8x16LeS();
const Operator* I8x16ShrU(int32_t);
const Operator* I8x16UConvertI16x8();
const Operator* I8x16AddSaturateU();
const Operator* I8x16SubSaturateU();
const Operator* I8x16MinU();
......
src/compiler/opcodes.h
View file @ dbfc0300
......@@ -593,6 +593,8 @@
V(I32x4ExtractLane) \
V(I32x4ReplaceLane) \
V(I32x4SConvertF32x4) \
V(I32x4SConvertI16x8Low) \
V(I32x4SConvertI16x8High) \
V(I32x4Neg) \
V(I32x4Shl) \
V(I32x4ShrS) \
......@@ -608,6 +610,8 @@
V(I32x4GtS) \
V(I32x4GeS) \
V(I32x4UConvertF32x4) \
V(I32x4UConvertI16x8Low) \
V(I32x4UConvertI16x8High) \
V(I32x4ShrU) \
V(I32x4MinU) \
V(I32x4MaxU) \
......@@ -618,9 +622,12 @@
V(I16x8Splat) \
V(I16x8ExtractLane) \
V(I16x8ReplaceLane) \
V(I16x8SConvertI8x16Low) \
V(I16x8SConvertI8x16High) \
V(I16x8Neg) \
V(I16x8Shl) \
V(I16x8ShrS) \
V(I16x8SConvertI32x4) \
V(I16x8Add) \
V(I16x8AddSaturateS) \
V(I16x8Sub) \
......@@ -634,9 +641,12 @@
V(I16x8LeS) \
V(I16x8GtS) \
V(I16x8GeS) \
V(I16x8UConvertI8x16Low) \
V(I16x8UConvertI8x16High) \
V(I16x8ShrU) \
V(I16x8UConvertI32x4) \
V(I16x8AddSaturateU) \
V(I16x8SubSaturateU) \
V(I16x8ShrU) \
V(I16x8MinU) \
V(I16x8MaxU) \
V(I16x8LtU) \
......@@ -646,6 +656,7 @@
V(I8x16Splat) \
V(I8x16ExtractLane) \
V(I8x16ReplaceLane) \
V(I8x16SConvertI16x8) \
V(I8x16Neg) \
V(I8x16Shl) \
V(I8x16ShrS) \
......@@ -662,6 +673,7 @@
V(I8x16LeS) \
V(I8x16GtS) \
V(I8x16GeS) \
V(I8x16UConvertI16x8) \
V(I8x16AddSaturateU) \
V(I8x16SubSaturateU) \
V(I8x16ShrU) \
......
src/compiler/wasm-compiler.cc
View file @ dbfc0300
......@@ -3246,6 +3246,12 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
case wasm::kExprI32x4UConvertF32x4:
return graph()->NewNode(jsgraph()->machine()->I32x4UConvertF32x4(),
inputs[0]);
case wasm::kExprI32x4SConvertI16x8Low:
return graph()->NewNode(jsgraph()->machine()->I32x4SConvertI16x8Low(),
inputs[0]);
case wasm::kExprI32x4SConvertI16x8High:
return graph()->NewNode(jsgraph()->machine()->I32x4SConvertI16x8High(),
inputs[0]);
case wasm::kExprI32x4Neg:
return graph()->NewNode(jsgraph()->machine()->I32x4Neg(), inputs[0]);
case wasm::kExprI32x4Add:
......@@ -3281,6 +3287,12 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
case wasm::kExprI32x4GeS:
return graph()->NewNode(jsgraph()->machine()->I32x4LeS(), inputs[1],
inputs[0]);
case wasm::kExprI32x4UConvertI16x8Low:
return graph()->NewNode(jsgraph()->machine()->I32x4UConvertI16x8Low(),
inputs[0]);
case wasm::kExprI32x4UConvertI16x8High:
return graph()->NewNode(jsgraph()->machine()->I32x4UConvertI16x8High(),
inputs[0]);
case wasm::kExprI32x4MinU:
return graph()->NewNode(jsgraph()->machine()->I32x4MinU(), inputs[0],
inputs[1]);
......@@ -3301,8 +3313,17 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
inputs[0]);
case wasm::kExprI16x8Splat:
return graph()->NewNode(jsgraph()->machine()->I16x8Splat(), inputs[0]);
case wasm::kExprI16x8SConvertI8x16Low:
return graph()->NewNode(jsgraph()->machine()->I16x8SConvertI8x16Low(),
inputs[0]);
case wasm::kExprI16x8SConvertI8x16High:
return graph()->NewNode(jsgraph()->machine()->I16x8SConvertI8x16High(),
inputs[0]);
case wasm::kExprI16x8Neg:
return graph()->NewNode(jsgraph()->machine()->I16x8Neg(), inputs[0]);
case wasm::kExprI16x8SConvertI32x4:
return graph()->NewNode(jsgraph()->machine()->I16x8SConvertI32x4(),
inputs[0], inputs[1]);
case wasm::kExprI16x8Add:
return graph()->NewNode(jsgraph()->machine()->I16x8Add(), inputs[0],
inputs[1]);
......@@ -3342,6 +3363,15 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
case wasm::kExprI16x8GeS:
return graph()->NewNode(jsgraph()->machine()->I16x8LeS(), inputs[1],
inputs[0]);
case wasm::kExprI16x8UConvertI8x16Low:
return graph()->NewNode(jsgraph()->machine()->I16x8UConvertI8x16Low(),
inputs[0]);
case wasm::kExprI16x8UConvertI8x16High:
return graph()->NewNode(jsgraph()->machine()->I16x8UConvertI8x16High(),
inputs[0]);
case wasm::kExprI16x8UConvertI32x4:
return graph()->NewNode(jsgraph()->machine()->I16x8UConvertI32x4(),
inputs[0], inputs[1]);
case wasm::kExprI16x8AddSaturateU:
return graph()->NewNode(jsgraph()->machine()->I16x8AddSaturateU(),
inputs[0], inputs[1]);
......@@ -3370,6 +3400,9 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
return graph()->NewNode(jsgraph()->machine()->I8x16Splat(), inputs[0]);
case wasm::kExprI8x16Neg:
return graph()->NewNode(jsgraph()->machine()->I8x16Neg(), inputs[0]);
case wasm::kExprI8x16SConvertI16x8:
return graph()->NewNode(jsgraph()->machine()->I8x16SConvertI16x8(),
inputs[0], inputs[1]);
case wasm::kExprI8x16Add:
return graph()->NewNode(jsgraph()->machine()->I8x16Add(), inputs[0],
inputs[1]);
......@@ -3409,6 +3442,9 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
case wasm::kExprI8x16GeS:
return graph()->NewNode(jsgraph()->machine()->I8x16LeS(), inputs[1],
inputs[0]);
case wasm::kExprI8x16UConvertI16x8:
return graph()->NewNode(jsgraph()->machine()->I8x16UConvertI16x8(),
inputs[0], inputs[1]);
case wasm::kExprI8x16AddSaturateU:
return graph()->NewNode(jsgraph()->machine()->I8x16AddSaturateU(),
inputs[0], inputs[1]);
......
src/wasm/wasm-opcodes.cc
View file @ dbfc0300
......@@ -191,6 +191,12 @@ const char* WasmOpcodes::OpcodeName(WasmOpcode opcode) {
CASE_F32x4_OP(Ge, "ge")
CASE_CONVERT_OP(Convert, F32x4, I32x4, "i32", "convert")
CASE_CONVERT_OP(Convert, I32x4, F32x4, "f32", "convert")
CASE_CONVERT_OP(Convert, I32x4, I16x8Low, "i32", "convert")
CASE_CONVERT_OP(Convert, I32x4, I16x8High, "i32", "convert")
CASE_CONVERT_OP(Convert, I16x8, I32x4, "i32", "convert")
CASE_CONVERT_OP(Convert, I16x8, I8x16Low, "i32", "convert")
CASE_CONVERT_OP(Convert, I16x8, I8x16High, "i32", "convert")
CASE_CONVERT_OP(Convert, I8x16, I16x8, "i32", "convert")
CASE_F32x4_OP(ExtractLane, "extract_lane")
CASE_F32x4_OP(ReplaceLane, "replace_lane")
CASE_SIMDI_OP(ExtractLane, "extract_lane")
......
src/wasm/wasm-opcodes.h
View file @ dbfc0300
......@@ -321,13 +321,17 @@ constexpr WasmCodePosition kNoCodePosition = -1;
V(I32x4GtS, 0xe52a, s1x4_ss) \
V(I32x4GeS, 0xe52b, s1x4_ss) \
V(I32x4SConvertF32x4, 0xe52f, s_s) \
V(I32x4UConvertF32x4, 0xe537, s_s) \
V(I32x4SConvertI16x8Low, 0xe594, s_s) \
V(I32x4SConvertI16x8High, 0xe595, s_s) \
V(I32x4UConvertI16x8Low, 0xe596, s_s) \
V(I32x4UConvertI16x8High, 0xe597, s_s) \
V(I32x4MinU, 0xe530, s_ss) \
V(I32x4MaxU, 0xe531, s_ss) \
V(I32x4LtU, 0xe533, s1x4_ss) \
V(I32x4LeU, 0xe534, s1x4_ss) \
V(I32x4GtU, 0xe535, s1x4_ss) \
V(I32x4GeU, 0xe536, s1x4_ss) \
V(I32x4UConvertF32x4, 0xe537, s_s) \
V(I16x8Splat, 0xe538, s_i) \
V(I16x8Neg, 0xe53b, s_s) \
V(I16x8Add, 0xe53c, s_ss) \
......@@ -351,6 +355,12 @@ constexpr WasmCodePosition kNoCodePosition = -1;
V(I16x8LeU, 0xe554, s1x8_ss) \
V(I16x8GtU, 0xe555, s1x8_ss) \
V(I16x8GeU, 0xe556, s1x8_ss) \
V(I16x8SConvertI32x4, 0xe598, s_ss) \
V(I16x8UConvertI32x4, 0xe599, s_ss) \
V(I16x8SConvertI8x16Low, 0xe59a, s_s) \
V(I16x8SConvertI8x16High, 0xe59b, s_s) \
V(I16x8UConvertI8x16Low, 0xe59c, s_s) \
V(I16x8UConvertI8x16High, 0xe59d, s_s) \
V(I8x16Splat, 0xe557, s_i) \
V(I8x16Neg, 0xe55a, s_s) \
V(I8x16Add, 0xe55b, s_ss) \
......@@ -374,6 +384,8 @@ constexpr WasmCodePosition kNoCodePosition = -1;
V(I8x16LeU, 0xe573, s1x16_ss) \
V(I8x16GtU, 0xe574, s1x16_ss) \
V(I8x16GeU, 0xe575, s1x16_ss) \
V(I8x16SConvertI16x8, 0xe59e, s_ss) \
V(I8x16UConvertI16x8, 0xe59f, s_ss) \
V(S128And, 0xe576, s_ss) \
V(S128Or, 0xe577, s_ss) \
V(S128Xor, 0xe578, s_ss) \
......
test/cctest/wasm/test-run-wasm-simd.cc
View file @ dbfc0300
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