[wasm-simd] Implement f64x2 add sub mul div for arm

Bug: v8:9813
Change-Id: Idee4daded322731648fe51e75f3b9e8be2dcd0d6
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1872929Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64488}

src/compiler/backend/arm/code-generator-arm.cc

@@ -494,6 +494,14 @@ void ComputePoisonedAddressForLoad(CodeGenerator* codegen,
     }                                                     \
   } while (0)
 
+#define ASSEMBLE_F64X2_ARITHMETIC_BINOP(op)                                   \
+  do {                                                                        \
+    __ op(i.OutputSimd128Register().low(), i.InputSimd128Register(0).low(),   \
+          i.InputSimd128Register(1).low());                                   \
+    __ op(i.OutputSimd128Register().high(), i.InputSimd128Register(0).high(), \
+          i.InputSimd128Register(1).high());                                  \
+  } while (0)
+
 void CodeGenerator::AssembleDeconstructFrame() {
   __ LeaveFrame(StackFrame::MANUAL);
   unwinding_info_writer_.MarkFrameDeconstructed(__ pc_offset());
@@ -1799,6 +1807,23 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
                i.InputSimd128Register(0).high());
       break;
     }
+    case kArmF64x2Add: {
+      ASSEMBLE_F64X2_ARITHMETIC_BINOP(vadd);
+      break;
+    }
+    case kArmF64x2Sub: {
+      ASSEMBLE_F64X2_ARITHMETIC_BINOP(vsub);
+      break;
+    }
+    case kArmF64x2Mul: {
+      ASSEMBLE_F64X2_ARITHMETIC_BINOP(vmul);
+      break;
+    }
+    case kArmF64x2Div: {
+      ASSEMBLE_F64X2_ARITHMETIC_BINOP(vdiv);
+      break;
+    }
+#undef ASSEMBLE_F64X2_ARITHMETIC_BINOP
     case kArmF32x4Splat: {
       int src_code = i.InputFloatRegister(0).code();
       __ vdup(Neon32, i.OutputSimd128Register(),

src/compiler/backend/arm/instruction-codes-arm.h

@@ -134,6 +134,10 @@ namespace compiler {
   V(ArmF64x2Abs)                   \
   V(ArmF64x2Neg)                   \
   V(ArmF64x2Sqrt)                  \
+  V(ArmF64x2Add)                   \
+  V(ArmF64x2Sub)                   \
+  V(ArmF64x2Mul)                   \
+  V(ArmF64x2Div)                   \
   V(ArmF32x4Splat)                 \
   V(ArmF32x4ExtractLane)           \
   V(ArmF32x4ReplaceLane)           \

src/compiler/backend/arm/instruction-scheduler-arm.cc

@@ -114,6 +114,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArmF64x2Abs:
     case kArmF64x2Neg:
     case kArmF64x2Sqrt:
+    case kArmF64x2Add:
+    case kArmF64x2Sub:
+    case kArmF64x2Mul:
+    case kArmF64x2Div:
     case kArmF32x4Splat:
     case kArmF32x4ExtractLane:
     case kArmF32x4ReplaceLane:

src/compiler/backend/arm/instruction-selector-arm.cc

@@ -2424,6 +2424,10 @@ void InstructionSelector::VisitWord32AtomicPairCompareExchange(Node* node) {
   V(I8x16ShrU)
 
 #define SIMD_BINOP_LIST(V)                      \
+  V(F64x2Add, kArmF64x2Add)                     \
+  V(F64x2Sub, kArmF64x2Sub)                     \
+  V(F64x2Mul, kArmF64x2Mul)                     \
+  V(F64x2Div, kArmF64x2Div)                     \
   V(F32x4Add, kArmF32x4Add)                     \
   V(F32x4AddHoriz, kArmF32x4AddHoriz)           \
   V(F32x4Sub, kArmF32x4Sub)                     \

src/compiler/backend/instruction-selector.cc

@@ -2648,10 +2648,6 @@ void InstructionSelector::VisitF64x2UConvertI64x2(Node* node) {
 }
 #if !V8_TARGET_ARCH_ARM64
 #if !V8_TARGET_ARCH_IA32
-void InstructionSelector::VisitF64x2Add(Node* node) { UNIMPLEMENTED(); }
-void InstructionSelector::VisitF64x2Sub(Node* node) { UNIMPLEMENTED(); }
-void InstructionSelector::VisitF64x2Mul(Node* node) { UNIMPLEMENTED(); }
-void InstructionSelector::VisitF64x2Div(Node* node) { UNIMPLEMENTED(); }
 void InstructionSelector::VisitF64x2Eq(Node* node) { UNIMPLEMENTED(); }
 void InstructionSelector::VisitF64x2Ne(Node* node) { UNIMPLEMENTED(); }
 void InstructionSelector::VisitF64x2Lt(Node* node) { UNIMPLEMENTED(); }

test/cctest/wasm/test-run-wasm-simd.cc

@@ -1301,7 +1301,6 @@ WASM_SIMD_TEST_NO_LOWERING(F64x2Sqrt) {
   RunF64x2UnOpTest(execution_tier, lower_simd, kExprF64x2Sqrt, Sqrt);
 }
 
-#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_IA32
 void RunF64x2BinOpTest(ExecutionTier execution_tier, LowerSimd lower_simd,
                        WasmOpcode opcode, DoubleBinOp expected_op) {
   WasmRunner<int32_t, double, double> r(execution_tier, lower_simd);
@@ -1365,6 +1364,7 @@ WASM_SIMD_TEST_NO_LOWERING(F64x2Div) {
   RunF64x2BinOpTest(execution_tier, lower_simd, kExprF64x2Div, Div);
 }
 
+#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_IA32
 void RunF64x2CompareOpTest(ExecutionTier execution_tier, LowerSimd lower_simd,
                            WasmOpcode opcode, DoubleCompareOp expected_op) {
   WasmRunner<int32_t, double, double> r(execution_tier, lower_simd);