[wasm-simd] Implement v128.andnot for arm

Bug: v8:10082
Change-Id: Ieabb0ebeec14091844b3d30b9b1684a249db7bdc
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1980949Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#65824}

src/codegen/arm/assembler-arm.cc

@@ -4036,6 +4036,15 @@ void Assembler::vand(QwNeonRegister dst, QwNeonRegister src1,
                                  src2.code()));
 }
 
+void Assembler::vbic(QwNeonRegister dst, QwNeonRegister src1,
+                     QwNeonRegister src2) {
+  // Qd = vbic(Qn, Qm) SIMD AND.
+  // Instruction details available in ARM DDI 0406C.b, A8-840.
+  DCHECK(IsEnabled(NEON));
+  emit(EncodeNeonBinaryBitwiseOp(VBIC, NEON_Q, dst.code(), src1.code(),
+                                 src2.code()));
+}
+
 void Assembler::vbsl(QwNeonRegister dst, QwNeonRegister src1,
                      QwNeonRegister src2) {
   // Qd = vbsl(Qn, Qm) SIMD bitwise select.

src/codegen/arm/assembler-arm.h

@@ -873,6 +873,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
   void vneg(NeonSize size, QwNeonRegister dst, QwNeonRegister src);
 
   void vand(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
+  void vbic(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
   void veor(DwVfpRegister dst, DwVfpRegister src1, DwVfpRegister src2);
   void veor(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
   void vbsl(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);

src/compiler/backend/arm/code-generator-arm.cc

@@ -2666,6 +2666,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vbsl(dst, i.InputSimd128Register(1), i.InputSimd128Register(2));
       break;
     }
+    case kArmS128AndNot: {
+      __ vbic(i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputSimd128Register(1));
+      break;
+    }
     case kArmS32x4ZipLeft: {
       Simd128Register dst = i.OutputSimd128Register(),
                       src1 = i.InputSimd128Register(1);

src/compiler/backend/arm/instruction-codes-arm.h

@@ -268,6 +268,7 @@ namespace compiler {
   V(ArmS128Xor)                    \
   V(ArmS128Not)                    \
   V(ArmS128Select)                 \
+  V(ArmS128AndNot)                 \
   V(ArmS32x4ZipLeft)               \
   V(ArmS32x4ZipRight)              \
   V(ArmS32x4UnzipLeft)             \

src/compiler/backend/arm/instruction-scheduler-arm.cc

@@ -248,6 +248,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArmS128Xor:
     case kArmS128Not:
     case kArmS128Select:
+    case kArmS128AndNot:
     case kArmS32x4ZipLeft:
     case kArmS32x4ZipRight:
     case kArmS32x4UnzipLeft:

src/compiler/backend/arm/instruction-selector-arm.cc

@@ -2571,7 +2571,8 @@ void InstructionSelector::VisitWord32AtomicPairCompareExchange(Node* node) {
   V(I8x16RoundingAverageU, kArmI8x16RoundingAverageU) \
   V(S128And, kArmS128And)                             \
   V(S128Or, kArmS128Or)                               \
-  V(S128Xor, kArmS128Xor)
+  V(S128Xor, kArmS128Xor)                             \
+  V(S128AndNot, kArmS128AndNot)
 
 void InstructionSelector::VisitS128Zero(Node* node) {
   ArmOperandGenerator g(this);

src/compiler/backend/instruction-selector.cc

@@ -2632,7 +2632,9 @@ void InstructionSelector::VisitF64x2SConvertI64x2(Node* node) {
 void InstructionSelector::VisitF64x2UConvertI64x2(Node* node) {
   UNIMPLEMENTED();
 }
+#if !V8_TARGET_ARCH_ARM
 void InstructionSelector::VisitS128AndNot(Node* node) { UNIMPLEMENTED(); }
+#endif  // !V8_TARGET_ARCH_ARM
 #if !V8_TARGET_ARCH_IA32
 void InstructionSelector::VisitI64x2Mul(Node* node) { UNIMPLEMENTED(); }
 #endif  // !V8_TARGET_ARCH_IA32

src/diagnostics/arm/disasm-arm.cc

@@ -1861,6 +1861,11 @@ void Decoder::DecodeSpecialCondition(Instruction* instr) {
               out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                           "vorr q%d, q%d, q%d", Vd, Vn, Vm);
             }
+          } else if (instr->Bits(21, 20) == 1 && instr->Bit(6) == 1 &&
+                     instr->Bit(4) == 1) {
+            // vbic Qd, Qn, Qm
+            out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
+                                        "vbic q%d, q%d, q%d", Vd, Vn, Vm);
           } else if (instr->Bits(21, 20) == 0 && instr->Bit(6) == 1 &&
                      instr->Bit(4) == 1) {
             // vand Qd, Qm, Qn.

src/execution/arm/simulator-arm.cc

@@ -4301,6 +4301,16 @@ void Simulator::DecodeSpecialCondition(Instruction* instr) {
               src1[i] = src1[i] & src2[i];
             }
             set_neon_register(Vd, src1);
+          } else if (instr->Bits(21, 20) == 1 && instr->Bit(6) == 1 &&
+                     instr->Bit(4) == 1) {
+            // vbic Qd, Qm, Qn.
+            uint32_t src1[4], src2[4];
+            get_neon_register(Vn, src1);
+            get_neon_register(Vm, src2);
+            for (int i = 0; i < 4; i++) {
+              src1[i] = src1[i] & ~src2[i];
+            }
+            set_neon_register(Vd, src1);
           } else {
             UNIMPLEMENTED();
           }

test/cctest/test-disasm-arm.cc

@@ -1107,6 +1107,8 @@ TEST(Neon) {
               "f340e170       veor q15, q0, q8");
       COMPARE(vand(q15, q0, q8),
               "f240e170       vand q15, q0, q8");
+      COMPARE(vbic(q15, q0, q8),
+              "f250e170       vbic q15, q0, q8");
       COMPARE(vorr(q15, q0, q8),
               "f260e170       vorr q15, q0, q8");
       COMPARE(vmin(q15, q0, q8),

test/cctest/wasm/test-run-wasm-simd.cc

@@ -1912,12 +1912,12 @@ WASM_SIMD_TEST(S128Xor) {
   RunI32x4BinOpTest(execution_tier, lower_simd, kExprS128Xor, Xor);
 }
 
-#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
+#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_ARM
 // Bitwise operation, doesn't really matter what simd type we test it with.
 WASM_SIMD_TEST_NO_LOWERING(S128AndNot) {
   RunI32x4BinOpTest(execution_tier, lower_simd, kExprS128AndNot, AndNot);
 }
-#endif  // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
+#endif  // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_ARM
 
 WASM_SIMD_TEST(I32x4Eq) {
   RunI32x4BinOpTest(execution_tier, lower_simd, kExprI32x4Eq, Equal);