- 09 Feb, 2021 1 commit
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Ng Zhi An authored
Bug: v8:11347,v8:11348,chromium:1174498 Change-Id: I9afaacefcab55a6d7eb48f6e9d1848b714f64eb6 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2666147Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#72603}
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- 19 Jan, 2021 1 commit
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Seth Brenith authored
On arm64, Windows Performance Recorder gets confused by the fact that fp in Builtins_JSEntry doesn't point to the saved {fp, lr} pair for the caller frame. The expected usage of fp is documented in [1]: The frame pointer (x29) is required for compatibility with fast stack walking used by ETW and other services. It must point to the previous {x29, x30} pair on the stack. In slightly more detail, the Windows function RtlWalkFrameChain is responsible for generating stack traces during profiling with Windows Performance Recorder, and that function relies on the rule quoted above. Notably, it does not make any effort to read the unwinding data that one could obtain with RtlLookupFunctionEntry. Stack walks using that data, such as those performed by WinDbg and the cctest StackUnwindingWin64, work fine. It would be convenient if we could use fp in a more standard way during JSEntry so that Windows profiling tools work correctly. (We can also reduce JSEntry by two instructions in doing so.) Both arm and arm64 currently put a -1 value on the stack at the location that fp points to. This could prevent accidental access during the epilog of JSEntry, where fp might be zero. However, we believe that this protection is no longer necessary, and any bug that causes a read from fp during the end of JSEntry would cause various CQ failures. [1] https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions?view=msvc-160 Change-Id: Iece5666129b9188fc4c12007809b50f046f4044f Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2607636 Commit-Queue: Seth Brenith <seth.brenith@microsoft.com> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Ross McIlroy <rmcilroy@chromium.org> Cr-Commit-Position: refs/heads/master@{#72165}
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- 12 Jan, 2021 1 commit
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Zhi An Ng authored
Removing ifdef guards since our 4 supported architectures implement this now. Bug: v8:10971 Change-Id: Ic0295b1492a6316df61340a38f3e6d06d8fe64ed Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2620900 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Cr-Commit-Position: refs/heads/master@{#72023}
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- 14 Dec, 2020 1 commit
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Zhi An Ng authored
This is the same as the original implementation in https://crrev.com/c/2567534 which was speculatively reverted due to flaky tests. Since then, there have been some changes to fix those tests, so trying to get this in again. Bug: v8:11002 Change-Id: I5bd0f63d3aec4cf6db403b35737f8b695b0f4e37 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2589063Reviewed-by:
Bill Budge <bbudge@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#71746}
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- 10 Dec, 2020 1 commit
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Zhi An Ng authored
Implement vclt and add some assembler tests. Bug: v8:10983 Change-Id: I78c701180ddc90af4b59db86a25188f281167366 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2575783 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Cr-Commit-Position: refs/heads/master@{#71685}
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- 09 Dec, 2020 2 commits
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Zhi An Ng authored
Add new instruction vpaddl for signed and unsigned integers, adding assembler, disassembler, simulator support, and also tests. The signed and unsigned opcodes for vpaddl are separate enums, because the helper EncodeNeonUnaryOp only takes a NeonSize (not NeonDataType). I considered changing the signature, but none of the other instructions use a NeonDataType, so it seems unnecessary. Bug: v8:11086 Change-Id: I5e6694ae407779c1fd3604c5a40ca0a1b6ce061b Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2578233Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#71671}
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Zhi An Ng authored
Add a new option to disassembler NEON size encoded in instructions with two registers, 'size2. Rename the current only to 'size3. Clean up existing operations to use this new formatting option. Bug: v8:11074 Change-Id: Ie309d93d24602439c3293c8bbfd6c2ecbc9fdfb7 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2575786Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#71670}
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- 07 Dec, 2020 1 commit
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Zhi An Ng authored
Prototype v128.{load,store}{8,16,32,64}_lane on arm. Bug: v8:10975 Change-Id: I649f567f39f8a5ba6992a86b761f93f62619c139 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2565079 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#71628}
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- 03 Dec, 2020 2 commits
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Zhi An Ng authored
This reverts commit d0f7c6a8. Reason for revert: Causing flaky tests https://ci.chromium.org/ui/p/v8/builders/ci/V8%20Mac64%20-%20debug/31929/overview Original change's description: > Reland "[wasm-simd][arm] Prototype i8x16.popcnt" > > This is a reland of e2aa734a > > The original change was speculatively reverted in > https://crrev.com/c/2568925 but seems unrelated to the flakey > test failures (which are on x64). > > Original change's description: > > [wasm-simd][arm] Prototype i8x16.popcnt > > > > Bug: v8:11002 > > Change-Id: Ib97e51ed52249a1af7a4b879396b70a016991719 > > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2567534 > > Commit-Queue: Zhi An Ng <zhin@chromium.org> > > Reviewed-by: Bill Budge <bbudge@chromium.org> > > Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> > > Cr-Commit-Position: refs/heads/master@{#71552} > > Bug: v8:11002 > Change-Id: I714918e2640d27d29953f940e3bedeb9ea2f8a08 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2567243 > Commit-Queue: Zhi An Ng <zhin@chromium.org> > Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> > Reviewed-by: Bill Budge <bbudge@chromium.org> > Cr-Commit-Position: refs/heads/master@{#71585} TBR=bbudge@chromium.org,jkummerow@chromium.org,v8-arm-ports@googlegroups.com,zhin@chromium.org Change-Id: Ib8454a4c20937495c2b83b7ceb3ad594b1b9e7e5 No-Presubmit: true No-Tree-Checks: true No-Try: true Bug: v8:11002 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2569559Reviewed-by:
Zhi An Ng <zhin@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#71586}
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Zhi An Ng authored
This is a reland of e2aa734a The original change was speculatively reverted in https://crrev.com/c/2568925 but seems unrelated to the flakey test failures (which are on x64). Original change's description: > [wasm-simd][arm] Prototype i8x16.popcnt > > Bug: v8:11002 > Change-Id: Ib97e51ed52249a1af7a4b879396b70a016991719 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2567534 > Commit-Queue: Zhi An Ng <zhin@chromium.org> > Reviewed-by: Bill Budge <bbudge@chromium.org> > Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> > Cr-Commit-Position: refs/heads/master@{#71552} Bug: v8:11002 Change-Id: I714918e2640d27d29953f940e3bedeb9ea2f8a08 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2567243 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Cr-Commit-Position: refs/heads/master@{#71585}
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- 02 Dec, 2020 2 commits
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Sathya Gunasekaran authored
This reverts commit e2aa734a. Reason for revert: speculative revert for https://ci.chromium.org/ui/p/v8/builders/ci/V8%20Mac64%20-%20debug/31901/blamelist Original change's description: > [wasm-simd][arm] Prototype i8x16.popcnt > > Bug: v8:11002 > Change-Id: Ib97e51ed52249a1af7a4b879396b70a016991719 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2567534 > Commit-Queue: Zhi An Ng <zhin@chromium.org> > Reviewed-by: Bill Budge <bbudge@chromium.org> > Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> > Cr-Commit-Position: refs/heads/master@{#71552} TBR=bbudge@chromium.org,jkummerow@chromium.org,v8-arm-ports@googlegroups.com,zhin@chromium.org Change-Id: Id1ae2dbaae52d45eb81ba8636178236ca8e9f7e0 No-Presubmit: true No-Tree-Checks: true No-Try: true Bug: v8:11002 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2568925Reviewed-by:
Sathya Gunasekaran <gsathya@chromium.org> Commit-Queue: Sathya Gunasekaran <gsathya@chromium.org> Cr-Commit-Position: refs/heads/master@{#71554}
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Zhi An Ng authored
Bug: v8:11002 Change-Id: Ib97e51ed52249a1af7a4b879396b70a016991719 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2567534 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#71552}
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- 30 Nov, 2020 2 commits
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Zhi An Ng authored
Bug: v8:11074 Change-Id: I478f4390523ddf7cfb87dd22cef5ed331be5c875 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2558267Reviewed-by:
Andreas Haas <ahaas@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#71468}
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Zhi An Ng authored
This is a reland of 21e47944 The fix is in the encoding of vmov. Bit 23 (the U bit) should be 0, whether the NeonDataType is NeonS32 or NeonU32. Also added a DCHECK in the simulator to assert this. Original change's description: > [wasm-simd][arm] Prototype i64x2.bitmask > > Cleanup to simulator to remove repetitive logic to get instruction > fields. > > Bug: v8:10997 > Change-Id: I01f0b99f85788b41e4cab505fc94362d637c396f > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2554256 > Commit-Queue: Zhi An Ng <zhin@chromium.org> > Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> > Reviewed-by: Bill Budge <bbudge@chromium.org> > Cr-Commit-Position: refs/heads/master@{#71391} Bug: v8:10997 Change-Id: I93b5d2168a50446d4a3b487ad83d6af8ea9ba8ab Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2558262 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#71467}
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- 25 Nov, 2020 2 commits
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Zhi An Ng authored
This reverts commit 21e47944. Reason for revert: Broke build https://ci.chromium.org/p/v8/builders/ci/V8%20Arm%20-%20debug/16872? Original change's description: > [wasm-simd][arm] Prototype i64x2.bitmask > > Cleanup to simulator to remove repetitive logic to get instruction > fields. > > Bug: v8:10997 > Change-Id: I01f0b99f85788b41e4cab505fc94362d637c396f > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2554256 > Commit-Queue: Zhi An Ng <zhin@chromium.org> > Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> > Reviewed-by: Bill Budge <bbudge@chromium.org> > Cr-Commit-Position: refs/heads/master@{#71391} TBR=bbudge@chromium.org,jkummerow@chromium.org,v8-arm-ports@googlegroups.com,zhin@chromium.org Change-Id: I15513cc5923db7d189d08a9faf5051e57af7190b No-Presubmit: true No-Tree-Checks: true No-Try: true Bug: v8:10997 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2558260Reviewed-by:
Zhi An Ng <zhin@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#71393}
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Zhi An Ng authored
Cleanup to simulator to remove repetitive logic to get instruction fields. Bug: v8:10997 Change-Id: I01f0b99f85788b41e4cab505fc94362d637c396f Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2554256 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Cr-Commit-Position: refs/heads/master@{#71391}
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- 24 Nov, 2020 1 commit
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Zhi An Ng authored
Currently we only correctly disassemble encoding A4, with a list of 4 regs. Also added tests for these encodings. Change-Id: I38066186d19deb8c180129d7a92b49bc589315cd Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2554258Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#71350}
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- 02 Nov, 2020 1 commit
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Zhi An Ng authored
Bug: v8:11038 Change-Id: Ifb50d8667b03afa045a957ffc8f3df799252e561 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2500939Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#70907}
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- 28 Oct, 2020 2 commits
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Zhi An Ng authored
Introduce a new option for Format, 'size, to print element sizes for Advanced SIMD instructions. Then convert some disassembly to use this new Format option. Bug: v8:10933 Change-Id: I9eab0e3f6d951c315c49b723db01bcdc93dbde02 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2504856Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#70861}
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Zhi An Ng authored
We can move the esize (element size) calculation into the other scope, since all but 1 instruction share this. Bug: v8:10933 Change-Id: I43cfef46fdf7e962d54c29949488c2a7c0900334 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2504854Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#70860}
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- 27 Oct, 2020 3 commits
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Zhi An Ng authored
Bug: v8:10933 Change-Id: I4a889b087b4d33111533b8b04f151c8ac0fce042 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2497397 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#70780}
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Zhi An Ng authored
Implement these two instructions on arm. Bug: v8:11038 Change-Id: I23d9c7291f60e29415cfbebced1bff323fd2465a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2485250 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Cr-Commit-Position: refs/heads/master@{#70779}
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Zhi An Ng authored
The SpecialValue field used in the disassembler covers too wide a range, this causes some duplication in the disassembler of instructions like mov, since the SpecialValue includes a bit used for the immediate. Attempt to refactor and follow the decoding guide given in the architecture manual [0], F4.1 A32 instruction set encoding, with the eventual goal for removing the duplicated instruction disassembly. [0] ARM DDI 0487F.b ARMv8 A32 instruction set Bug: v8:10933 Change-Id: Iddf4df317f9a5b29be2544ad2f9f93180e9bcdfc Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2497395 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#70775}
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- 20 Oct, 2020 1 commit
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Santiago Aboy Solanes authored
Bug: v8:10799 Change-Id: Id912520b6a27e439e204bac47c0723a8f613be4b Fixed: v8:10799 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2472000 Commit-Queue: Santiago Aboy Solanes <solanes@chromium.org> Reviewed-by:
Ulan Degenbaev <ulan@chromium.org> Reviewed-by:
Ross McIlroy <rmcilroy@chromium.org> Cr-Commit-Position: refs/heads/master@{#70656}
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- 11 Aug, 2020 1 commit
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Ng Zhi An authored
This is a reland of 57242a05 no-sse4.1 builds were failing due to missing simd-scalar-lowering for s128.const, this reland adds that implementation. Original change's description: > [wasm-simd][arm] Use vmov to move all ones to register > > vceq(dst, dst, dst) does not seem to always set the register to all > ones. The right way should be be to use vmov (immediate) anyway. This > was not supported in the assembler yet, so we need changes to the > assembler, diassembler, and simulator. > > There is an unfortunate fork in logic in the simulator, due to the way > the switches are set up, vmov (imm) logic is duplicated across two > different cases, because the switch looks at the top bit of the > immediate. Refactoring this will be a bigger change that is irrelevant > for this bug, so I'm putting that off for now. Instead we extract the > core of vmov (imm) into helpers and call it in the two cases. > > Bug: chromium:1112124 > Change-Id: I283dbcd86cb0572e5ee720835f897b51fae96701 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2337503 > Commit-Queue: Zhi An Ng <zhin@chromium.org> > Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> > Reviewed-by: Bill Budge <bbudge@chromium.org> > Cr-Commit-Position: refs/heads/master@{#69315} Bug: chromium:1112124 Change-Id: Id450e5cea41f7a569e49be8386a7788ca8f00658 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2346937Reviewed-by:
Bill Budge <bbudge@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#69346}
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- 10 Aug, 2020 2 commits
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Bill Budge authored
This reverts commit 57242a05. Reason for revert: regression tests fails: https://ci.chromium.org/p/v8/builders/ci/V8%20Linux%20-%20debug/31477 Original change's description: > [wasm-simd][arm] Use vmov to move all ones to register > > vceq(dst, dst, dst) does not seem to always set the register to all > ones. The right way should be be to use vmov (immediate) anyway. This > was not supported in the assembler yet, so we need changes to the > assembler, diassembler, and simulator. > > There is an unfortunate fork in logic in the simulator, due to the way > the switches are set up, vmov (imm) logic is duplicated across two > different cases, because the switch looks at the top bit of the > immediate. Refactoring this will be a bigger change that is irrelevant > for this bug, so I'm putting that off for now. Instead we extract the > core of vmov (imm) into helpers and call it in the two cases. > > Bug: chromium:1112124 > Change-Id: I283dbcd86cb0572e5ee720835f897b51fae96701 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2337503 > Commit-Queue: Zhi An Ng <zhin@chromium.org> > Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> > Reviewed-by: Bill Budge <bbudge@chromium.org> > Cr-Commit-Position: refs/heads/master@{#69315} TBR=bbudge@chromium.org,jkummerow@chromium.org,v8-arm-ports@googlegroups.com,zhin@chromium.org Change-Id: I5d9d1dcb81771f71001d959ec5a03a43a11c4233 No-Presubmit: true No-Tree-Checks: true No-Try: true Bug: chromium:1112124 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2347211Reviewed-by:
Bill Budge <bbudge@chromium.org> Commit-Queue: Bill Budge <bbudge@chromium.org> Cr-Commit-Position: refs/heads/master@{#69316}
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Ng Zhi An authored
vceq(dst, dst, dst) does not seem to always set the register to all ones. The right way should be be to use vmov (immediate) anyway. This was not supported in the assembler yet, so we need changes to the assembler, diassembler, and simulator. There is an unfortunate fork in logic in the simulator, due to the way the switches are set up, vmov (imm) logic is duplicated across two different cases, because the switch looks at the top bit of the immediate. Refactoring this will be a bigger change that is irrelevant for this bug, so I'm putting that off for now. Instead we extract the core of vmov (imm) into helpers and call it in the two cases. Bug: chromium:1112124 Change-Id: I283dbcd86cb0572e5ee720835f897b51fae96701 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2337503 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Cr-Commit-Position: refs/heads/master@{#69315}
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- 25 Jun, 2020 1 commit
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Ng Zhi An authored
This implements I32x4DotI16x8S for arm. Bug: v8:10583 Change-Id: I4541f4f5bc7daba03c6ab2040589893c8ef571bc Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2230787Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#68550}
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- 24 Jun, 2020 1 commit
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Ng Zhi An authored
Prototype f32x4.nearest on ARM for both ARM v7 and ARM v8. ARM v8 has support for vrintn, and for ARM v7 we fallback to runtime. Since ARM v8 uses vrintn, which is the same instruction used for F32RoundTiesEven (scalar), wasm-compiler reuses the Float32RoundTiesEven check. Bug: v8:10553 Change-Id: I066b8c5f10fd86294afe1c530c516493deeb7b53 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2258037Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#68526}
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- 23 Jun, 2020 2 commits
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Ng Zhi An authored
Prototype f32x4.trunc on ARM for both ARM v7 and ARM v8. ARM v8 has support for vrintz, and for ARM v7 we fallback to runtime. Since ARM v8 uses vrintz, which is the same instruction used for F32 trunc (scalar), wasm-compiler reuses the Float32RoundTruncate check. Bug: v8:10553 Change-Id: I65ddc36ccff21f8f0ff21a6e768184c084ffcfea Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2256770 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#68498}
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Ng Zhi An authored
Bug: v8:10553 Change-Id: I57610afbf676f17d11675da1099ca45633d00402 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2254482 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#68497}
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- 22 Jun, 2020 1 commit
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Ng Zhi An authored
Prototype f32x4.floor on ARM for both ARM v7 and ARM v8. ARM v8 has support for vrintm, and for ARM v7 we fallback to runtime. Since ARM v8 uses vrintm, which is the same instruction used for F32 Floor (scalar), wasm-compiler reuses the Float32RoundDown check. Bug: v8:10553 Change-Id: I540e82a156131821f732cd427df2e5c68f4094d7 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2252541Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#68470}
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- 18 Jun, 2020 1 commit
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Ng Zhi An authored
Prototype f32x4.ceil on ARM for both ARM v7 and ARM v8. ARM v8 has support for vrintp, and for ARM v7 we fallback to runtime. Since ARM v8 uses vrintp, which is the same instruction used for F32 Ceil (scalar), wasm-compiler reuses the Float32Round check, rather than creating new F32x4Round optional operators. Implementation for vrintp (Advanced SIMD version that takes Q registers), assembler, disassembler support. Incomplete for now, but more will be added as we add other rounding modes. Bug: v8:10553 Change-Id: I4563608b9501f6f57c3a8325b17de89da7058a43 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2248779Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#68419}
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- 17 Jan, 2020 1 commit
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Ng Zhi An authored
Bug: v8:9813 Change-Id: I0436c6a90284559a110e99476c12ae39183c961e Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1994382 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#65846}
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- 16 Jan, 2020 2 commits
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Ng Zhi An authored
Add 64-bit data size support to SHL and SHR, add simulator logic to support new data size, and fix disasm. For the disasm fix, casting size / 16 to NeonSize no longer works when given a size of 64, it is 4, but should be 3. Change-Id: I5bd1ce254cd3ff4b86159837087f22b2ed06703e Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1994180Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#65825}
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Ng Zhi An authored
Bug: v8:10082 Change-Id: Ieabb0ebeec14091844b3d30b9b1684a249db7bdc Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1980949Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#65824}
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- 07 Jan, 2020 1 commit
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Ng Zhi An authored
Bug: v8:10039 Change-Id: If7c9668821a1cdfd5968f1533c3412247567bf3e Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1955550Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#65615}
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- 19 Nov, 2019 2 commits
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Ng Zhi An authored
These instructions should always treat inputs as signed, and saturate to unsigned min/max values. E.g. given -1, it should saturate to 0. The spec text, https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#integer-to-integer-narrowing, has been updated to describe this. The changes here include codegen changes to ia32, x64, arm, and arm64, changes to arm simulator, assembler, and disassembler to handle the case of treating input as signed and narrowing to unsigned. The vqmovn instruction can handle this case, our assembler wasn't allowing callers to specify this. The interpreter and scalar lowering are also fixed with this change. Bug: v8:9729 Change-Id: I6f72baa825f59037f7754485df6a2964af59fe31 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1879423Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#65051}
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Ng Zhi An authored
Bug: v8:9813 Change-Id: I75ca39612f0420548a56cc32edaa13a36a9713e9 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1900661Reviewed-by:
Bill Budge <bbudge@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#65041}
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- 18 Sep, 2019 1 commit
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Ng Zhi An authored
Change-Id: Ib07ad54ef20877597dcf50a995a8f8a8e8dcb1c3 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1809816Reviewed-by:
Martyn Capewell <martyn.capewell@arm.com> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#63877}
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