[arm] Add missing disasm and test for vld1r

Bug: v8:11038
Change-Id: Ifb50d8667b03afa045a957ffc8f3df799252e561
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2500939Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#70907}

src/diagnostics/arm/disasm-arm.cc

@@ -2434,16 +2434,18 @@ void Decoder::DecodeAdvancedSIMDElementOrStructureLoadStore(
   int op0 = instr->Bit(23);
   int op1 = instr->Bits(11, 10);
   int l = instr->Bit(21);
+  int n = instr->Bits(9, 8);
+  int Vd = instr->VFPDRegValue(kDoublePrecision);
+  int Rn = instr->VnValue();
+  int Rm = instr->VmValue();
+
   if (op0 == 0) {
     // Advanced SIMD load/store multiple structures.
     int itype = instr->Bits(11, 8);
     if (itype == 0b0010) {
       // vld1/vst1
-      int Vd = (instr->Bit(22) << 4) | instr->VdValue();
-      int Rn = instr->VnValue();
       int size = instr->Bits(7, 6);
       int align = instr->Bits(5, 4);
-      int Rm = instr->VmValue();
       const char* op = l ? "vld1.%d " : "vst1.%d ";
       out_buffer_pos_ +=
           SNPrintF(out_buffer_ + out_buffer_pos_, op, (1 << size) << 3);
@@ -2453,15 +2455,27 @@ void Decoder::DecodeAdvancedSIMDElementOrStructureLoadStore(
     } else {
       Unknown(instr);
     }
+  } else if (op1 == 0b11) {
+    // Advanced SIMD load single structure to all lanes.
+    if (l && n == 0b00) {
+      // vld1r(replicate) single element to all lanes.
+      int size = instr->Bits(7, 6);
+      DCHECK_NE(0b11, size);
+      int type = instr->Bit(5) ? nlt_2 : nlt_1;
+      out_buffer_pos_ +=
+          SNPrintF(out_buffer_ + out_buffer_pos_, "vld1.%d ", (1 << size) << 3);
+      FormatNeonList(Vd, type);
+      DCHECK_EQ(0, instr->Bit(4));  // Alignment not supported.
+      Print(", ");
+      FormatNeonMemory(Rn, 0, Rm);
+    } else {
+      Unknown(instr);
+    }
   } else if (op1 != 0b11) {
     // Advanced SIMD load/store single structure to one lane.
     int size = op1;  // size and op1 occupy the same bits in decoding.
-    int n = instr->Bits(9, 8);
     if (l && n == 0b00) {
       // VLD1 (single element to one lane) - A1, A2, A3
-      int Vd = instr->VFPDRegValue(kDoublePrecision);
-      int Rn = instr->VnValue();
-      int Rm = instr->VmValue();
       int index_align = instr->Bits(7, 4);
       int index = index_align >> (size + 1);
       // Omit alignment.

test/cctest/test-disasm-arm.cc

@@ -1000,6 +1000,10 @@ TEST(Neon) {
               "f4a1480f       vld1.32 {d4[0]}, [r1]");
       COMPARE(vld1s(Neon16, NeonListOperand(d4, 1), 3, NeonMemOperand(r1)),
               "f4a144cf       vld1.16 {d4[3]}, [r1]");
+      COMPARE(vld1r(Neon8, NeonListOperand(d4, 1), NeonMemOperand(r1)),
+              "f4a14c0f       vld1.8 {d4}, [r1]");
+      COMPARE(vld1r(Neon16, NeonListOperand(d4, 2), NeonMemOperand(r1)),
+              "f4a14c6f       vld1.16 {d4, d5}, [r1]");
       COMPARE(vst1(Neon16, NeonListOperand(d17, 4), NeonMemOperand(r9)),
               "f449124f       vst1.16 {d17, d18, d19, d20}, [r9]");
       COMPARE(vmovl(NeonU8, q3, d1), "f3886a11       vmovl.u8 q3, d1");