Commit 72b8a49f authored by Ng Zhi An's avatar Ng Zhi An Committed by Commit Bot

Add disasm for vshl (register) on arm

Change-Id: Ib07ad54ef20877597dcf50a995a8f8a8e8dcb1c3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1809816Reviewed-by: 's avatarMartyn Capewell <martyn.capewell@arm.com>
Reviewed-by: 's avatarDeepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#63877}
parent 42c98392
......@@ -1890,6 +1890,17 @@ void Decoder::DecodeSpecialCondition(Instruction* instr) {
op, size, Vd, Vn, Vm);
break;
}
case 0x4: {
if (instr->Bit(4) == 0) {
// vshl.s<size> Qd, Qm, Qn.
out_buffer_pos_ +=
SNPrintF(out_buffer_ + out_buffer_pos_,
"vshl.s%d q%d, q%d, q%d", size, Vd, Vm, Vn);
} else {
Unknown(instr);
}
break;
}
case 0x6: {
// vmin/vmax.s<size> Qd, Qm, Qn.
const char* op = instr->Bit(4) == 1 ? "vmin" : "vmax";
......@@ -2083,6 +2094,17 @@ void Decoder::DecodeSpecialCondition(Instruction* instr) {
op, size, Vd, Vn, Vm);
break;
}
case 0x4: {
if (instr->Bit(4) == 0) {
// vshl.u<size> Qd, Qm, Qn.
out_buffer_pos_ +=
SNPrintF(out_buffer_ + out_buffer_pos_,
"vshl.u%d q%d, q%d, q%d", size, Vd, Vm, Vn);
} else {
Unknown(instr);
}
break;
}
case 0x6: {
// vmin/vmax.u<size> Qd, Qm, Qn.
const char* op = instr->Bit(4) == 1 ? "vmin" : "vmax";
......
......@@ -1166,6 +1166,12 @@ TEST(Neon) {
"f2dae550 vshl.i16 q15, q0, #10");
COMPARE(vshl(NeonS32, q15, q0, 17),
"f2f1e550 vshl.i32 q15, q0, #17");
COMPARE(vshl(NeonS8, q15, q0, q1),
"f242e440 vshl.s8 q15, q0, q1");
COMPARE(vshl(NeonU16, q15, q2, q3),
"f356e444 vshl.u16 q15, q2, q3");
COMPARE(vshl(NeonS32, q15, q4, q5),
"f26ae448 vshl.s32 q15, q4, q5");
COMPARE(vshr(NeonS8, q15, q0, 6),
"f2cae050 vshr.s8 q15, q0, #6");
COMPARE(vshr(NeonU16, q15, q0, 10),
......
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