assembler-mips.cc 93.7 KB
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// Copyright (c) 1994-2006 Sun Microsystems Inc.
// All Rights Reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistribution in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of Sun Microsystems or the names of contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

// The original source code covered by the above license above has been
// modified significantly by Google Inc.
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// Copyright 2012 the V8 project authors. All rights reserved.
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#include "src/mips/assembler-mips.h"

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#if V8_TARGET_ARCH_MIPS
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#include "src/base/bits.h"
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#include "src/base/cpu.h"
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#include "src/mips/assembler-mips-inl.h"
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namespace v8 {
namespace internal {

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// Get the CPU features enabled by the build. For cross compilation the
// preprocessor symbols CAN_USE_FPU_INSTRUCTIONS
// can be defined to enable FPU instructions when building the
// snapshot.
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static unsigned CpuFeaturesImpliedByCompiler() {
  unsigned answer = 0;
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#ifdef CAN_USE_FPU_INSTRUCTIONS
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  answer |= 1u << FPU;
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#endif  // def CAN_USE_FPU_INSTRUCTIONS

  // If the compiler is allowed to use FPU then we can use FPU too in our code
  // generation even when generating snapshots.  This won't work for cross
  // compilation.
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#if defined(__mips__) && defined(__mips_hard_float) && __mips_hard_float != 0
  answer |= 1u << FPU;
#endif
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  return answer;
}


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void CpuFeatures::ProbeImpl(bool cross_compile) {
  supported_ |= CpuFeaturesImpliedByCompiler();
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  // Only use statically determined features for cross compile (snapshot).
  if (cross_compile) return;
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  // If the compiler is allowed to use fpu then we can use fpu too in our
  // code generation.
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#ifndef __mips__
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  // For the simulator build, use FPU.
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  supported_ |= 1u << FPU;
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#if defined(_MIPS_ARCH_MIPS32R6)
  // FP64 mode is implied on r6.
  supported_ |= 1u << FP64FPU;
#endif
#if defined(FPU_MODE_FP64)
  supported_ |= 1u << FP64FPU;
#endif
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#else
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  // Probe for additional features at runtime.
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  base::CPU cpu;
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  if (cpu.has_fpu()) supported_ |= 1u << FPU;
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#if defined(FPU_MODE_FPXX)
  if (cpu.is_fp64_mode()) supported_ |= 1u << FP64FPU;
#elif defined(FPU_MODE_FP64)
  supported_ |= 1u << FP64FPU;
#endif
#if defined(_MIPS_ARCH_MIPS32RX)
  if (cpu.architecture() == 6) {
    supported_ |= 1u << MIPSr6;
  } else if (cpu.architecture() == 2) {
    supported_ |= 1u << MIPSr1;
    supported_ |= 1u << MIPSr2;
  } else {
    supported_ |= 1u << MIPSr1;
  }
#endif
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#endif
}
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void CpuFeatures::PrintTarget() { }
void CpuFeatures::PrintFeatures() { }


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int ToNumber(Register reg) {
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  DCHECK(reg.is_valid());
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  const int kNumbers[] = {
    0,    // zero_reg
    1,    // at
    2,    // v0
    3,    // v1
    4,    // a0
    5,    // a1
    6,    // a2
    7,    // a3
    8,    // t0
    9,    // t1
    10,   // t2
    11,   // t3
    12,   // t4
    13,   // t5
    14,   // t6
    15,   // t7
    16,   // s0
    17,   // s1
    18,   // s2
    19,   // s3
    20,   // s4
    21,   // s5
    22,   // s6
    23,   // s7
    24,   // t8
    25,   // t9
    26,   // k0
    27,   // k1
    28,   // gp
    29,   // sp
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    30,   // fp
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    31,   // ra
  };
  return kNumbers[reg.code()];
}

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Register ToRegister(int num) {
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  DCHECK(num >= 0 && num < kNumRegisters);
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  const Register kRegisters[] = {
    zero_reg,
    at,
    v0, v1,
    a0, a1, a2, a3,
    t0, t1, t2, t3, t4, t5, t6, t7,
    s0, s1, s2, s3, s4, s5, s6, s7,
    t8, t9,
    k0, k1,
    gp,
    sp,
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    fp,
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    ra
  };
  return kRegisters[num];
}


// -----------------------------------------------------------------------------
// Implementation of RelocInfo.

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const int RelocInfo::kApplyMask = RelocInfo::kCodeTargetMask |
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                                  1 << RelocInfo::INTERNAL_REFERENCE |
                                  1 << RelocInfo::INTERNAL_REFERENCE_ENCODED;
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bool RelocInfo::IsCodedSpecially() {
  // The deserializer needs to know whether a pointer is specially coded.  Being
  // specially coded on MIPS means that it is a lui/ori instruction, and that is
  // always the case inside code objects.
  return true;
}


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bool RelocInfo::IsInConstantPool() {
  return false;
}

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Address RelocInfo::wasm_memory_reference() {
  DCHECK(IsWasmMemoryReference(rmode_));
  return Assembler::target_address_at(pc_, host_);
}

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Address RelocInfo::wasm_global_reference() {
  DCHECK(IsWasmGlobalReference(rmode_));
  return Assembler::target_address_at(pc_, host_);
}

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uint32_t RelocInfo::wasm_memory_size_reference() {
  DCHECK(IsWasmMemorySizeReference(rmode_));
  return reinterpret_cast<uint32_t>(Assembler::target_address_at(pc_, host_));
}

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void RelocInfo::unchecked_update_wasm_memory_reference(
    Address address, ICacheFlushMode flush_mode) {
  Assembler::set_target_address_at(isolate_, pc_, host_, address, flush_mode);
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}
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void RelocInfo::unchecked_update_wasm_memory_size(uint32_t size,
                                                  ICacheFlushMode flush_mode) {
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  Assembler::set_target_address_at(isolate_, pc_, host_,
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                                   reinterpret_cast<Address>(size), flush_mode);
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}

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// -----------------------------------------------------------------------------
// Implementation of Operand and MemOperand.
// See assembler-mips-inl.h for inlined constructors.

Operand::Operand(Handle<Object> handle) {
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  AllowDeferredHandleDereference using_raw_address;
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  rm_ = no_reg;
  // Verify all Objects referred by code are NOT in new space.
  Object* obj = *handle;
  if (obj->IsHeapObject()) {
    imm32_ = reinterpret_cast<intptr_t>(handle.location());
    rmode_ = RelocInfo::EMBEDDED_OBJECT;
  } else {
    // No relocation needed.
    imm32_ = reinterpret_cast<intptr_t>(obj);
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    rmode_ = RelocInfo::NONE32;
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  }
}

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MemOperand::MemOperand(Register rm, int32_t offset) : Operand(rm) {
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  offset_ = offset;
}


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MemOperand::MemOperand(Register rm, int32_t unit, int32_t multiplier,
                       OffsetAddend offset_addend) : Operand(rm) {
  offset_ = unit * multiplier + offset_addend;
}


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// -----------------------------------------------------------------------------
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// Specific instructions, constants, and masks.

static const int kNegOffset = 0x00008000;
// addiu(sp, sp, 4) aka Pop() operation or part of Pop(r)
// operations as post-increment of sp.
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const Instr kPopInstruction = ADDIU | (Register::kCode_sp << kRsShift) |
                              (Register::kCode_sp << kRtShift) |
                              (kPointerSize & kImm16Mask);  // NOLINT
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// addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp.
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const Instr kPushInstruction = ADDIU | (Register::kCode_sp << kRsShift) |
                               (Register::kCode_sp << kRtShift) |
                               (-kPointerSize & kImm16Mask);  // NOLINT
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// sw(r, MemOperand(sp, 0))
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const Instr kPushRegPattern =
    SW | (Register::kCode_sp << kRsShift) | (0 & kImm16Mask);  // NOLINT
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//  lw(r, MemOperand(sp, 0))
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const Instr kPopRegPattern =
    LW | (Register::kCode_sp << kRsShift) | (0 & kImm16Mask);  // NOLINT
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const Instr kLwRegFpOffsetPattern =
    LW | (Register::kCode_fp << kRsShift) | (0 & kImm16Mask);  // NOLINT
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const Instr kSwRegFpOffsetPattern =
    SW | (Register::kCode_fp << kRsShift) | (0 & kImm16Mask);  // NOLINT
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const Instr kLwRegFpNegOffsetPattern = LW | (Register::kCode_fp << kRsShift) |
                                       (kNegOffset & kImm16Mask);  // NOLINT
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const Instr kSwRegFpNegOffsetPattern = SW | (Register::kCode_fp << kRsShift) |
                                       (kNegOffset & kImm16Mask);  // NOLINT
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// A mask for the Rt register for push, pop, lw, sw instructions.
const Instr kRtMask = kRtFieldMask;
const Instr kLwSwInstrTypeMask = 0xffe00000;
const Instr kLwSwInstrArgumentMask  = ~kLwSwInstrTypeMask;
const Instr kLwSwOffsetMask = kImm16Mask;

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Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
    : AssemblerBase(isolate, buffer, buffer_size),
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      recorded_ast_id_(TypeFeedbackId::None()) {
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  reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
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  last_trampoline_pool_end_ = 0;
  no_trampoline_pool_before_ = 0;
  trampoline_pool_blocked_nesting_ = 0;
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  // We leave space (16 * kTrampolineSlotsSize)
  // for BlockTrampolinePoolScope buffer.
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  next_buffer_check_ = FLAG_force_long_branches
      ? kMaxInt : kMaxBranchOffset - kTrampolineSlotsSize * 16;
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  internal_trampoline_exception_ = false;
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  last_bound_pos_ = 0;
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  trampoline_emitted_ = FLAG_force_long_branches;
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  unbound_labels_count_ = 0;
  block_buffer_growth_ = false;

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  ClearRecordedAstId();
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}


void Assembler::GetCode(CodeDesc* desc) {
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  EmitForbiddenSlotInstruction();
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  DCHECK(pc_ <= reloc_info_writer.pos());  // No overlap.
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  // Set up code descriptor.
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  desc->buffer = buffer_;
  desc->buffer_size = buffer_size_;
  desc->instr_size = pc_offset();
  desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
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  desc->origin = this;
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  desc->constant_pool_size = 0;
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  desc->unwinding_info_size = 0;
  desc->unwinding_info = nullptr;
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}


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void Assembler::Align(int m) {
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  DCHECK(m >= 4 && base::bits::IsPowerOfTwo32(m));
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  EmitForbiddenSlotInstruction();
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  while ((pc_offset() & (m - 1)) != 0) {
    nop();
  }
}


void Assembler::CodeTargetAlign() {
  // No advantage to aligning branch/call targets to more than
  // single instruction, that I am aware of.
  Align(4);
}


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Register Assembler::GetRtReg(Instr instr) {
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  Register rt;
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  rt.reg_code = (instr & kRtFieldMask) >> kRtShift;
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  return rt;
}


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Register Assembler::GetRsReg(Instr instr) {
  Register rs;
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  rs.reg_code = (instr & kRsFieldMask) >> kRsShift;
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  return rs;
}


Register Assembler::GetRdReg(Instr instr) {
  Register rd;
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  rd.reg_code = (instr & kRdFieldMask) >> kRdShift;
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  return rd;
}


uint32_t Assembler::GetRt(Instr instr) {
  return (instr & kRtFieldMask) >> kRtShift;
}


uint32_t Assembler::GetRtField(Instr instr) {
  return instr & kRtFieldMask;
}


uint32_t Assembler::GetRs(Instr instr) {
  return (instr & kRsFieldMask) >> kRsShift;
}


uint32_t Assembler::GetRsField(Instr instr) {
  return instr & kRsFieldMask;
}


uint32_t Assembler::GetRd(Instr instr) {
  return  (instr & kRdFieldMask) >> kRdShift;
}


uint32_t Assembler::GetRdField(Instr instr) {
  return  instr & kRdFieldMask;
}


uint32_t Assembler::GetSa(Instr instr) {
  return (instr & kSaFieldMask) >> kSaShift;
}


uint32_t Assembler::GetSaField(Instr instr) {
  return instr & kSaFieldMask;
}


uint32_t Assembler::GetOpcodeField(Instr instr) {
  return instr & kOpcodeMask;
}


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uint32_t Assembler::GetFunction(Instr instr) {
  return (instr & kFunctionFieldMask) >> kFunctionShift;
}


uint32_t Assembler::GetFunctionField(Instr instr) {
  return instr & kFunctionFieldMask;
}


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uint32_t Assembler::GetImmediate16(Instr instr) {
  return instr & kImm16Mask;
}


uint32_t Assembler::GetLabelConst(Instr instr) {
  return instr & ~kImm16Mask;
}


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bool Assembler::IsPop(Instr instr) {
  return (instr & ~kRtMask) == kPopRegPattern;
}


bool Assembler::IsPush(Instr instr) {
  return (instr & ~kRtMask) == kPushRegPattern;
}


bool Assembler::IsSwRegFpOffset(Instr instr) {
  return ((instr & kLwSwInstrTypeMask) == kSwRegFpOffsetPattern);
}


bool Assembler::IsLwRegFpOffset(Instr instr) {
  return ((instr & kLwSwInstrTypeMask) == kLwRegFpOffsetPattern);
}


bool Assembler::IsSwRegFpNegOffset(Instr instr) {
  return ((instr & (kLwSwInstrTypeMask | kNegOffset)) ==
          kSwRegFpNegOffsetPattern);
}


bool Assembler::IsLwRegFpNegOffset(Instr instr) {
  return ((instr & (kLwSwInstrTypeMask | kNegOffset)) ==
          kLwRegFpNegOffsetPattern);
}


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// Labels refer to positions in the (to be) generated code.
// There are bound, linked, and unused labels.
//
// Bound labels refer to known positions in the already
// generated code. pos() is the position the label refers to.
//
// Linked labels refer to unknown positions in the code
// to be generated; pos() is the position of the last
// instruction using the label.

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// The link chain is terminated by a value in the instruction of -1,
// which is an otherwise illegal value (branch -1 is inf loop).
// The instruction 16-bit offset field addresses 32-bit words, but in
// code is conv to an 18-bit value addressing bytes, hence the -4 value.
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const int kEndOfChain = -4;
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// Determines the end of the Jump chain (a subset of the label link chain).
const int kEndOfJumpChain = 0;
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bool Assembler::IsBranch(Instr instr) {
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  uint32_t opcode   = GetOpcodeField(instr);
  uint32_t rt_field = GetRtField(instr);
  uint32_t rs_field = GetRsField(instr);
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  // Checks if the instruction is a branch.
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  bool isBranch =
      opcode == BEQ || opcode == BNE || opcode == BLEZ || opcode == BGTZ ||
      opcode == BEQL || opcode == BNEL || opcode == BLEZL || opcode == BGTZL ||
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      (opcode == REGIMM && (rt_field == BLTZ || rt_field == BGEZ ||
                            rt_field == BLTZAL || rt_field == BGEZAL)) ||
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      (opcode == COP1 && rs_field == BC1) ||  // Coprocessor branch.
      (opcode == COP1 && rs_field == BC1EQZ) ||
      (opcode == COP1 && rs_field == BC1NEZ);
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  if (!isBranch && IsMipsArchVariant(kMips32r6)) {
    // All the 3 variants of POP10 (BOVC, BEQC, BEQZALC) and
    // POP30 (BNVC, BNEC, BNEZALC) are branch ops.
    isBranch |= opcode == POP10 || opcode == POP30 || opcode == BC ||
                opcode == BALC ||
                (opcode == POP66 && rs_field != 0) ||  // BEQZC
                (opcode == POP76 && rs_field != 0);    // BNEZC
  }
  return isBranch;
}


bool Assembler::IsBc(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  // Checks if the instruction is a BC or BALC.
  return opcode == BC || opcode == BALC;
}


bool Assembler::IsBzc(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  // Checks if the instruction is BEQZC or BNEZC.
  return (opcode == POP66 && GetRsField(instr) != 0) ||
         (opcode == POP76 && GetRsField(instr) != 0);
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}

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bool Assembler::IsEmittedConstant(Instr instr) {
  uint32_t label_constant = GetLabelConst(instr);
  return label_constant == 0;  // Emitted label const in reg-exp engine.
}
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bool Assembler::IsBeq(Instr instr) {
  return GetOpcodeField(instr) == BEQ;
}


bool Assembler::IsBne(Instr instr) {
  return GetOpcodeField(instr) == BNE;
}


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bool Assembler::IsBeqzc(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  return opcode == POP66 && GetRsField(instr) != 0;
}


bool Assembler::IsBnezc(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  return opcode == POP76 && GetRsField(instr) != 0;
}


bool Assembler::IsBeqc(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  uint32_t rs = GetRsField(instr);
  uint32_t rt = GetRtField(instr);
  return opcode == POP10 && rs != 0 && rs < rt;  // && rt != 0
}


bool Assembler::IsBnec(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  uint32_t rs = GetRsField(instr);
  uint32_t rt = GetRtField(instr);
  return opcode == POP30 && rs != 0 && rs < rt;  // && rt != 0
}

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bool Assembler::IsJicOrJialc(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  uint32_t rs = GetRsField(instr);
  return (opcode == POP66 || opcode == POP76) && rs == 0;
}
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bool Assembler::IsJump(Instr instr) {
  uint32_t opcode   = GetOpcodeField(instr);
  uint32_t rt_field = GetRtField(instr);
  uint32_t rd_field = GetRdField(instr);
  uint32_t function_field = GetFunctionField(instr);
  // Checks if the instruction is a jump.
  return opcode == J || opcode == JAL ||
      (opcode == SPECIAL && rt_field == 0 &&
      ((function_field == JALR) || (rd_field == 0 && (function_field == JR))));
}

bool Assembler::IsJ(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  // Checks if the instruction is a jump.
  return opcode == J;
}


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bool Assembler::IsJal(Instr instr) {
  return GetOpcodeField(instr) == JAL;
}

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bool Assembler::IsJr(Instr instr) {
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  if (!IsMipsArchVariant(kMips32r6))  {
    return GetOpcodeField(instr) == SPECIAL && GetFunctionField(instr) == JR;
  } else {
    return GetOpcodeField(instr) == SPECIAL &&
        GetRdField(instr) == 0  && GetFunctionField(instr) == JALR;
  }
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}

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bool Assembler::IsJalr(Instr instr) {
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  return GetOpcodeField(instr) == SPECIAL &&
         GetRdField(instr) != 0  && GetFunctionField(instr) == JALR;
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}


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bool Assembler::IsLui(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  // Checks if the instruction is a load upper immediate.
  return opcode == LUI;
}


bool Assembler::IsOri(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  // Checks if the instruction is a load upper immediate.
  return opcode == ORI;
}


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bool Assembler::IsNop(Instr instr, unsigned int type) {
  // See Assembler::nop(type).
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  DCHECK(type < 32);
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  uint32_t opcode = GetOpcodeField(instr);
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  uint32_t function = GetFunctionField(instr);
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  uint32_t rt = GetRt(instr);
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  uint32_t rd = GetRd(instr);
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  uint32_t sa = GetSa(instr);
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  // Traditional mips nop == sll(zero_reg, zero_reg, 0)
  // When marking non-zero type, use sll(zero_reg, at, type)
  // to avoid use of mips ssnop and ehb special encodings
  // of the sll instruction.
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  Register nop_rt_reg = (type == 0) ? zero_reg : at;
  bool ret = (opcode == SPECIAL && function == SLL &&
              rd == static_cast<uint32_t>(ToNumber(zero_reg)) &&
              rt == static_cast<uint32_t>(ToNumber(nop_rt_reg)) &&
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              sa == type);

  return ret;
}


int32_t Assembler::GetBranchOffset(Instr instr) {
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  DCHECK(IsBranch(instr));
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  return (static_cast<int16_t>(instr & kImm16Mask)) << 2;
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}


bool Assembler::IsLw(Instr instr) {
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  return (static_cast<uint32_t>(instr & kOpcodeMask) == LW);
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}


int16_t Assembler::GetLwOffset(Instr instr) {
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  DCHECK(IsLw(instr));
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  return ((instr & kImm16Mask));
}


Instr Assembler::SetLwOffset(Instr instr, int16_t offset) {
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  DCHECK(IsLw(instr));
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  // We actually create a new lw instruction based on the original one.
  Instr temp_instr = LW | (instr & kRsFieldMask) | (instr & kRtFieldMask)
      | (offset & kImm16Mask);

  return temp_instr;
}


bool Assembler::IsSw(Instr instr) {
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  return (static_cast<uint32_t>(instr & kOpcodeMask) == SW);
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}


Instr Assembler::SetSwOffset(Instr instr, int16_t offset) {
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  DCHECK(IsSw(instr));
679 680 681 682 683 684 685 686 687 688
  return ((instr & ~kImm16Mask) | (offset & kImm16Mask));
}


bool Assembler::IsAddImmediate(Instr instr) {
  return ((instr & kOpcodeMask) == ADDIU);
}


Instr Assembler::SetAddImmediateOffset(Instr instr, int16_t offset) {
689
  DCHECK(IsAddImmediate(instr));
690
  return ((instr & ~kImm16Mask) | (offset & kImm16Mask));
691 692 693
}


694 695 696 697 698
bool Assembler::IsAndImmediate(Instr instr) {
  return GetOpcodeField(instr) == ANDI;
}


699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727
static Assembler::OffsetSize OffsetSizeInBits(Instr instr) {
  if (IsMipsArchVariant(kMips32r6)) {
    if (Assembler::IsBc(instr)) {
      return Assembler::OffsetSize::kOffset26;
    } else if (Assembler::IsBzc(instr)) {
      return Assembler::OffsetSize::kOffset21;
    }
  }
  return Assembler::OffsetSize::kOffset16;
}


static inline int32_t AddBranchOffset(int pos, Instr instr) {
  int bits = OffsetSizeInBits(instr);
  const int32_t mask = (1 << bits) - 1;
  bits = 32 - bits;

  // Do NOT change this to <<2. We rely on arithmetic shifts here, assuming
  // the compiler uses arithmetic shifts for signed integers.
  int32_t imm = ((instr & mask) << bits) >> (bits - 2);

  if (imm == kEndOfChain) {
    // EndOfChain sentinel is returned directly, not relative to pc or pos.
    return kEndOfChain;
  } else {
    return pos + Assembler::kBranchPCOffset + imm;
  }
}

728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768
uint32_t Assembler::CreateTargetAddress(Instr instr_lui, Instr instr_jic) {
  DCHECK(IsLui(instr_lui) && IsJicOrJialc(instr_jic));
  int16_t jic_offset = GetImmediate16(instr_jic);
  int16_t lui_offset = GetImmediate16(instr_lui);

  if (jic_offset < 0) {
    lui_offset += kImm16Mask;
  }
  uint32_t lui_offset_u = (static_cast<uint32_t>(lui_offset)) << kLuiShift;
  uint32_t jic_offset_u = static_cast<uint32_t>(jic_offset) & kImm16Mask;

  return lui_offset_u | jic_offset_u;
}

// Use just lui and jic instructions. Insert lower part of the target address in
// jic offset part. Since jic sign-extends offset and then add it with register,
// before that addition, difference between upper part of the target address and
// upper part of the sign-extended offset (0xffff or 0x0000), will be inserted
// in jic register with lui instruction.
void Assembler::UnpackTargetAddress(uint32_t address, int16_t& lui_offset,
                                    int16_t& jic_offset) {
  lui_offset = (address & kHiMask) >> kLuiShift;
  jic_offset = address & kLoMask;

  if (jic_offset < 0) {
    lui_offset -= kImm16Mask;
  }
}

void Assembler::UnpackTargetAddressUnsigned(uint32_t address,
                                            uint32_t& lui_offset,
                                            uint32_t& jic_offset) {
  int16_t lui_offset16 = (address & kHiMask) >> kLuiShift;
  int16_t jic_offset16 = address & kLoMask;

  if (jic_offset16 < 0) {
    lui_offset16 -= kImm16Mask;
  }
  lui_offset = static_cast<uint32_t>(lui_offset16) & kImm16Mask;
  jic_offset = static_cast<uint32_t>(jic_offset16) & kImm16Mask;
}
769

770
int Assembler::target_at(int pos, bool is_internal) {
771
  Instr instr = instr_at(pos);
772 773 774 775 776
  if (is_internal) {
    if (instr == 0) {
      return kEndOfChain;
    } else {
      int32_t instr_address = reinterpret_cast<int32_t>(buffer_ + pos);
777
      int delta = static_cast<int>(instr_address - instr);
778 779 780 781
      DCHECK(pos > delta);
      return pos - delta;
    }
  }
782 783
  if ((instr & ~kImm16Mask) == 0) {
    // Emitted label constant, not part of a branch.
784 785 786 787 788 789
    if (instr == 0) {
       return kEndOfChain;
     } else {
       int32_t imm18 =((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14;
       return (imm18 + pos);
     }
790
  }
791
  // Check we have a branch or jump instruction.
792
  DCHECK(IsBranch(instr) || IsLui(instr));
793
  if (IsBranch(instr)) {
794 795
    return AddBranchOffset(pos, instr);
  } else {
796 797 798 799 800 801 802 803 804 805
    Instr instr1 = instr_at(pos + 0 * Assembler::kInstrSize);
    Instr instr2 = instr_at(pos + 1 * Assembler::kInstrSize);
    DCHECK(IsOri(instr2) || IsJicOrJialc(instr2));
    int32_t imm;
    if (IsJicOrJialc(instr2)) {
      imm = CreateTargetAddress(instr1, instr2);
    } else {
      imm = (instr1 & static_cast<int32_t>(kImm16Mask)) << kLuiShift;
      imm |= (instr2 & static_cast<int32_t>(kImm16Mask));
    }
806 807 808 809 810 811 812

    if (imm == kEndOfJumpChain) {
      // EndOfChain sentinel is returned directly, not relative to pc or pos.
      return kEndOfChain;
    } else {
      uint32_t instr_address = reinterpret_cast<int32_t>(buffer_ + pos);
      int32_t delta = instr_address - imm;
813
      DCHECK(pos > delta);
814 815
      return pos - delta;
    }
816
  }
817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832
  return 0;
}


static inline Instr SetBranchOffset(int32_t pos, int32_t target_pos,
                                    Instr instr) {
  int32_t bits = OffsetSizeInBits(instr);
  int32_t imm = target_pos - (pos + Assembler::kBranchPCOffset);
  DCHECK((imm & 3) == 0);
  imm >>= 2;

  const int32_t mask = (1 << bits) - 1;
  instr &= ~mask;
  DCHECK(is_intn(imm, bits));

  return instr | (imm & mask);
833 834 835
}


836 837
void Assembler::target_at_put(int32_t pos, int32_t target_pos,
                              bool is_internal) {
838
  Instr instr = instr_at(pos);
839 840 841 842 843 844

  if (is_internal) {
    uint32_t imm = reinterpret_cast<uint32_t>(buffer_) + target_pos;
    instr_at_put(pos, imm);
    return;
  }
845
  if ((instr & ~kImm16Mask) == 0) {
846
    DCHECK(target_pos == kEndOfChain || target_pos >= 0);
847 848 849 850 851 852
    // Emitted label constant, not part of a branch.
    // Make label relative to Code* of generated Code object.
    instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag));
    return;
  }

853
  DCHECK(IsBranch(instr) || IsLui(instr));
854
  if (IsBranch(instr)) {
855 856 857
    instr = SetBranchOffset(pos, target_pos, instr);
    instr_at_put(pos, instr);
  } else {
858 859 860
    Instr instr1 = instr_at(pos + 0 * Assembler::kInstrSize);
    Instr instr2 = instr_at(pos + 1 * Assembler::kInstrSize);
    DCHECK(IsOri(instr2) || IsJicOrJialc(instr2));
861
    uint32_t imm = reinterpret_cast<uint32_t>(buffer_) + target_pos;
862
    DCHECK((imm & 3) == 0);
863 864 865 866 867 868 869 870 871 872 873 874 875 876 877
    DCHECK(IsLui(instr1) && (IsJicOrJialc(instr2) || IsOri(instr2)));
    instr1 &= ~kImm16Mask;
    instr2 &= ~kImm16Mask;

    if (IsJicOrJialc(instr2)) {
      uint32_t lui_offset_u, jic_offset_u;
      UnpackTargetAddressUnsigned(imm, lui_offset_u, jic_offset_u);
      instr_at_put(pos + 0 * Assembler::kInstrSize, instr1 | lui_offset_u);
      instr_at_put(pos + 1 * Assembler::kInstrSize, instr2 | jic_offset_u);
    } else {
      instr_at_put(pos + 0 * Assembler::kInstrSize,
                   instr1 | ((imm & kHiMask) >> kLuiShift));
      instr_at_put(pos + 1 * Assembler::kInstrSize,
                   instr2 | (imm & kImm16Mask));
    }
878
  }
879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897
}


void Assembler::print(Label* L) {
  if (L->is_unused()) {
    PrintF("unused label\n");
  } else if (L->is_bound()) {
    PrintF("bound label to %d\n", L->pos());
  } else if (L->is_linked()) {
    Label l = *L;
    PrintF("unbound label");
    while (l.is_linked()) {
      PrintF("@ %d ", l.pos());
      Instr instr = instr_at(l.pos());
      if ((instr & ~kImm16Mask) == 0) {
        PrintF("value\n");
      } else {
        PrintF("%d\n", instr);
      }
898 899
      next(&l, internal_reference_positions_.find(l.pos()) !=
                   internal_reference_positions_.end());
900 901 902 903 904 905 906 907
    }
  } else {
    PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
  }
}


void Assembler::bind_to(Label* L, int pos) {
908
  DCHECK(0 <= pos && pos <= pc_offset());  // Must have valid binding position.
909
  int32_t trampoline_pos = kInvalidSlotPos;
910
  bool is_internal = false;
911 912 913 914 915
  if (L->is_linked() && !trampoline_emitted_) {
    unbound_labels_count_--;
    next_buffer_check_ += kTrampolineSlotsSize;
  }

916 917
  while (L->is_linked()) {
    int32_t fixup_pos = L->pos();
918
    int32_t dist = pos - fixup_pos;
919 920 921 922
    is_internal = internal_reference_positions_.find(fixup_pos) !=
                  internal_reference_positions_.end();
    next(L, is_internal);  // Call next before overwriting link with target at
                           // fixup_pos.
923
    Instr instr = instr_at(fixup_pos);
924 925
    if (is_internal) {
      target_at_put(fixup_pos, pos, is_internal);
926 927
    } else {
      if (IsBranch(instr)) {
928 929
        int branch_offset = BranchOffset(instr);
        if (dist > branch_offset) {
930 931 932 933
          if (trampoline_pos == kInvalidSlotPos) {
            trampoline_pos = get_trampoline_entry(fixup_pos);
            CHECK(trampoline_pos != kInvalidSlotPos);
          }
934
          CHECK((trampoline_pos - fixup_pos) <= branch_offset);
935 936 937
          target_at_put(fixup_pos, trampoline_pos, false);
          fixup_pos = trampoline_pos;
          dist = pos - fixup_pos;
938
        }
939 940 941
        target_at_put(fixup_pos, pos, false);
      } else {
        target_at_put(fixup_pos, pos, false);
942 943
      }
    }
944 945 946 947 948 949 950 951 952 953 954
  }
  L->bind_to(pos);

  // Keep track of the last bound label so we don't eliminate any instructions
  // before a bound label.
  if (pos > last_bound_pos_)
    last_bound_pos_ = pos;
}


void Assembler::bind(Label* L) {
955
  DCHECK(!L->is_bound());  // Label can only be bound once.
956 957 958 959
  bind_to(L, pc_offset());
}


960
void Assembler::next(Label* L, bool is_internal) {
961
  DCHECK(L->is_linked());
962
  int link = target_at(L->pos(), is_internal);
963
  if (link == kEndOfChain) {
964
    L->Unuse();
965
  } else {
966
    DCHECK(link >= 0);
967
    L->link_to(link);
968 969 970
  }
}

971

972
bool Assembler::is_near(Label* L) {
973
  DCHECK(L->is_bound());
974
  return pc_offset() - L->pos() < kMaxBranchOffset - 4 * kInstrSize;
975 976 977 978 979
}


bool Assembler::is_near(Label* L, OffsetSize bits) {
  if (L == nullptr || !L->is_bound()) return true;
980
  return pc_offset() - L->pos() < (1 << (bits + 2 - 1)) - 1 - 5 * kInstrSize;
981 982 983 984 985
}


bool Assembler::is_near_branch(Label* L) {
  DCHECK(L->is_bound());
986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013
  return IsMipsArchVariant(kMips32r6) ? is_near_r6(L) : is_near_pre_r6(L);
}


int Assembler::BranchOffset(Instr instr) {
  // At pre-R6 and for other R6 branches the offset is 16 bits.
  int bits = OffsetSize::kOffset16;

  if (IsMipsArchVariant(kMips32r6)) {
    uint32_t opcode = GetOpcodeField(instr);
    switch (opcode) {
      // Checks BC or BALC.
      case BC:
      case BALC:
        bits = OffsetSize::kOffset26;
        break;

      // Checks BEQZC or BNEZC.
      case POP66:
      case POP76:
        if (GetRsField(instr) != 0) bits = OffsetSize::kOffset21;
        break;
      default:
        break;
    }
  }

  return (1 << (bits + 2 - 1)) - 1;
1014
}
1015

1016

1017 1018 1019 1020
// We have to use a temporary register for things that can be relocated even
// if they can be encoded in the MIPS's 16 bits of immediate-offset instruction
// space.  There is no guarantee that the relocated location can be similarly
// encoded.
1021
bool Assembler::MustUseReg(RelocInfo::Mode rmode) {
1022
  return !RelocInfo::IsNone(rmode);
1023 1024 1025 1026 1027 1028 1029 1030
}

void Assembler::GenInstrRegister(Opcode opcode,
                                 Register rs,
                                 Register rt,
                                 Register rd,
                                 uint16_t sa,
                                 SecondaryField func) {
1031
  DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa));
1032 1033 1034 1035 1036 1037
  Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
      | (rd.code() << kRdShift) | (sa << kSaShift) | func;
  emit(instr);
}


1038 1039 1040 1041 1042 1043
void Assembler::GenInstrRegister(Opcode opcode,
                                 Register rs,
                                 Register rt,
                                 uint16_t msb,
                                 uint16_t lsb,
                                 SecondaryField func) {
1044
  DCHECK(rs.is_valid() && rt.is_valid() && is_uint5(msb) && is_uint5(lsb));
1045 1046 1047 1048 1049 1050
  Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
      | (msb << kRdShift) | (lsb << kSaShift) | func;
  emit(instr);
}


1051 1052 1053 1054 1055 1056
void Assembler::GenInstrRegister(Opcode opcode,
                                 SecondaryField fmt,
                                 FPURegister ft,
                                 FPURegister fs,
                                 FPURegister fd,
                                 SecondaryField func) {
1057
  DCHECK(fd.is_valid() && fs.is_valid() && ft.is_valid());
1058 1059
  Instr instr = opcode | fmt | (ft.code() << kFtShift) | (fs.code() << kFsShift)
      | (fd.code() << kFdShift) | func;
1060 1061 1062 1063
  emit(instr);
}


1064 1065 1066 1067 1068 1069
void Assembler::GenInstrRegister(Opcode opcode,
                                 FPURegister fr,
                                 FPURegister ft,
                                 FPURegister fs,
                                 FPURegister fd,
                                 SecondaryField func) {
1070
  DCHECK(fd.is_valid() && fr.is_valid() && fs.is_valid() && ft.is_valid());
1071 1072 1073 1074 1075 1076
  Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift)
      | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;
  emit(instr);
}


1077 1078 1079 1080 1081 1082
void Assembler::GenInstrRegister(Opcode opcode,
                                 SecondaryField fmt,
                                 Register rt,
                                 FPURegister fs,
                                 FPURegister fd,
                                 SecondaryField func) {
1083
  DCHECK(fd.is_valid() && fs.is_valid() && rt.is_valid());
1084
  Instr instr = opcode | fmt | (rt.code() << kRtShift)
1085 1086 1087 1088 1089 1090 1091 1092 1093 1094
      | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;
  emit(instr);
}


void Assembler::GenInstrRegister(Opcode opcode,
                                 SecondaryField fmt,
                                 Register rt,
                                 FPUControlRegister fs,
                                 SecondaryField func) {
1095
  DCHECK(fs.is_valid() && rt.is_valid());
1096 1097
  Instr instr =
      opcode | fmt | (rt.code() << kRtShift) | (fs.code() << kFsShift) | func;
1098 1099 1100 1101 1102 1103
  emit(instr);
}


// Instructions with immediate value.
// Registers are in the order of the instruction encoding, from left to right.
1104 1105 1106
void Assembler::GenInstrImmediate(Opcode opcode, Register rs, Register rt,
                                  int32_t j,
                                  CompactBranchType is_compact_branch) {
1107
  DCHECK(rs.is_valid() && rt.is_valid() && (is_int16(j) || is_uint16(j)));
1108 1109
  Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
      | (j & kImm16Mask);
1110
  emit(instr, is_compact_branch);
1111 1112 1113
}


1114 1115 1116
void Assembler::GenInstrImmediate(Opcode opcode, Register rs, SecondaryField SF,
                                  int32_t j,
                                  CompactBranchType is_compact_branch) {
1117
  DCHECK(rs.is_valid() && (is_int16(j) || is_uint16(j)));
1118
  Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask);
1119
  emit(instr, is_compact_branch);
1120 1121 1122
}


1123 1124 1125
void Assembler::GenInstrImmediate(Opcode opcode, Register rs, FPURegister ft,
                                  int32_t j,
                                  CompactBranchType is_compact_branch) {
1126
  DCHECK(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j)));
1127 1128
  Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift)
      | (j & kImm16Mask);
1129
  emit(instr, is_compact_branch);
1130 1131 1132
}


1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144
void Assembler::GenInstrImmediate(Opcode opcode, Register rs, int32_t offset21,
                                  CompactBranchType is_compact_branch) {
  DCHECK(rs.is_valid() && (is_int21(offset21)));
  Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask);
  emit(instr, is_compact_branch);
}


void Assembler::GenInstrImmediate(Opcode opcode, Register rs,
                                  uint32_t offset21) {
  DCHECK(rs.is_valid() && (is_uint21(offset21)));
  Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask);
1145 1146 1147 1148
  emit(instr);
}


1149 1150
void Assembler::GenInstrImmediate(Opcode opcode, int32_t offset26,
                                  CompactBranchType is_compact_branch) {
1151 1152
  DCHECK(is_int26(offset26));
  Instr instr = opcode | (offset26 & kImm26Mask);
1153
  emit(instr, is_compact_branch);
1154 1155 1156
}


1157
void Assembler::GenInstrJump(Opcode opcode,
1158
                             uint32_t address) {
1159
  BlockTrampolinePoolScope block_trampoline_pool(this);
1160
  DCHECK(is_uint26(address));
1161 1162
  Instr instr = opcode | address;
  emit(instr);
1163 1164 1165 1166
  BlockTrampolinePoolFor(1);  // For associated delay slot.
}


1167 1168 1169
// Returns the next free trampoline entry.
int32_t Assembler::get_trampoline_entry(int32_t pos) {
  int32_t trampoline_entry = kInvalidSlotPos;
1170

1171 1172 1173
  if (!internal_trampoline_exception_) {
    if (trampoline_.start() > pos) {
     trampoline_entry = trampoline_.take_slot();
1174
    }
1175 1176 1177

    if (kInvalidSlotPos == trampoline_entry) {
      internal_trampoline_exception_ = true;
1178 1179
    }
  }
1180
  return trampoline_entry;
1181 1182 1183
}


1184 1185
uint32_t Assembler::jump_address(Label* L) {
  int32_t target_pos;
1186

1187 1188 1189 1190 1191 1192 1193 1194 1195
  if (L->is_bound()) {
    target_pos = L->pos();
  } else {
    if (L->is_linked()) {
      target_pos = L->pos();  // L's link.
      L->link_to(pc_offset());
    } else {
      L->link_to(pc_offset());
      return kEndOfJumpChain;
1196
    }
1197
  }
1198

1199
  uint32_t imm = reinterpret_cast<uint32_t>(buffer_) + target_pos;
1200
  DCHECK((imm & 3) == 0);
1201 1202

  return imm;
1203 1204 1205
}


1206
int32_t Assembler::branch_offset_helper(Label* L, OffsetSize bits) {
1207
  int32_t target_pos;
1208
  int32_t pad = IsPrevInstrCompactBranch() ? kInstrSize : 0;
1209 1210 1211 1212 1213 1214

  if (L->is_bound()) {
    target_pos = L->pos();
  } else {
    if (L->is_linked()) {
      target_pos = L->pos();
1215
      L->link_to(pc_offset() + pad);
1216
    } else {
1217
      L->link_to(pc_offset() + pad);
1218 1219 1220 1221 1222 1223 1224 1225
      if (!trampoline_emitted_) {
        unbound_labels_count_++;
        next_buffer_check_ -= kTrampolineSlotsSize;
      }
      return kEndOfChain;
    }
  }

1226 1227
  int32_t offset = target_pos - (pc_offset() + kBranchPCOffset + pad);
  DCHECK(is_intn(offset, bits + 2));
1228 1229 1230 1231 1232 1233
  DCHECK((offset & 3) == 0);

  return offset;
}


1234 1235 1236 1237
void Assembler::label_at_put(Label* L, int at_offset) {
  int target_pos;
  if (L->is_bound()) {
    target_pos = L->pos();
1238
    instr_at_put(at_offset, target_pos + (Code::kHeaderSize - kHeapObjectTag));
1239 1240
  } else {
    if (L->is_linked()) {
1241 1242
      target_pos = L->pos();  // L's link.
      int32_t imm18 = target_pos - at_offset;
1243
      DCHECK((imm18 & 3) == 0);
1244
      int32_t imm16 = imm18 >> 2;
1245
      DCHECK(is_int16(imm16));
1246
      instr_at_put(at_offset, (imm16 & kImm16Mask));
1247 1248
    } else {
      target_pos = kEndOfChain;
1249
      instr_at_put(at_offset, 0);
1250 1251 1252 1253
      if (!trampoline_emitted_) {
        unbound_labels_count_++;
        next_buffer_check_ -= kTrampolineSlotsSize;
      }
1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271
    }
    L->link_to(at_offset);
  }
}


//------- Branch and jump instructions --------

void Assembler::b(int16_t offset) {
  beq(zero_reg, zero_reg, offset);
}


void Assembler::bal(int16_t offset) {
  bgezal(zero_reg, offset);
}


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void Assembler::bc(int32_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  GenInstrImmediate(BC, offset, CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::balc(int32_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  GenInstrImmediate(BALC, offset, CompactBranchType::COMPACT_BRANCH);
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}


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void Assembler::beq(Register rs, Register rt, int16_t offset) {
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrImmediate(BEQ, rs, rt, offset);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


void Assembler::bgez(Register rs, int16_t offset) {
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrImmediate(REGIMM, rs, BGEZ, offset);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


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void Assembler::bgezc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(!(rt.is(zero_reg)));
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  GenInstrImmediate(BLEZL, rt, rt, offset, CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::bgeuc(Register rs, Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(!(rs.is(zero_reg)));
  DCHECK(!(rt.is(zero_reg)));
  DCHECK(rs.code() != rt.code());
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  GenInstrImmediate(BLEZ, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::bgec(Register rs, Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(!(rs.is(zero_reg)));
  DCHECK(!(rt.is(zero_reg)));
  DCHECK(rs.code() != rt.code());
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  GenInstrImmediate(BLEZL, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
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}


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void Assembler::bgezal(Register rs, int16_t offset) {
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  DCHECK(!IsMipsArchVariant(kMips32r6) || rs.is(zero_reg));
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrImmediate(REGIMM, rs, BGEZAL, offset);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


void Assembler::bgtz(Register rs, int16_t offset) {
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrImmediate(BGTZ, rs, zero_reg, offset);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


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void Assembler::bgtzc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(!(rt.is(zero_reg)));
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  GenInstrImmediate(BGTZL, zero_reg, rt, offset,
                    CompactBranchType::COMPACT_BRANCH);
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}


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void Assembler::blez(Register rs, int16_t offset) {
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrImmediate(BLEZ, rs, zero_reg, offset);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


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void Assembler::blezc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(!(rt.is(zero_reg)));
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  GenInstrImmediate(BLEZL, zero_reg, rt, offset,
                    CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::bltzc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(!rt.is(zero_reg));
  GenInstrImmediate(BGTZL, rt, rt, offset, CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::bltuc(Register rs, Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(!(rs.is(zero_reg)));
  DCHECK(!(rt.is(zero_reg)));
  DCHECK(rs.code() != rt.code());
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  GenInstrImmediate(BGTZ, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::bltc(Register rs, Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(!rs.is(zero_reg));
  DCHECK(!rt.is(zero_reg));
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  DCHECK(rs.code() != rt.code());
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  GenInstrImmediate(BGTZL, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
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}


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void Assembler::bltz(Register rs, int16_t offset) {
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrImmediate(REGIMM, rs, BLTZ, offset);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


void Assembler::bltzal(Register rs, int16_t offset) {
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  DCHECK(!IsMipsArchVariant(kMips32r6) || rs.is(zero_reg));
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrImmediate(REGIMM, rs, BLTZAL, offset);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


void Assembler::bne(Register rs, Register rt, int16_t offset) {
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrImmediate(BNE, rs, rt, offset);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


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void Assembler::bovc(Register rs, Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  if (rs.code() >= rt.code()) {
    GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
  } else {
    GenInstrImmediate(ADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
  }
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}


void Assembler::bnvc(Register rs, Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  if (rs.code() >= rt.code()) {
    GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
  } else {
    GenInstrImmediate(DADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
  }
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}


void Assembler::blezalc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(!(rt.is(zero_reg)));
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  GenInstrImmediate(BLEZ, zero_reg, rt, offset,
                    CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::bgezalc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(!(rt.is(zero_reg)));
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  GenInstrImmediate(BLEZ, rt, rt, offset, CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::bgezall(Register rs, int16_t offset) {
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  DCHECK(!IsMipsArchVariant(kMips32r6));
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  DCHECK(!(rs.is(zero_reg)));
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrImmediate(REGIMM, rs, BGEZALL, offset);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


void Assembler::bltzalc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(!(rt.is(zero_reg)));
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  GenInstrImmediate(BGTZ, rt, rt, offset, CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::bgtzalc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(!(rt.is(zero_reg)));
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  GenInstrImmediate(BGTZ, zero_reg, rt, offset,
                    CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::beqzalc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(!(rt.is(zero_reg)));
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  GenInstrImmediate(ADDI, zero_reg, rt, offset,
                    CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::bnezalc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(!(rt.is(zero_reg)));
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  GenInstrImmediate(DADDI, zero_reg, rt, offset,
                    CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::beqc(Register rs, Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(rs.code() != rt.code() && rs.code() != 0 && rt.code() != 0);
  if (rs.code() < rt.code()) {
    GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
  } else {
    GenInstrImmediate(ADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
  }
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}


void Assembler::beqzc(Register rs, int32_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(!(rs.is(zero_reg)));
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  GenInstrImmediate(POP66, rs, offset, CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::bnec(Register rs, Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(rs.code() != rt.code() && rs.code() != 0 && rt.code() != 0);
  if (rs.code() < rt.code()) {
    GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
  } else {
    GenInstrImmediate(DADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
  }
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}


void Assembler::bnezc(Register rs, int32_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(!(rs.is(zero_reg)));
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  GenInstrImmediate(POP76, rs, offset, CompactBranchType::COMPACT_BRANCH);
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}


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void Assembler::j(int32_t target) {
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#if DEBUG
  // Get pc of delay slot.
  uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize);
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  bool in_range = ((ipc ^ static_cast<uint32_t>(target)) >>
                   (kImm26Bits + kImmFieldShift)) == 0;
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  DCHECK(in_range && ((target & 3) == 0));
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#endif
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrJump(J, (target >> 2) & kImm26Mask);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


void Assembler::jr(Register rs) {
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  if (!IsMipsArchVariant(kMips32r6)) {
    BlockTrampolinePoolScope block_trampoline_pool(this);
    GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR);
    BlockTrampolinePoolFor(1);  // For associated delay slot.
  } else {
    jalr(rs, zero_reg);
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  }
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}


void Assembler::jal(int32_t target) {
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#ifdef DEBUG
  // Get pc of delay slot.
  uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize);
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  bool in_range = ((ipc ^ static_cast<uint32_t>(target)) >>
                   (kImm26Bits + kImmFieldShift)) == 0;
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  DCHECK(in_range && ((target & 3) == 0));
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#endif
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrJump(JAL, (target >> 2) & kImm26Mask);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


void Assembler::jalr(Register rs, Register rd) {
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  DCHECK(rs.code() != rd.code());
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


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void Assembler::jic(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  GenInstrImmediate(POP66, zero_reg, rt, offset);
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}


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void Assembler::jialc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  GenInstrImmediate(POP76, zero_reg, rt, offset);
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}


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// -------Data-processing-instructions---------
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// Arithmetic.

void Assembler::addu(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADDU);
}


void Assembler::addiu(Register rd, Register rs, int32_t j) {
  GenInstrImmediate(ADDIU, rs, rd, j);
}


void Assembler::subu(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUBU);
}


void Assembler::mul(Register rd, Register rs, Register rt) {
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  if (!IsMipsArchVariant(kMips32r6)) {
    GenInstrRegister(SPECIAL2, rs, rt, rd, 0, MUL);
  } else {
    GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH);
  }
}


void Assembler::mulu(Register rd, Register rs, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH_U);
}


void Assembler::muh(Register rd, Register rs, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH);
}


void Assembler::muhu(Register rd, Register rs, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH_U);
}


void Assembler::mod(Register rd, Register rs, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD);
}


void Assembler::modu(Register rd, Register rs, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD_U);
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}


void Assembler::mult(Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULT);
}


void Assembler::multu(Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULTU);
}


void Assembler::div(Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIV);
}


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void Assembler::div(Register rd, Register rs, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD);
}


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void Assembler::divu(Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU);
}


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void Assembler::divu(Register rd, Register rs, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U);
}


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// Logical.

void Assembler::and_(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND);
}


void Assembler::andi(Register rt, Register rs, int32_t j) {
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  DCHECK(is_uint16(j));
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  GenInstrImmediate(ANDI, rs, rt, j);
}


void Assembler::or_(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR);
}


void Assembler::ori(Register rt, Register rs, int32_t j) {
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  DCHECK(is_uint16(j));
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  GenInstrImmediate(ORI, rs, rt, j);
}


void Assembler::xor_(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR);
}


void Assembler::xori(Register rt, Register rs, int32_t j) {
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  DCHECK(is_uint16(j));
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  GenInstrImmediate(XORI, rs, rt, j);
}


void Assembler::nor(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR);
}


// Shifts.
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void Assembler::sll(Register rd,
                    Register rt,
                    uint16_t sa,
                    bool coming_from_nop) {
  // Don't allow nop instructions in the form sll zero_reg, zero_reg to be
  // generated using the sll instruction. They must be generated using
  // nop(int/NopMarkerTypes) or MarkCode(int/NopMarkerTypes) pseudo
  // instructions.
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  DCHECK(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg)));
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  GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SLL);
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}


void Assembler::sllv(Register rd, Register rt, Register rs) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV);
}


void Assembler::srl(Register rd, Register rt, uint16_t sa) {
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  GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRL);
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}


void Assembler::srlv(Register rd, Register rt, Register rs) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRLV);
}


void Assembler::sra(Register rd, Register rt, uint16_t sa) {
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  GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRA);
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}


void Assembler::srav(Register rd, Register rt, Register rs) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV);
}


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void Assembler::rotr(Register rd, Register rt, uint16_t sa) {
  // Should be called via MacroAssembler::Ror.
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  DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa));
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  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
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  Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift)
      | (rd.code() << kRdShift) | (sa << kSaShift) | SRL;
  emit(instr);
}


void Assembler::rotrv(Register rd, Register rt, Register rs) {
  // Should be called via MacroAssembler::Ror.
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  DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid());
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  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
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  Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift)
     | (rd.code() << kRdShift) | (1 << kSaShift) | SRLV;
  emit(instr);
}


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void Assembler::lsa(Register rd, Register rt, Register rs, uint8_t sa) {
  DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid());
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  DCHECK(sa <= 3);
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  DCHECK(IsMipsArchVariant(kMips32r6));
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  Instr instr = SPECIAL | rs.code() << kRsShift | rt.code() << kRtShift |
                rd.code() << kRdShift | sa << kSaShift | LSA;
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  emit(instr);
}


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// ------------Memory-instructions-------------
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// Helper for base-reg + offset, when offset is larger than int16.
void Assembler::LoadRegPlusOffsetToAt(const MemOperand& src) {
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  DCHECK(!src.rm().is(at));
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  lui(at, (src.offset_ >> kLuiShift) & kImm16Mask);
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  ori(at, at, src.offset_ & kImm16Mask);  // Load 32-bit offset.
  addu(at, at, src.rm());  // Add base register.
}


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void Assembler::lb(Register rd, const MemOperand& rs) {
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  if (is_int16(rs.offset_)) {
    GenInstrImmediate(LB, rs.rm(), rd, rs.offset_);
  } else {  // Offset > 16 bits, use multiple instructions to load.
    LoadRegPlusOffsetToAt(rs);
    GenInstrImmediate(LB, at, rd, 0);  // Equiv to lb(rd, MemOperand(at, 0));
  }
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}


void Assembler::lbu(Register rd, const MemOperand& rs) {
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  if (is_int16(rs.offset_)) {
    GenInstrImmediate(LBU, rs.rm(), rd, rs.offset_);
  } else {  // Offset > 16 bits, use multiple instructions to load.
    LoadRegPlusOffsetToAt(rs);
    GenInstrImmediate(LBU, at, rd, 0);  // Equiv to lbu(rd, MemOperand(at, 0));
  }
}


void Assembler::lh(Register rd, const MemOperand& rs) {
  if (is_int16(rs.offset_)) {
    GenInstrImmediate(LH, rs.rm(), rd, rs.offset_);
  } else {  // Offset > 16 bits, use multiple instructions to load.
    LoadRegPlusOffsetToAt(rs);
    GenInstrImmediate(LH, at, rd, 0);  // Equiv to lh(rd, MemOperand(at, 0));
  }
}


void Assembler::lhu(Register rd, const MemOperand& rs) {
  if (is_int16(rs.offset_)) {
    GenInstrImmediate(LHU, rs.rm(), rd, rs.offset_);
  } else {  // Offset > 16 bits, use multiple instructions to load.
    LoadRegPlusOffsetToAt(rs);
    GenInstrImmediate(LHU, at, rd, 0);  // Equiv to lhu(rd, MemOperand(at, 0));
  }
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}


void Assembler::lw(Register rd, const MemOperand& rs) {
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  if (is_int16(rs.offset_)) {
    GenInstrImmediate(LW, rs.rm(), rd, rs.offset_);
  } else {  // Offset > 16 bits, use multiple instructions to load.
    LoadRegPlusOffsetToAt(rs);
    GenInstrImmediate(LW, at, rd, 0);  // Equiv to lw(rd, MemOperand(at, 0));
  }
}


void Assembler::lwl(Register rd, const MemOperand& rs) {
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  DCHECK(is_int16(rs.offset_));
  DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) ||
         IsMipsArchVariant(kMips32r2));
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  GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_);
}


void Assembler::lwr(Register rd, const MemOperand& rs) {
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  DCHECK(is_int16(rs.offset_));
  DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) ||
         IsMipsArchVariant(kMips32r2));
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  GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_);
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}


void Assembler::sb(Register rd, const MemOperand& rs) {
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  if (is_int16(rs.offset_)) {
    GenInstrImmediate(SB, rs.rm(), rd, rs.offset_);
  } else {  // Offset > 16 bits, use multiple instructions to store.
    LoadRegPlusOffsetToAt(rs);
    GenInstrImmediate(SB, at, rd, 0);  // Equiv to sb(rd, MemOperand(at, 0));
  }
}


void Assembler::sh(Register rd, const MemOperand& rs) {
  if (is_int16(rs.offset_)) {
    GenInstrImmediate(SH, rs.rm(), rd, rs.offset_);
  } else {  // Offset > 16 bits, use multiple instructions to store.
    LoadRegPlusOffsetToAt(rs);
    GenInstrImmediate(SH, at, rd, 0);  // Equiv to sh(rd, MemOperand(at, 0));
  }
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}


void Assembler::sw(Register rd, const MemOperand& rs) {
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  if (is_int16(rs.offset_)) {
    GenInstrImmediate(SW, rs.rm(), rd, rs.offset_);
  } else {  // Offset > 16 bits, use multiple instructions to store.
    LoadRegPlusOffsetToAt(rs);
    GenInstrImmediate(SW, at, rd, 0);  // Equiv to sw(rd, MemOperand(at, 0));
  }
}


void Assembler::swl(Register rd, const MemOperand& rs) {
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  DCHECK(is_int16(rs.offset_));
  DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) ||
         IsMipsArchVariant(kMips32r2));
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  GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_);
}


void Assembler::swr(Register rd, const MemOperand& rs) {
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  DCHECK(is_int16(rs.offset_));
  DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) ||
         IsMipsArchVariant(kMips32r2));
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  GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_);
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}


void Assembler::lui(Register rd, int32_t j) {
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  DCHECK(is_uint16(j));
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  GenInstrImmediate(LUI, zero_reg, rd, j);
}


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void Assembler::aui(Register rt, Register rs, int32_t j) {
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  // This instruction uses same opcode as 'lui'. The difference in encoding is
  // 'lui' has zero reg. for rs field.
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  DCHECK(!(rs.is(zero_reg)));
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  DCHECK(is_uint16(j));
  GenInstrImmediate(LUI, rs, rt, j);
}

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// ---------PC-Relative instructions-----------

void Assembler::addiupc(Register rs, int32_t imm19) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(rs.is_valid() && is_int19(imm19));
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  uint32_t imm21 = ADDIUPC << kImm19Bits | (imm19 & kImm19Mask);
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  GenInstrImmediate(PCREL, rs, imm21);
}


void Assembler::lwpc(Register rs, int32_t offset19) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(rs.is_valid() && is_int19(offset19));
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  uint32_t imm21 = LWPC << kImm19Bits | (offset19 & kImm19Mask);
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  GenInstrImmediate(PCREL, rs, imm21);
}


void Assembler::auipc(Register rs, int16_t imm16) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(rs.is_valid());
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  uint32_t imm21 = AUIPC << kImm16Bits | (imm16 & kImm16Mask);
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  GenInstrImmediate(PCREL, rs, imm21);
}


void Assembler::aluipc(Register rs, int16_t imm16) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(rs.is_valid());
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  uint32_t imm21 = ALUIPC << kImm16Bits | (imm16 & kImm16Mask);
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  GenInstrImmediate(PCREL, rs, imm21);
}


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// -------------Misc-instructions--------------
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// Break / Trap instructions.
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void Assembler::break_(uint32_t code, bool break_as_stop) {
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  DCHECK((code & ~0xfffff) == 0);
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  // We need to invalidate breaks that could be stops as well because the
  // simulator expects a char pointer after the stop instruction.
  // See constants-mips.h for explanation.
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  DCHECK((break_as_stop &&
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          code <= kMaxStopCode &&
          code > kMaxWatchpointCode) ||
         (!break_as_stop &&
          (code > kMaxStopCode ||
           code <= kMaxWatchpointCode)));
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  Instr break_instr = SPECIAL | BREAK | (code << 6);
  emit(break_instr);
}


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void Assembler::stop(const char* msg, uint32_t code) {
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  DCHECK(code > kMaxWatchpointCode);
  DCHECK(code <= kMaxStopCode);
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#if V8_HOST_ARCH_MIPS
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  break_(0x54321);
#else  // V8_HOST_ARCH_MIPS
  BlockTrampolinePoolFor(2);
  // The Simulator will handle the stop instruction and get the message address.
  // On MIPS stop() is just a special kind of break_().
  break_(code, true);
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  // Do not embed the message string address! We used to do this, but that
  // made snapshots created from position-independent executable builds
  // non-deterministic.
  // TODO(yangguo): remove this field entirely.
  nop();
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#endif
}


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void Assembler::tge(Register rs, Register rt, uint16_t code) {
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  DCHECK(is_uint10(code));
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  Instr instr = SPECIAL | TGE | rs.code() << kRsShift
      | rt.code() << kRtShift | code << 6;
  emit(instr);
}


void Assembler::tgeu(Register rs, Register rt, uint16_t code) {
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  DCHECK(is_uint10(code));
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  Instr instr = SPECIAL | TGEU | rs.code() << kRsShift
      | rt.code() << kRtShift | code << 6;
  emit(instr);
}


void Assembler::tlt(Register rs, Register rt, uint16_t code) {
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  DCHECK(is_uint10(code));
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  Instr instr =
      SPECIAL | TLT | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
  emit(instr);
}


void Assembler::tltu(Register rs, Register rt, uint16_t code) {
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  DCHECK(is_uint10(code));
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  Instr instr =
      SPECIAL | TLTU | rs.code() << kRsShift
      | rt.code() << kRtShift | code << 6;
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  emit(instr);
}


void Assembler::teq(Register rs, Register rt, uint16_t code) {
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  DCHECK(is_uint10(code));
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  Instr instr =
      SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
  emit(instr);
}


void Assembler::tne(Register rs, Register rt, uint16_t code) {
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  DCHECK(is_uint10(code));
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  Instr instr =
      SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
  emit(instr);
}

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void Assembler::sync() {
  Instr sync_instr = SPECIAL | SYNC;
  emit(sync_instr);
}
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// Move from HI/LO register.

void Assembler::mfhi(Register rd) {
  GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI);
}


void Assembler::mflo(Register rd) {
  GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO);
}


// Set on less than instructions.
void Assembler::slt(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLT);
}


void Assembler::sltu(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLTU);
}


void Assembler::slti(Register rt, Register rs, int32_t j) {
  GenInstrImmediate(SLTI, rs, rt, j);
}


void Assembler::sltiu(Register rt, Register rs, int32_t j) {
  GenInstrImmediate(SLTIU, rs, rt, j);
}


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// Conditional move.
void Assembler::movz(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ);
}


void Assembler::movn(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN);
}


void Assembler::movt(Register rd, Register rs, uint16_t cc) {
  Register rt;
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  rt.reg_code = (cc & 0x0007) << 2 | 1;
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  GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
}


void Assembler::movf(Register rd, Register rs, uint16_t cc) {
  Register rt;
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  rt.reg_code = (cc & 0x0007) << 2 | 0;
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  GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
}


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void Assembler::seleqz(Register rd, Register rs, Register rt) {
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  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELEQZ_S);
}


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// Bit twiddling.
void Assembler::clz(Register rd, Register rs) {
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  if (!IsMipsArchVariant(kMips32r6)) {
    // Clz instr requires same GPR number in 'rd' and 'rt' fields.
    GenInstrRegister(SPECIAL2, rs, rd, rd, 0, CLZ);
  } else {
    GenInstrRegister(SPECIAL, rs, zero_reg, rd, 1, CLZ_R6);
  }
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}


void Assembler::ins_(Register rt, Register rs, uint16_t pos, uint16_t size) {
  // Should be called via MacroAssembler::Ins.
  // Ins instr has 'rt' field as dest, and two uint5: msb, lsb.
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  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
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  GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, INS);
}


void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) {
  // Should be called via MacroAssembler::Ext.
  // Ext instr has 'rt' field as dest, and two uint5: msb, lsb.
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  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
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  GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT);
}


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void Assembler::bitswap(Register rd, Register rt) {
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  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL3, zero_reg, rt, rd, 0, BSHFL);
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}


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void Assembler::pref(int32_t hint, const MemOperand& rs) {
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  DCHECK(!IsMipsArchVariant(kLoongson));
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  DCHECK(is_uint5(hint) && is_uint16(rs.offset_));
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  Instr instr = PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift)
      | (rs.offset_);
  emit(instr);
}


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void Assembler::align(Register rd, Register rs, Register rt, uint8_t bp) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(is_uint3(bp));
  uint16_t sa = (ALIGN << kBp2Bits) | bp;
  GenInstrRegister(SPECIAL3, rs, rt, rd, sa, BSHFL);
}

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// Byte swap.
void Assembler::wsbh(Register rd, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL3, zero_reg, rt, rd, WSBH, BSHFL);
}

void Assembler::seh(Register rd, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL3, zero_reg, rt, rd, SEH, BSHFL);
}

void Assembler::seb(Register rd, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL3, zero_reg, rt, rd, SEB, BSHFL);
}
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// --------Coprocessor-instructions----------------
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// Load, store, move.
void Assembler::lwc1(FPURegister fd, const MemOperand& src) {
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  if (is_int16(src.offset_)) {
    GenInstrImmediate(LWC1, src.rm(), fd, src.offset_);
  } else {  // Offset > 16 bits, use multiple instructions to load.
    LoadRegPlusOffsetToAt(src);
    GenInstrImmediate(LWC1, at, fd, 0);
  }
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}


void Assembler::ldc1(FPURegister fd, const MemOperand& src) {
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  // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
  // load to two 32-bit loads.
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  if (IsFp32Mode()) {  // fp32 mode.
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    if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
      GenInstrImmediate(LWC1, src.rm(), fd,
                        src.offset_ + Register::kMantissaOffset);
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      FPURegister nextfpreg;
      nextfpreg.setcode(fd.code() + 1);
      GenInstrImmediate(LWC1, src.rm(), nextfpreg,
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                        src.offset_ + Register::kExponentOffset);
    } else {  // Offset > 16 bits, use multiple instructions to load.
      LoadRegPlusOffsetToAt(src);
      GenInstrImmediate(LWC1, at, fd, Register::kMantissaOffset);
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      FPURegister nextfpreg;
      nextfpreg.setcode(fd.code() + 1);
      GenInstrImmediate(LWC1, at, nextfpreg, Register::kExponentOffset);
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    }
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  } else {
    DCHECK(IsFp64Mode() || IsFpxxMode());
    // Currently we support FPXX and FP64 on Mips32r2 and Mips32r6
    DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
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    if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
      GenInstrImmediate(LWC1, src.rm(), fd,
                        src.offset_ + Register::kMantissaOffset);
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      GenInstrImmediate(LW, src.rm(), at,
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                        src.offset_ + Register::kExponentOffset);
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      mthc1(at, fd);
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    } else {  // Offset > 16 bits, use multiple instructions to load.
      LoadRegPlusOffsetToAt(src);
      GenInstrImmediate(LWC1, at, fd, Register::kMantissaOffset);
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      GenInstrImmediate(LW, at, at, Register::kExponentOffset);
      mthc1(at, fd);
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    }
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  }
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}


void Assembler::swc1(FPURegister fd, const MemOperand& src) {
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  if (is_int16(src.offset_)) {
    GenInstrImmediate(SWC1, src.rm(), fd, src.offset_);
  } else {  // Offset > 16 bits, use multiple instructions to load.
    LoadRegPlusOffsetToAt(src);
    GenInstrImmediate(SWC1, at, fd, 0);
  }
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}


void Assembler::sdc1(FPURegister fd, const MemOperand& src) {
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  // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
  // store to two 32-bit stores.
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  DCHECK(!src.rm().is(at));
  DCHECK(!src.rm().is(t8));
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  if (IsFp32Mode()) {  // fp32 mode.
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    if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
      GenInstrImmediate(SWC1, src.rm(), fd,
                        src.offset_ + Register::kMantissaOffset);
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      FPURegister nextfpreg;
      nextfpreg.setcode(fd.code() + 1);
      GenInstrImmediate(SWC1, src.rm(), nextfpreg,
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                        src.offset_ + Register::kExponentOffset);
    } else {  // Offset > 16 bits, use multiple instructions to load.
      LoadRegPlusOffsetToAt(src);
      GenInstrImmediate(SWC1, at, fd, Register::kMantissaOffset);
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      FPURegister nextfpreg;
      nextfpreg.setcode(fd.code() + 1);
      GenInstrImmediate(SWC1, at, nextfpreg, Register::kExponentOffset);
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    }
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  } else {
    DCHECK(IsFp64Mode() || IsFpxxMode());
    // Currently we support FPXX and FP64 on Mips32r2 and Mips32r6
    DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
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    if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
      GenInstrImmediate(SWC1, src.rm(), fd,
                        src.offset_ + Register::kMantissaOffset);
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      mfhc1(at, fd);
      GenInstrImmediate(SW, src.rm(), at,
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                        src.offset_ + Register::kExponentOffset);
    } else {  // Offset > 16 bits, use multiple instructions to load.
      LoadRegPlusOffsetToAt(src);
      GenInstrImmediate(SWC1, at, fd, Register::kMantissaOffset);
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      mfhc1(t8, fd);
      GenInstrImmediate(SW, at, t8, Register::kExponentOffset);
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    }
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  }
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}


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void Assembler::mtc1(Register rt, FPURegister fs) {
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  GenInstrRegister(COP1, MTC1, rt, fs, f0);
}


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void Assembler::mthc1(Register rt, FPURegister fs) {
  GenInstrRegister(COP1, MTHC1, rt, fs, f0);
}


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void Assembler::mfc1(Register rt, FPURegister fs) {
  GenInstrRegister(COP1, MFC1, rt, fs, f0);
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}


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void Assembler::mfhc1(Register rt, FPURegister fs) {
  GenInstrRegister(COP1, MFHC1, rt, fs, f0);
}


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void Assembler::ctc1(Register rt, FPUControlRegister fs) {
  GenInstrRegister(COP1, CTC1, rt, fs);
}


void Assembler::cfc1(Register rt, FPUControlRegister fs) {
  GenInstrRegister(COP1, CFC1, rt, fs);
}

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void Assembler::DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi) {
  uint64_t i;
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  memcpy(&i, &d, 8);
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  *lo = i & 0xffffffff;
  *hi = i >> 32;
}
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void Assembler::movn_s(FPURegister fd, FPURegister fs, Register rt) {
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  DCHECK(!IsMipsArchVariant(kMips32r6));
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  GenInstrRegister(COP1, S, rt, fs, fd, MOVN_C);
}


void Assembler::movn_d(FPURegister fd, FPURegister fs, Register rt) {
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  DCHECK(!IsMipsArchVariant(kMips32r6));
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  GenInstrRegister(COP1, D, rt, fs, fd, MOVN_C);
}


void Assembler::sel(SecondaryField fmt, FPURegister fd, FPURegister fs,
                    FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK((fmt == D) || (fmt == S));

  GenInstrRegister(COP1, fmt, ft, fs, fd, SEL);
}


void Assembler::sel_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  sel(S, fd, fs, ft);
}


void Assembler::sel_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  sel(D, fd, fs, ft);
}


void Assembler::seleqz(SecondaryField fmt, FPURegister fd, FPURegister fs,
                       FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK((fmt == D) || (fmt == S));
  GenInstrRegister(COP1, fmt, ft, fs, fd, SELEQZ_C);
}


void Assembler::selnez(Register rd, Register rs, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELNEZ_S);
}


void Assembler::selnez(SecondaryField fmt, FPURegister fd, FPURegister fs,
                       FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK((fmt == D) || (fmt == S));
  GenInstrRegister(COP1, fmt, ft, fs, fd, SELNEZ_C);
}


void Assembler::seleqz_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  seleqz(D, fd, fs, ft);
}


void Assembler::seleqz_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  seleqz(S, fd, fs, ft);
}


void Assembler::selnez_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  selnez(D, fd, fs, ft);
}


void Assembler::selnez_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  selnez(S, fd, fs, ft);
}


void Assembler::movz_s(FPURegister fd, FPURegister fs, Register rt) {
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  DCHECK(!IsMipsArchVariant(kMips32r6));
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  GenInstrRegister(COP1, S, rt, fs, fd, MOVZ_C);
}


void Assembler::movz_d(FPURegister fd, FPURegister fs, Register rt) {
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  DCHECK(!IsMipsArchVariant(kMips32r6));
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  GenInstrRegister(COP1, D, rt, fs, fd, MOVZ_C);
}


void Assembler::movt_s(FPURegister fd, FPURegister fs, uint16_t cc) {
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  DCHECK(!IsMipsArchVariant(kMips32r6));
2395
  FPURegister ft;
2396
  ft.reg_code = (cc & 0x0007) << 2 | 1;
2397 2398 2399 2400 2401
  GenInstrRegister(COP1, S, ft, fs, fd, MOVF);
}


void Assembler::movt_d(FPURegister fd, FPURegister fs, uint16_t cc) {
2402
  DCHECK(!IsMipsArchVariant(kMips32r6));
2403
  FPURegister ft;
2404
  ft.reg_code = (cc & 0x0007) << 2 | 1;
2405 2406 2407 2408 2409
  GenInstrRegister(COP1, D, ft, fs, fd, MOVF);
}


void Assembler::movf_s(FPURegister fd, FPURegister fs, uint16_t cc) {
2410
  DCHECK(!IsMipsArchVariant(kMips32r6));
2411
  FPURegister ft;
2412
  ft.reg_code = (cc & 0x0007) << 2 | 0;
2413 2414 2415 2416 2417
  GenInstrRegister(COP1, S, ft, fs, fd, MOVF);
}


void Assembler::movf_d(FPURegister fd, FPURegister fs, uint16_t cc) {
2418
  DCHECK(!IsMipsArchVariant(kMips32r6));
2419
  FPURegister ft;
2420
  ft.reg_code = (cc & 0x0007) << 2 | 0;
2421 2422 2423 2424
  GenInstrRegister(COP1, D, ft, fs, fd, MOVF);
}


2425 2426
// Arithmetic.

2427
void Assembler::add_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2428
  GenInstrRegister(COP1, S, ft, fs, fd, ADD_S);
2429 2430 2431
}


2432 2433 2434 2435 2436
void Assembler::add_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  GenInstrRegister(COP1, D, ft, fs, fd, ADD_D);
}


2437
void Assembler::sub_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2438
  GenInstrRegister(COP1, S, ft, fs, fd, SUB_S);
2439 2440 2441
}


2442 2443 2444 2445 2446
void Assembler::sub_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  GenInstrRegister(COP1, D, ft, fs, fd, SUB_D);
}


2447
void Assembler::mul_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2448
  GenInstrRegister(COP1, S, ft, fs, fd, MUL_S);
2449 2450 2451
}


2452 2453 2454 2455
void Assembler::mul_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  GenInstrRegister(COP1, D, ft, fs, fd, MUL_D);
}

2456 2457 2458 2459 2460
void Assembler::madd_s(FPURegister fd, FPURegister fr, FPURegister fs,
                       FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r2));
  GenInstrRegister(COP1X, fr, ft, fs, fd, MADD_S);
}
2461

2462 2463
void Assembler::madd_d(FPURegister fd, FPURegister fr, FPURegister fs,
    FPURegister ft) {
2464
  DCHECK(IsMipsArchVariant(kMips32r2));
2465 2466 2467
  GenInstrRegister(COP1X, fr, ft, fs, fd, MADD_D);
}

2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498
void Assembler::msub_s(FPURegister fd, FPURegister fr, FPURegister fs,
                       FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r2));
  GenInstrRegister(COP1X, fr, ft, fs, fd, MSUB_S);
}

void Assembler::msub_d(FPURegister fd, FPURegister fr, FPURegister fs,
                       FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r2));
  GenInstrRegister(COP1X, fr, ft, fs, fd, MSUB_D);
}

void Assembler::maddf_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(COP1, S, ft, fs, fd, MADDF_S);
}

void Assembler::maddf_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(COP1, D, ft, fs, fd, MADDF_D);
}

void Assembler::msubf_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(COP1, S, ft, fs, fd, MSUBF_S);
}

void Assembler::msubf_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(COP1, D, ft, fs, fd, MSUBF_D);
}
2499

2500
void Assembler::div_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2501
  GenInstrRegister(COP1, S, ft, fs, fd, DIV_S);
2502 2503 2504
}


2505 2506 2507 2508 2509
void Assembler::div_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  GenInstrRegister(COP1, D, ft, fs, fd, DIV_D);
}


2510
void Assembler::abs_s(FPURegister fd, FPURegister fs) {
2511
  GenInstrRegister(COP1, S, f0, fs, fd, ABS_S);
2512 2513 2514
}


2515 2516
void Assembler::abs_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, ABS_D);
2517 2518 2519
}


2520
void Assembler::mov_d(FPURegister fd, FPURegister fs) {
2521
  GenInstrRegister(COP1, D, f0, fs, fd, MOV_D);
2522 2523 2524 2525
}


void Assembler::mov_s(FPURegister fd, FPURegister fs) {
2526
  GenInstrRegister(COP1, S, f0, fs, fd, MOV_S);
2527 2528 2529
}


2530
void Assembler::neg_s(FPURegister fd, FPURegister fs) {
2531
  GenInstrRegister(COP1, S, f0, fs, fd, NEG_S);
2532 2533 2534
}


2535 2536 2537 2538 2539
void Assembler::neg_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, NEG_D);
}


2540
void Assembler::sqrt_s(FPURegister fd, FPURegister fs) {
2541
  GenInstrRegister(COP1, S, f0, fs, fd, SQRT_S);
2542 2543 2544
}


2545 2546
void Assembler::sqrt_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, SQRT_D);
2547 2548 2549
}


2550
void Assembler::rsqrt_s(FPURegister fd, FPURegister fs) {
2551
  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
2552 2553 2554 2555 2556
  GenInstrRegister(COP1, S, f0, fs, fd, RSQRT_S);
}


void Assembler::rsqrt_d(FPURegister fd, FPURegister fs) {
2557
  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
2558 2559 2560 2561 2562
  GenInstrRegister(COP1, D, f0, fs, fd, RSQRT_D);
}


void Assembler::recip_d(FPURegister fd, FPURegister fs) {
2563
  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
2564 2565 2566 2567 2568
  GenInstrRegister(COP1, D, f0, fs, fd, RECIP_D);
}


void Assembler::recip_s(FPURegister fd, FPURegister fs) {
2569
  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
2570 2571 2572 2573
  GenInstrRegister(COP1, S, f0, fs, fd, RECIP_S);
}


2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585
// Conversions.

void Assembler::cvt_w_s(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, S, f0, fs, fd, CVT_W_S);
}


void Assembler::cvt_w_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, CVT_W_D);
}


2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625
void Assembler::trunc_w_s(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_W_S);
}


void Assembler::trunc_w_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, TRUNC_W_D);
}


void Assembler::round_w_s(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, S, f0, fs, fd, ROUND_W_S);
}


void Assembler::round_w_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, ROUND_W_D);
}


void Assembler::floor_w_s(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, S, f0, fs, fd, FLOOR_W_S);
}


void Assembler::floor_w_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, FLOOR_W_D);
}


void Assembler::ceil_w_s(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, S, f0, fs, fd, CEIL_W_S);
}


void Assembler::ceil_w_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, CEIL_W_D);
}


2626 2627 2628 2629 2630
void Assembler::rint_s(FPURegister fd, FPURegister fs) { rint(S, fd, fs); }


void Assembler::rint(SecondaryField fmt, FPURegister fd, FPURegister fs) {
  DCHECK(IsMipsArchVariant(kMips32r6));
2631
  DCHECK((fmt == D) || (fmt == S));
2632 2633 2634 2635 2636 2637 2638
  GenInstrRegister(COP1, fmt, f0, fs, fd, RINT);
}


void Assembler::rint_d(FPURegister fd, FPURegister fs) { rint(D, fd, fs); }


2639
void Assembler::cvt_l_s(FPURegister fd, FPURegister fs) {
2640 2641
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
2642 2643 2644 2645 2646
  GenInstrRegister(COP1, S, f0, fs, fd, CVT_L_S);
}


void Assembler::cvt_l_d(FPURegister fd, FPURegister fs) {
2647 2648
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
2649 2650 2651 2652
  GenInstrRegister(COP1, D, f0, fs, fd, CVT_L_D);
}


2653
void Assembler::trunc_l_s(FPURegister fd, FPURegister fs) {
2654 2655
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
2656 2657 2658 2659 2660
  GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_L_S);
}


void Assembler::trunc_l_d(FPURegister fd, FPURegister fs) {
2661 2662
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
2663 2664 2665 2666 2667
  GenInstrRegister(COP1, D, f0, fs, fd, TRUNC_L_D);
}


void Assembler::round_l_s(FPURegister fd, FPURegister fs) {
2668 2669
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
2670 2671 2672 2673 2674
  GenInstrRegister(COP1, S, f0, fs, fd, ROUND_L_S);
}


void Assembler::round_l_d(FPURegister fd, FPURegister fs) {
2675 2676
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
2677 2678 2679 2680 2681
  GenInstrRegister(COP1, D, f0, fs, fd, ROUND_L_D);
}


void Assembler::floor_l_s(FPURegister fd, FPURegister fs) {
2682 2683
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
2684 2685 2686 2687 2688
  GenInstrRegister(COP1, S, f0, fs, fd, FLOOR_L_S);
}


void Assembler::floor_l_d(FPURegister fd, FPURegister fs) {
2689 2690
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
2691 2692 2693 2694 2695
  GenInstrRegister(COP1, D, f0, fs, fd, FLOOR_L_D);
}


void Assembler::ceil_l_s(FPURegister fd, FPURegister fs) {
2696 2697
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
2698 2699 2700 2701 2702
  GenInstrRegister(COP1, S, f0, fs, fd, CEIL_L_S);
}


void Assembler::ceil_l_d(FPURegister fd, FPURegister fs) {
2703 2704
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
2705 2706 2707 2708
  GenInstrRegister(COP1, D, f0, fs, fd, CEIL_L_D);
}


2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720
void Assembler::class_s(FPURegister fd, FPURegister fs) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(COP1, S, f0, fs, fd, CLASS_S);
}


void Assembler::class_d(FPURegister fd, FPURegister fs) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(COP1, D, f0, fs, fd, CLASS_D);
}


2721 2722
void Assembler::min(SecondaryField fmt, FPURegister fd, FPURegister fs,
                    FPURegister ft) {
2723 2724 2725 2726 2727 2728
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK((fmt == D) || (fmt == S));
  GenInstrRegister(COP1, fmt, ft, fs, fd, MIN);
}


2729 2730
void Assembler::mina(SecondaryField fmt, FPURegister fd, FPURegister fs,
                     FPURegister ft) {
2731 2732 2733 2734 2735 2736
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK((fmt == D) || (fmt == S));
  GenInstrRegister(COP1, fmt, ft, fs, fd, MINA);
}


2737 2738
void Assembler::max(SecondaryField fmt, FPURegister fd, FPURegister fs,
                    FPURegister ft) {
2739 2740 2741 2742 2743 2744
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK((fmt == D) || (fmt == S));
  GenInstrRegister(COP1, fmt, ft, fs, fd, MAX);
}


2745 2746
void Assembler::maxa(SecondaryField fmt, FPURegister fd, FPURegister fs,
                     FPURegister ft) {
2747 2748 2749 2750 2751 2752
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK((fmt == D) || (fmt == S));
  GenInstrRegister(COP1, fmt, ft, fs, fd, MAXA);
}


2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792
void Assembler::min_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  min(S, fd, fs, ft);
}


void Assembler::min_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  min(D, fd, fs, ft);
}


void Assembler::max_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  max(S, fd, fs, ft);
}


void Assembler::max_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  max(D, fd, fs, ft);
}


void Assembler::mina_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  mina(S, fd, fs, ft);
}


void Assembler::mina_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  mina(D, fd, fs, ft);
}


void Assembler::maxa_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  maxa(S, fd, fs, ft);
}


void Assembler::maxa_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  maxa(D, fd, fs, ft);
}


2793 2794 2795 2796 2797 2798
void Assembler::cvt_s_w(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, W, f0, fs, fd, CVT_S_W);
}


void Assembler::cvt_s_l(FPURegister fd, FPURegister fs) {
2799 2800
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815
  GenInstrRegister(COP1, L, f0, fs, fd, CVT_S_L);
}


void Assembler::cvt_s_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, CVT_S_D);
}


void Assembler::cvt_d_w(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, W, f0, fs, fd, CVT_D_W);
}


void Assembler::cvt_d_l(FPURegister fd, FPURegister fs) {
2816 2817
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
2818 2819 2820 2821 2822 2823 2824 2825 2826
  GenInstrRegister(COP1, L, f0, fs, fd, CVT_D_L);
}


void Assembler::cvt_d_s(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, S, f0, fs, fd, CVT_D_S);
}


2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837
// Conditions for >= MIPSr6.
void Assembler::cmp(FPUCondition cond, SecondaryField fmt,
    FPURegister fd, FPURegister fs, FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK((fmt & ~(31 << kRsShift)) == 0);
  Instr instr = COP1 | fmt | ft.code() << kFtShift |
      fs.code() << kFsShift | fd.code() << kFdShift | (0 << 5) | cond;
  emit(instr);
}


2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848
void Assembler::cmp_s(FPUCondition cond, FPURegister fd, FPURegister fs,
                      FPURegister ft) {
  cmp(cond, W, fd, fs, ft);
}

void Assembler::cmp_d(FPUCondition cond, FPURegister fd, FPURegister fs,
                      FPURegister ft) {
  cmp(cond, L, fd, fs, ft);
}


2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863
void Assembler::bc1eqz(int16_t offset, FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  Instr instr = COP1 | BC1EQZ | ft.code() << kFtShift | (offset & kImm16Mask);
  emit(instr);
}


void Assembler::bc1nez(int16_t offset, FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  Instr instr = COP1 | BC1NEZ | ft.code() << kFtShift | (offset & kImm16Mask);
  emit(instr);
}


// Conditions for < MIPSr6.
2864
void Assembler::c(FPUCondition cond, SecondaryField fmt,
2865
    FPURegister fs, FPURegister ft, uint16_t cc) {
2866
  DCHECK(is_uint3(cc));
2867
  DCHECK(fmt == S || fmt == D);
2868
  DCHECK((fmt & ~(31 << kRsShift)) == 0);
2869 2870 2871 2872 2873 2874
  Instr instr = COP1 | fmt | ft.code() << 16 | fs.code() << kFsShift
      | cc << 8 | 3 << 4 | cond;
  emit(instr);
}


2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886
void Assembler::c_s(FPUCondition cond, FPURegister fs, FPURegister ft,
                    uint16_t cc) {
  c(cond, S, fs, ft, cc);
}


void Assembler::c_d(FPUCondition cond, FPURegister fs, FPURegister ft,
                    uint16_t cc) {
  c(cond, D, fs, ft, cc);
}


2887 2888
void Assembler::fcmp(FPURegister src1, const double src2,
      FPUCondition cond) {
2889
  DCHECK(src2 == 0.0);
2890 2891 2892 2893 2894 2895
  mtc1(zero_reg, f14);
  cvt_d_w(f14, f14);
  c(cond, D, src1, f14, 0);
}


2896
void Assembler::bc1f(int16_t offset, uint16_t cc) {
2897
  DCHECK(is_uint3(cc));
2898 2899 2900 2901 2902 2903
  Instr instr = COP1 | BC1 | cc << 18 | 0 << 16 | (offset & kImm16Mask);
  emit(instr);
}


void Assembler::bc1t(int16_t offset, uint16_t cc) {
2904
  DCHECK(is_uint3(cc));
2905 2906 2907 2908 2909
  Instr instr = COP1 | BC1 | cc << 18 | 1 << 16 | (offset & kImm16Mask);
  emit(instr);
}


2910 2911
int Assembler::RelocateInternalReference(RelocInfo::Mode rmode, byte* pc,
                                         intptr_t pc_delta) {
2912
  Instr instr = instr_at(pc);
2913

2914
  if (RelocInfo::IsInternalReference(rmode)) {
2915
    int32_t* p = reinterpret_cast<int32_t*>(pc);
2916
    if (*p == 0) {
2917
      return 0;  // Number of instructions patched.
2918
    }
2919 2920
    *p += pc_delta;
    return 1;  // Number of instructions patched.
2921 2922 2923
  } else {
    DCHECK(RelocInfo::IsInternalReferenceEncoded(rmode));
    if (IsLui(instr)) {
2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934
      Instr instr1 = instr_at(pc + 0 * Assembler::kInstrSize);
      Instr instr2 = instr_at(pc + 1 * Assembler::kInstrSize);
      DCHECK(IsOri(instr2) || IsJicOrJialc(instr2));
      int32_t imm;
      if (IsJicOrJialc(instr2)) {
        imm = CreateTargetAddress(instr1, instr2);
      } else {
        imm = (instr1 & static_cast<int32_t>(kImm16Mask)) << kLuiShift;
        imm |= (instr2 & static_cast<int32_t>(kImm16Mask));
      }

2935 2936 2937 2938 2939
      if (imm == kEndOfJumpChain) {
        return 0;  // Number of instructions patched.
      }
      imm += pc_delta;
      DCHECK((imm & 3) == 0);
2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953
      instr1 &= ~kImm16Mask;
      instr2 &= ~kImm16Mask;

      if (IsJicOrJialc(instr2)) {
        uint32_t lui_offset_u, jic_offset_u;
        Assembler::UnpackTargetAddressUnsigned(imm, lui_offset_u, jic_offset_u);
        instr_at_put(pc + 0 * Assembler::kInstrSize, instr1 | lui_offset_u);
        instr_at_put(pc + 1 * Assembler::kInstrSize, instr2 | jic_offset_u);
      } else {
        instr_at_put(pc + 0 * Assembler::kInstrSize,
                     instr1 | ((imm >> kLuiShift) & kImm16Mask));
        instr_at_put(pc + 1 * Assembler::kInstrSize,
                     instr2 | (imm & kImm16Mask));
      }
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      return 2;  // Number of instructions patched.
    } else {
      UNREACHABLE();
      return 0;
    }
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  }
}


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void Assembler::GrowBuffer() {
  if (!own_buffer_) FATAL("external code buffer is too small");

  // Compute new buffer size.
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  CodeDesc desc;  // The new buffer.
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  if (buffer_size_ < 1 * MB) {
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    desc.buffer_size = 2*buffer_size_;
  } else {
    desc.buffer_size = buffer_size_ + 1*MB;
  }
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  CHECK_GT(desc.buffer_size, 0);  // No overflow.
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2975
  // Set up new buffer.
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  desc.buffer = NewArray<byte>(desc.buffer_size);
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  desc.origin = this;
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  desc.instr_size = pc_offset();
  desc.reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();

  // Copy the data.
  int pc_delta = desc.buffer - buffer_;
  int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_);
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  MemMove(desc.buffer, buffer_, desc.instr_size);
  MemMove(reloc_info_writer.pos() + rc_delta, reloc_info_writer.pos(),
          desc.reloc_size);
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  // Switch buffers.
  DeleteArray(buffer_);
  buffer_ = desc.buffer;
  buffer_size_ = desc.buffer_size;
  pc_ += pc_delta;
  reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
                               reloc_info_writer.last_pc() + pc_delta);

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  // Relocate runtime entries.
  for (RelocIterator it(desc); !it.done(); it.next()) {
    RelocInfo::Mode rmode = it.rinfo()->rmode();
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    if (rmode == RelocInfo::INTERNAL_REFERENCE_ENCODED ||
        rmode == RelocInfo::INTERNAL_REFERENCE) {
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      byte* p = reinterpret_cast<byte*>(it.rinfo()->pc());
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      RelocateInternalReference(rmode, p, pc_delta);
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    }
  }
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  DCHECK(!overflow());
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}


3010
void Assembler::db(uint8_t data) {
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  CheckForEmitInForbiddenSlot();
  EmitHelper(data);
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}


void Assembler::dd(uint32_t data) {
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  CheckForEmitInForbiddenSlot();
  EmitHelper(data);
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}


3022
void Assembler::dq(uint64_t data) {
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  CheckForEmitInForbiddenSlot();
  EmitHelper(data);
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}


3028
void Assembler::dd(Label* label) {
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  uint32_t data;
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  CheckForEmitInForbiddenSlot();
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  if (label->is_bound()) {
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    data = reinterpret_cast<uint32_t>(buffer_ + label->pos());
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  } else {
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    data = jump_address(label);
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    unbound_labels_count_++;
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    internal_reference_positions_.insert(label->pos());
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  }
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  RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE);
  EmitHelper(data);
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}


3043
void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
3044
  // We do not try to reuse pool constants.
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  RelocInfo rinfo(isolate(), pc_, rmode, data, NULL);
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  if (rmode >= RelocInfo::COMMENT &&
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      rmode <= RelocInfo::DEBUG_BREAK_SLOT_AT_TAIL_CALL) {
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    // Adjust code for new modes.
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    DCHECK(RelocInfo::IsDebugBreakSlot(rmode) || RelocInfo::IsComment(rmode));
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    // These modes do not need an entry in the constant pool.
  }
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  if (!RelocInfo::IsNone(rinfo.rmode())) {
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    // Don't record external references unless the heap will be serialized.
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    if (rmode == RelocInfo::EXTERNAL_REFERENCE &&
        !serializer_enabled() && !emit_debug_code()) {
      return;
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    }
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    DCHECK(buffer_space() >= kMaxRelocSize);  // Too late to grow buffer here.
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    if (rmode == RelocInfo::CODE_TARGET_WITH_ID) {
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      RelocInfo reloc_info_with_ast_id(isolate(), pc_, rmode,
                                       RecordedAstId().ToInt(), NULL);
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      ClearRecordedAstId();
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      reloc_info_writer.Write(&reloc_info_with_ast_id);
    } else {
      reloc_info_writer.Write(&rinfo);
    }
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  }
}


3071
void Assembler::BlockTrampolinePoolFor(int instructions) {
3072
  CheckTrampolinePoolQuick(instructions);
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  BlockTrampolinePoolBefore(pc_offset() + instructions * kInstrSize);
}


3077
void Assembler::CheckTrampolinePool() {
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  // Some small sequences of instructions must not be broken up by the
  // insertion of a trampoline pool; such sequences are protected by setting
  // either trampoline_pool_blocked_nesting_ or no_trampoline_pool_before_,
  // which are both checked here. Also, recursive calls to CheckTrampolinePool
  // are blocked by trampoline_pool_blocked_nesting_.
  if ((trampoline_pool_blocked_nesting_ > 0) ||
      (pc_offset() < no_trampoline_pool_before_)) {
    // Emission is currently blocked; make sure we try again as soon as
    // possible.
    if (trampoline_pool_blocked_nesting_ > 0) {
      next_buffer_check_ = pc_offset() + kInstrSize;
    } else {
      next_buffer_check_ = no_trampoline_pool_before_;
    }
    return;
  }

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  DCHECK(!trampoline_emitted_);
  DCHECK(unbound_labels_count_ >= 0);
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  if (unbound_labels_count_ > 0) {
    // First we emit jump (2 instructions), then we emit trampoline pool.
    { BlockTrampolinePoolScope block_trampoline_pool(this);
      Label after_pool;
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      if (IsMipsArchVariant(kMips32r6)) {
        bc(&after_pool);
      } else {
        b(&after_pool);
        nop();
      }
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      int pool_start = pc_offset();
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      if (IsMipsArchVariant(kMips32r6)) {
        for (int i = 0; i < unbound_labels_count_; i++) {
          uint32_t imm32;
          imm32 = jump_address(&after_pool);
          uint32_t lui_offset, jic_offset;
          UnpackTargetAddressUnsigned(imm32, lui_offset, jic_offset);
          {
            BlockGrowBufferScope block_buf_growth(this);
            // Buffer growth (and relocation) must be blocked for internal
            // references until associated instructions are emitted and
            // available to be patched.
            RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE_ENCODED);
            lui(at, lui_offset);
            jic(at, jic_offset);
          }
          CheckBuffer();
        }
      } else {
        for (int i = 0; i < unbound_labels_count_; i++) {
          uint32_t imm32;
          imm32 = jump_address(&after_pool);
          {
            BlockGrowBufferScope block_buf_growth(this);
            // Buffer growth (and relocation) must be blocked for internal
            // references until associated instructions are emitted and
            // available to be patched.
            RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE_ENCODED);
            lui(at, (imm32 & kHiMask) >> kLuiShift);
            ori(at, at, (imm32 & kImm16Mask));
          }
          CheckBuffer();
          jr(at);
          nop();
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        }
      }
      bind(&after_pool);
      trampoline_ = Trampoline(pool_start, unbound_labels_count_);

      trampoline_emitted_ = true;
      // As we are only going to emit trampoline once, we need to prevent any
      // further emission.
      next_buffer_check_ = kMaxInt;
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    }
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  } else {
    // Number of branches to unbound label at this point is zero, so we can
    // move next buffer check to maximum.
    next_buffer_check_ = pc_offset() +
        kMaxBranchOffset - kTrampolineSlotsSize * 16;
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  }
  return;
}


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Address Assembler::target_address_at(Address pc) {
  Instr instr1 = instr_at(pc);
  Instr instr2 = instr_at(pc + kInstrSize);
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  // Interpret 2 instructions generated by li: lui/ori
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  if (IsLui(instr1) && IsOri(instr2)) {
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    // Assemble the 32 bit value.
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    return reinterpret_cast<Address>((GetImmediate16(instr1) << kLuiShift) |
                                     GetImmediate16(instr2));
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  }

3172
  // We should never get here, force a bad address if we do.
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  UNREACHABLE();
  return (Address)0x0;
}


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// MIPS and ia32 use opposite encoding for qNaN and sNaN, such that ia32
// qNaN is a MIPS sNaN, and ia32 sNaN is MIPS qNaN. If running from a heap
// snapshot generated on ia32, the resulting MIPS sNaN must be quieted.
// OS::nan_value() returns a qNaN.
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void Assembler::QuietNaN(HeapObject* object) {
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  HeapNumber::cast(object)->set_value(std::numeric_limits<double>::quiet_NaN());
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}


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// On Mips, a target address is stored in a lui/ori instruction pair, each
// of which load 16 bits of the 32-bit address to a register.
// Patching the address must replace both instr, and flush the i-cache.
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// On r6, target address is stored in a lui/jic pair, and both instr have to be
// patched.
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//
// There is an optimization below, which emits a nop when the address
// fits in just 16 bits. This is unlikely to help, and should be benchmarked,
// and possibly removed.
3196
void Assembler::set_target_address_at(Isolate* isolate, Address pc,
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                                      Address target,
                                      ICacheFlushMode icache_flush_mode) {
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  Instr instr2 = instr_at(pc + kInstrSize);
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  uint32_t rt_code = GetRtField(instr2);
  uint32_t* p = reinterpret_cast<uint32_t*>(pc);
  uint32_t itarget = reinterpret_cast<uint32_t>(target);

3204
#ifdef DEBUG
3205
  // Check we have the result from a li macro-instruction, using instr pair.
3206
  Instr instr1 = instr_at(pc);
3207
  CHECK(IsLui(instr1) && (IsOri(instr2) || IsJicOrJialc(instr2)));
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#endif

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  if (IsJicOrJialc(instr2)) {
    // Must use 2 instructions to insure patchable code => use lui and jic
    uint32_t lui_offset, jic_offset;
    Assembler::UnpackTargetAddressUnsigned(itarget, lui_offset, jic_offset);
3214

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    *p &= ~kImm16Mask;
    *(p + 1) &= ~kImm16Mask;

    *p |= lui_offset;
    *(p + 1) |= jic_offset;

  } else {
    // Must use 2 instructions to insure patchable code => just use lui and ori.
    // lui rt, upper-16.
    // ori rt rt, lower-16.
    *p = LUI | rt_code | ((itarget & kHiMask) >> kLuiShift);
    *(p + 1) = ORI | rt_code | (rt_code << 5) | (itarget & kImm16Mask);
  }
3228

3229
  if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
3230
    Assembler::FlushICache(isolate, pc, 2 * sizeof(int32_t));
3231
  }
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}

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}  // namespace internal
}  // namespace v8
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#endif  // V8_TARGET_ARCH_MIPS