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Commit 9e05ee74 authored by Djordje.Pesic's avatar Djordje.Pesic Committed by Commit bot
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MIPS: Fix illegal use of at register 

Fix illegal use of at register when ldc1 and sdc1 are called. Added dchecks to prevent such a usage.

TEST=mjsunit/asm/float64array-negative-offset(r6), mjsunit/asm/float64array-outofbounds(r6)

Review URL: https://codereview.chromium.org/1323763002

Cr-Commit-Position: refs/heads/master@{#30670}
parent 99f01307
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Showing with 26 additions and 19 deletions
src/compiler/mips/code-generator-mips.cc
View file @ 9e05ee74
......@@ -304,8 +304,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
if (instr->InputAt(0)->IsRegister()) { \
auto offset = i.InputRegister(0); \
__ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \
__ addu(at, i.InputRegister(2), offset); \
__ asm_instr(result, MemOperand(at, 0)); \
__ addu(kScratchReg, i.InputRegister(2), offset); \
__ asm_instr(result, MemOperand(kScratchReg, 0)); \
} else { \
auto offset = i.InputOperand(0).immediate(); \
__ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset)); \
......@@ -322,8 +322,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
if (instr->InputAt(0)->IsRegister()) { \
auto offset = i.InputRegister(0); \
__ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \
__ addu(at, i.InputRegister(2), offset); \
__ asm_instr(result, MemOperand(at, 0)); \
__ addu(kScratchReg, i.InputRegister(2), offset); \
__ asm_instr(result, MemOperand(kScratchReg, 0)); \
} else { \
auto offset = i.InputOperand(0).immediate(); \
__ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset)); \
......@@ -340,8 +340,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
auto offset = i.InputRegister(0); \
auto value = i.Input##width##Register(2); \
__ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \
__ addu(at, i.InputRegister(3), offset); \
__ asm_instr(value, MemOperand(at, 0)); \
__ addu(kScratchReg, i.InputRegister(3), offset); \
__ asm_instr(value, MemOperand(kScratchReg, 0)); \
} else { \
auto offset = i.InputOperand(0).immediate(); \
auto value = i.Input##width##Register(2); \
......@@ -359,8 +359,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
auto offset = i.InputRegister(0); \
auto value = i.InputRegister(2); \
__ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \
__ addu(at, i.InputRegister(3), offset); \
__ asm_instr(value, MemOperand(at, 0)); \
__ addu(kScratchReg, i.InputRegister(3), offset); \
__ asm_instr(value, MemOperand(kScratchReg, 0)); \
} else { \
auto offset = i.InputOperand(0).immediate(); \
auto value = i.InputRegister(2); \
......
src/compiler/mips64/code-generator-mips64.cc
View file @ 9e05ee74
......@@ -305,8 +305,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
if (instr->InputAt(0)->IsRegister()) { \
auto offset = i.InputRegister(0); \
__ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \
__ Daddu(at, i.InputRegister(2), offset); \
__ asm_instr(result, MemOperand(at, 0)); \
__ Daddu(kScratchReg, i.InputRegister(2), offset); \
__ asm_instr(result, MemOperand(kScratchReg, 0)); \
} else { \
int offset = static_cast<int>(i.InputOperand(0).immediate()); \
__ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset)); \
......@@ -323,8 +323,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
if (instr->InputAt(0)->IsRegister()) { \
auto offset = i.InputRegister(0); \
__ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \
__ Daddu(at, i.InputRegister(2), offset); \
__ asm_instr(result, MemOperand(at, 0)); \
__ Daddu(kScratchReg, i.InputRegister(2), offset); \
__ asm_instr(result, MemOperand(kScratchReg, 0)); \
} else { \
int offset = static_cast<int>(i.InputOperand(0).immediate()); \
__ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset)); \
......@@ -341,8 +341,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
auto offset = i.InputRegister(0); \
auto value = i.Input##width##Register(2); \
__ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \
__ Daddu(at, i.InputRegister(3), offset); \
__ asm_instr(value, MemOperand(at, 0)); \
__ Daddu(kScratchReg, i.InputRegister(3), offset); \
__ asm_instr(value, MemOperand(kScratchReg, 0)); \
} else { \
int offset = static_cast<int>(i.InputOperand(0).immediate()); \
auto value = i.Input##width##Register(2); \
......@@ -360,8 +360,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
auto offset = i.InputRegister(0); \
auto value = i.InputRegister(2); \
__ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \
__ Daddu(at, i.InputRegister(3), offset); \
__ asm_instr(value, MemOperand(at, 0)); \
__ Daddu(kScratchReg, i.InputRegister(3), offset); \
__ asm_instr(value, MemOperand(kScratchReg, 0)); \
} else { \
int offset = static_cast<int>(i.InputOperand(0).immediate()); \
auto value = i.InputRegister(2); \
......
src/mips/assembler-mips.cc
View file @ 9e05ee74
......@@ -2026,6 +2026,7 @@ void Assembler::lwc1(FPURegister fd, const MemOperand& src) {
void Assembler::ldc1(FPURegister fd, const MemOperand& src) {
// Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
// load to two 32-bit loads.
DCHECK(!src.rm().is(at));
if (IsFp64Mode()) {
if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
GenInstrImmediate(LWC1, src.rm(), fd,
......@@ -2071,6 +2072,8 @@ void Assembler::swc1(FPURegister fd, const MemOperand& src) {
void Assembler::sdc1(FPURegister fd, const MemOperand& src) {
// Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
// store to two 32-bit stores.
DCHECK(!src.rm().is(at));
DCHECK(!src.rm().is(t8));
if (IsFp64Mode()) {
if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
GenInstrImmediate(SWC1, src.rm(), fd,
......
src/mips/lithium-codegen-mips.cc
View file @ 9e05ee74
......@@ -4188,6 +4188,7 @@ void LCodeGen::DoStoreKeyedFixedDoubleArray(LStoreKeyed* instr) {
DoubleRegister value = ToDoubleRegister(instr->value());
Register elements = ToRegister(instr->elements());
Register scratch = scratch0();
Register scratch_1 = scratch1();
DoubleRegister double_scratch = double_scratch0();
bool key_is_constant = instr->key()->IsConstantOperand();
int base_offset = instr->base_offset();
......@@ -4219,8 +4220,9 @@ void LCodeGen::DoStoreKeyedFixedDoubleArray(LStoreKeyed* instr) {
// Only load canonical NaN if the comparison above set the overflow.
__ bind(&is_nan);
__ LoadRoot(at, Heap::kNanValueRootIndex);
__ ldc1(double_scratch, FieldMemOperand(at, HeapNumber::kValueOffset));
__ LoadRoot(scratch_1, Heap::kNanValueRootIndex);
__ ldc1(double_scratch,
FieldMemOperand(scratch_1, HeapNumber::kValueOffset));
__ sdc1(double_scratch, MemOperand(scratch, 0));
__ Branch(&done);
}
......
src/mips/macro-assembler-mips.cc
View file @ 9e05ee74
......@@ -4948,7 +4948,7 @@ void MacroAssembler::LeaveExitFrame(bool save_doubles, Register argument_count,
lw(t8, MemOperand(fp, ExitFrameConstants::kSPOffset));
for (int i = 0; i < FPURegister::kMaxNumRegisters; i+=2) {
FPURegister reg = FPURegister::from_code(i);
ldc1(reg, MemOperand(t8, i * kDoubleSize + kPointerSize));
ldc1(reg, MemOperand(t8, i * kDoubleSize + kPointerSize));
}
}
......
src/mips64/assembler-mips64.cc
View file @ 9e05ee74
......@@ -2378,6 +2378,7 @@ void Assembler::lwc1(FPURegister fd, const MemOperand& src) {
void Assembler::ldc1(FPURegister fd, const MemOperand& src) {
DCHECK(!src.rm().is(at));
if (is_int16(src.offset_)) {
GenInstrImmediate(LDC1, src.rm(), fd, src.offset_);
} else { // Offset > 16 bits, use multiple instructions to load.
......@@ -2398,6 +2399,7 @@ void Assembler::swc1(FPURegister fd, const MemOperand& src) {
void Assembler::sdc1(FPURegister fd, const MemOperand& src) {
DCHECK(!src.rm().is(at));
if (is_int16(src.offset_)) {
GenInstrImmediate(SDC1, src.rm(), fd, src.offset_);
} else { // Offset > 16 bits, use multiple instructions to load.
......
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