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Commit 40172e6a authored by sgjesse@chromium.org's avatar sgjesse@chromium.org
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Update mips infrastructure files. 

- Merge to current tip of tree, fix build problems.
- Remove deprecated source files.
- Add cctest test-disasm-mips
- Consistently use single-reg push()/pop() (remove uppercase variants)
- Add assembler field accessors.
- More style fixes.

BUG=
TEST=

Review URL: http://codereview.chromium.org//6965006

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7825 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
parent 07ed2f12
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src/mips/assembler-mips-inl.h
View file @ 40172e6a
......@@ -30,7 +30,7 @@
// The original source code covered by the above license above has been
// modified significantly by Google Inc.
// Copyright 2010 the V8 project authors. All rights reserved.
// Copyright 2011 the V8 project authors. All rights reserved.
#ifndef V8_MIPS_ASSEMBLER_MIPS_INL_H_
......@@ -45,7 +45,7 @@ namespace v8 {
namespace internal {
// -----------------------------------------------------------------------------
// Operand and MemOperand
// Operand and MemOperand.
Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) {
rm_ = no_reg;
......@@ -80,7 +80,7 @@ bool Operand::is_reg() const {
// -----------------------------------------------------------------------------
// RelocInfo
// RelocInfo.
void RelocInfo::apply(intptr_t delta) {
// On MIPS we do not use pc relative addressing, so we don't need to patch the
......@@ -254,23 +254,25 @@ void RelocInfo::Visit(ObjectVisitor* visitor) {
// RelocInfo is needed when pointer must be updated/serialized, such as
// UpdatingVisitor in mark-compact.cc or Serializer in serialize.cc.
// It is ignored by visitors that do not need it.
// Commenting out, to simplify arch-independednt changes.
// TODO(mips): Commenting out, to simplify arch-independent changes.
// GC won't work like this, but this commit is for asm/disasm/sim.
// visitor->VisitPointer(target_object_address(), this);
} else if (RelocInfo::IsCodeTarget(mode)) {
visitor->VisitCodeTarget(this);
} else if (mode == RelocInfo::GLOBAL_PROPERTY_CELL) {
visitor->VisitGlobalPropertyCell(this);
} else if (mode == RelocInfo::EXTERNAL_REFERENCE) {
// RelocInfo is needed when external-references must be serialized by
// Serializer Visitor in serialize.cc. It is ignored by visitors that
// do not need it.
// Commenting out, to simplify arch-independednt changes.
// TODO(mips): Commenting out, to simplify arch-independent changes.
// Serializer won't work like this, but this commit is for asm/disasm/sim.
// visitor->VisitExternalReference(target_reference_address(), this);
#ifdef ENABLE_DEBUGGER_SUPPORT
// TODO(isolates): Get a cached isolate below.
} else if (((RelocInfo::IsJSReturn(mode) &&
IsPatchedReturnSequence()) ||
(RelocInfo::IsDebugBreakSlot(mode) &&
(RelocInfo::IsDebugBreakSlot(mode) &&
IsPatchedDebugBreakSlotSequence())) &&
Isolate::Current()->debug()->has_break_points()) {
visitor->VisitDebugTarget(this);
......@@ -287,7 +289,9 @@ void RelocInfo::Visit(Heap* heap) {
if (mode == RelocInfo::EMBEDDED_OBJECT) {
StaticVisitor::VisitPointer(heap, target_object_address());
} else if (RelocInfo::IsCodeTarget(mode)) {
StaticVisitor::VisitCodeTarget(this);
StaticVisitor::VisitCodeTarget(heap, this);
} else if (mode == RelocInfo::GLOBAL_PROPERTY_CELL) {
StaticVisitor::VisitGlobalPropertyCell(heap, this);
} else if (mode == RelocInfo::EXTERNAL_REFERENCE) {
StaticVisitor::VisitExternalReference(target_reference_address());
#ifdef ENABLE_DEBUGGER_SUPPORT
......@@ -296,7 +300,7 @@ void RelocInfo::Visit(Heap* heap) {
IsPatchedReturnSequence()) ||
(RelocInfo::IsDebugBreakSlot(mode) &&
IsPatchedDebugBreakSlotSequence()))) {
StaticVisitor::VisitDebugTarget(this);
StaticVisitor::VisitDebugTarget(heap, this);
#endif
} else if (mode == RelocInfo::RUNTIME_ENTRY) {
StaticVisitor::VisitRuntimeEntry(this);
......@@ -305,7 +309,7 @@ void RelocInfo::Visit(Heap* heap) {
// -----------------------------------------------------------------------------
// Assembler
// Assembler.
void Assembler::CheckBuffer() {
......
src/mips/assembler-mips.cc
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src/mips/assembler-mips.h
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src/mips/builtins-mips.cc
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// Copyright 2010 the V8 project authors. All rights reserved.
// Copyright 2011 the V8 project authors. All rights reserved.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
......@@ -31,7 +31,7 @@
#if defined(V8_TARGET_ARCH_MIPS)
#include "codegen-inl.h"
#include "codegen.h"
#include "debug.h"
#include "deoptimizer.h"
#include "full-codegen.h"
......
src/mips/code-stubs-mips.cc
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src/mips/code-stubs-mips.h
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src/mips/codegen-mips-inl.h deleted 100644 → 0
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// Copyright 2010 the V8 project authors. All rights reserved.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
// * Neither the name of Google Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#ifndef V8_MIPS_CODEGEN_MIPS_INL_H_
#define V8_MIPS_CODEGEN_MIPS_INL_H_
#include "virtual-frame-mips.h"
namespace v8 {
namespace internal {
#define __ ACCESS_MASM(masm_)
// Platform-specific inline functions.
void DeferredCode::Jump() {
__ b(&entry_label_);
__ nop();
}
// Note: this has been hacked for submisson. Mips branches require two
// additional operands: Register src1, const Operand& src2.
void DeferredCode::Branch(Condition cond) {
__ Branch(&entry_label_, cond, zero_reg, Operand(0));
}
void Reference::GetValueAndSpill() {
GetValue();
}
#undef __
} } // namespace v8::internal
#endif // V8_MIPS_CODEGEN_MIPS_INL_H_
src/mips/codegen-mips.cc
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src/mips/codegen-mips.h
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src/mips/constants-mips.cc
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// Copyright 2010 the V8 project authors. All rights reserved.
// Copyright 2011 the V8 project authors. All rights reserved.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
......@@ -36,7 +36,7 @@ namespace internal {
// -----------------------------------------------------------------------------
// Registers
// Registers.
// These register names are defined in a way to match the native disassembler
......@@ -145,7 +145,7 @@ int FPURegisters::Number(const char* name) {
// -----------------------------------------------------------------------------
// Instruction
// Instructions.
bool Instruction::IsForbiddenInBranchDelay() const {
const int op = OpcodeFieldRaw();
......@@ -293,15 +293,15 @@ Instruction::Type Instruction::InstructionType() const {
UNREACHABLE();
};
break;
case COP1: // Coprocessor instructions
case COP1: // Coprocessor instructions.
switch (RsFieldRawNoAssert()) {
case BC1: // branch on coprocessor condition
case BC1: // Branch on coprocessor condition.
return kImmediateType;
default:
return kRegisterType;
};
break;
// 16 bits Immediate type instructions. eg: addi dest, src, imm16
// 16 bits Immediate type instructions. eg: addi dest, src, imm16.
case REGIMM:
case BEQ:
case BNE:
......@@ -336,7 +336,7 @@ Instruction::Type Instruction::InstructionType() const {
case SWC1:
case SDC1:
return kImmediateType;
// 26 bits immediate type instructions. eg: j imm26
// 26 bits immediate type instructions. eg: j imm26.
case J:
case JAL:
return kJumpType;
......
src/mips/constants-mips.h
View file @ 40172e6a
......@@ -58,7 +58,7 @@ namespace v8 {
namespace internal {
// -----------------------------------------------------------------------------
// Registers and FPURegister.
// Registers and FPURegisters.
// Number of general purpose registers.
static const int kNumRegisters = 32;
......@@ -82,6 +82,11 @@ static const uint32_t kFPUInvalidResult = (uint32_t) (1 << 31) - 1;
// FCSR constants.
static const uint32_t kFCSRFlagMask = (1 << 6) - 1;
static const uint32_t kFCSRFlagShift = 2;
static const uint32_t kFCSRInexactFlagBit = 1 << 0;
static const uint32_t kFCSRUnderflowFlagBit = 1 << 1;
static const uint32_t kFCSROverflowFlagBit = 1 << 2;
static const uint32_t kFCSRDivideByZeroFlagBit = 1 << 3;
static const uint32_t kFCSRInvalidOpFlagBit = 1 << 4;
// Helper functions for converting between register numbers and names.
class Registers {
......@@ -133,8 +138,6 @@ class FPURegisters {
// On MIPS all instructions are 32 bits.
typedef int32_t Instr;
typedef unsigned char byte_;
// Special Software Interrupt codes when used in the presence of the MIPS
// simulator.
enum SoftwareInterruptCodes {
......@@ -175,7 +178,7 @@ static const int kFBccBits = 3;
static const int kFBtrueShift = 16;
static const int kFBtrueBits = 1;
// ----- Miscellianous useful masks.
// ----- Miscellaneous useful masks.
// Instruction bit masks.
static const int kOpcodeMask = ((1 << kOpcodeBits) - 1) << kOpcodeShift;
static const int kImm16Mask = ((1 << kImm16Bits) - 1) << kImm16Shift;
......@@ -215,7 +218,7 @@ enum Opcode {
XORI = ((1 << 3) + 6) << kOpcodeShift,
LUI = ((1 << 3) + 7) << kOpcodeShift,
COP1 = ((2 << 3) + 1) << kOpcodeShift, // Coprocessor 1 class
COP1 = ((2 << 3) + 1) << kOpcodeShift, // Coprocessor 1 class.
BEQL = ((2 << 3) + 4) << kOpcodeShift,
BNEL = ((2 << 3) + 5) << kOpcodeShift,
BLEZL = ((2 << 3) + 6) << kOpcodeShift,
......@@ -393,7 +396,7 @@ enum Condition {
cc_always = 16,
// aliases
// Aliases.
carry = Uless,
not_carry = Ugreater_equal,
zero = equal,
......@@ -455,14 +458,14 @@ inline Condition ReverseCondition(Condition cc) {
// ----- Coprocessor conditions.
enum FPUCondition {
F, // False
UN, // Unordered
EQ, // Equal
UEQ, // Unordered or Equal
OLT, // Ordered or Less Than
ULT, // Unordered or Less Than
OLE, // Ordered or Less Than or Equal
ULE // Unordered or Less Than or Equal
F, // False.
UN, // Unordered.
EQ, // Equal.
UEQ, // Unordered or Equal.
OLT, // Ordered or Less Than.
ULT, // Unordered or Less Than.
OLE, // Ordered or Less Than or Equal.
ULE // Unordered or Less Than or Equal.
};
......@@ -494,7 +497,7 @@ extern const Instr kPopInstruction;
extern const Instr kPushInstruction;
// sw(r, MemOperand(sp, 0))
extern const Instr kPushRegPattern;
// lw(r, MemOperand(sp, 0))
// lw(r, MemOperand(sp, 0))
extern const Instr kPopRegPattern;
extern const Instr kLwRegFpOffsetPattern;
extern const Instr kSwRegFpOffsetPattern;
......@@ -687,7 +690,7 @@ class Instruction {
// reference to an instruction is to convert a pointer. There is no way
// to allocate or create instances of class Instruction.
// Use the At(pc) function to create references to Instruction.
static Instruction* At(byte_* pc) {
static Instruction* At(byte* pc) {
return reinterpret_cast<Instruction*>(pc);
}
......
src/mips/cpu-mips.cc
View file @ 40172e6a
// Copyright 2010 the V8 project authors. All rights reserved.
// Copyright 2011 the V8 project authors. All rights reserved.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
......@@ -48,19 +48,25 @@ namespace internal {
void CPU::Setup() {
CpuFeatures* cpu_features = Isolate::Current()->cpu_features();
cpu_features->Probe(true);
if (!cpu_features->IsSupported(FPU) || Serializer::enabled()) {
V8::DisableCrankshaft();
}
CpuFeatures::Probe();
}
bool CPU::SupportsCrankshaft() {
return CpuFeatures::IsSupported(FPU);
}
void CPU::FlushICache(void* start, size_t size) {
// Nothing to do, flushing no instructions.
if (size == 0) {
return;
}
#if !defined (USE_SIMULATOR)
int res;
// See http://www.linux-mips.org/wiki/Cacheflush_Syscall
// See http://www.linux-mips.org/wiki/Cacheflush_Syscall.
res = syscall(__NR_cacheflush, start, size, ICACHE);
if (res) {
......
src/mips/debug-mips.cc
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......@@ -31,7 +31,7 @@
#if defined(V8_TARGET_ARCH_MIPS)
#include "codegen-inl.h"
#include "codegen.h"
#include "debug.h"
namespace v8 {
......
src/mips/disasm-mips.cc
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src/mips/frames-mips.cc
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......@@ -38,8 +38,12 @@ namespace internal {
Address ExitFrame::ComputeStackPointer(Address fp) {
UNIMPLEMENTED_MIPS();
return fp;
Address marker = Memory::Address_at(fp + ExitFrameConstants::kMarkerOffset);
Address sp = fp + ExitFrameConstants::kSPOffset;
if (marker == NULL) {
sp -= FPURegister::kNumRegisters * kDoubleSize + 2 * kPointerSize;
}
return sp;
}
......
src/mips/frames-mips.h
View file @ 40172e6a
......@@ -59,7 +59,7 @@ static const RegList kCalleeSaved =
// Saved temporaries.
1 << 16 | 1 << 17 | 1 << 18 | 1 << 19 |
1 << 20 | 1 << 21 | 1 << 22 | 1 << 23 |
// gp, sp, fp
// gp, sp, fp.
1 << 28 | 1 << 29 | 1 << 30;
static const int kNumCalleeSaved = 11;
......@@ -135,7 +135,8 @@ class StandardFrameConstants : public AllStatic {
static const int kRegularArgsSlotsSize = kRArgsSlotsSize;
// C/C++ argument slots size.
static const int kCArgsSlotsSize = 4 * kPointerSize;
static const int kCArgSlotCount = 4;
static const int kCArgsSlotsSize = kCArgSlotCount * kPointerSize;
// JS argument slots size.
static const int kJSArgsSlotsSize = 0 * kPointerSize;
// Assembly builtins argument slots size.
......
src/mips/full-codegen-mips.cc
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......@@ -38,7 +38,7 @@
// next call: mov(a0, v0). This is not needed on the other architectures.
#include "code-stubs.h"
#include "codegen-inl.h"
#include "codegen.h"
#include "compiler.h"
#include "debug.h"
#include "full-codegen.h"
......@@ -368,7 +368,7 @@ void FullCodeGenerator::EmitKeyedPropertyLoad(Property* prop) {
}
void FullCodeGenerator::EmitInlineSmiBinaryOp(Expression* expr,
void FullCodeGenerator::EmitInlineSmiBinaryOp(BinaryOperation* expr,
Token::Value op,
OverwriteMode mode,
Expression* left,
......@@ -377,7 +377,8 @@ void FullCodeGenerator::EmitInlineSmiBinaryOp(Expression* expr,
}
void FullCodeGenerator::EmitBinaryOp(Token::Value op,
void FullCodeGenerator::EmitBinaryOp(BinaryOperation* expr,
Token::Value op,
OverwriteMode mode) {
UNIMPLEMENTED_MIPS();
}
......@@ -423,7 +424,7 @@ void FullCodeGenerator::EmitKeyedCallWithIC(Call* expr,
}
void FullCodeGenerator::EmitCallWithStub(Call* expr) {
void FullCodeGenerator::EmitCallWithStub(Call* expr, CallFunctionFlags flags) {
UNIMPLEMENTED_MIPS();
}
......@@ -692,7 +693,9 @@ Register FullCodeGenerator::context_register() {
}
void FullCodeGenerator::EmitCallIC(Handle<Code> ic, RelocInfo::Mode mode) {
void FullCodeGenerator::EmitCallIC(Handle<Code> ic,
RelocInfo::Mode mode,
unsigned ast_id) {
UNIMPLEMENTED_MIPS();
}
......
src/mips/ic-mips.cc
View file @ 40172e6a
// Copyright 2010 the V8 project authors. All rights reserved.
// Copyright 2011 the V8 project authors. All rights reserved.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
......@@ -31,7 +31,7 @@
#if defined(V8_TARGET_ARCH_MIPS)
#include "codegen-inl.h"
#include "codegen.h"
#include "code-stubs.h"
#include "ic-inl.h"
#include "runtime.h"
......@@ -115,39 +115,6 @@ void LoadIC::GenerateMiss(MacroAssembler* masm) {
}
bool LoadIC::PatchInlinedLoad(Address address, Object* map, int offset) {
UNIMPLEMENTED_MIPS();
return false;
}
bool LoadIC::PatchInlinedContextualLoad(Address address,
Object* map,
Object* cell,
bool is_dont_delete) {
UNIMPLEMENTED_MIPS();
return false;
}
bool StoreIC::PatchInlinedStore(Address address, Object* map, int offset) {
UNIMPLEMENTED_MIPS();
return false;
}
bool KeyedLoadIC::PatchInlinedLoad(Address address, Object* map) {
UNIMPLEMENTED_MIPS();
return false;
}
bool KeyedStoreIC::PatchInlinedStore(Address address, Object* map) {
UNIMPLEMENTED_MIPS();
return false;
}
Object* KeyedLoadIC_Miss(Arguments args);
......
src/mips/jump-target-mips.cc deleted 100644 → 0
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// Copyright 2010 the V8 project authors. All rights reserved.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
// * Neither the name of Google Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#include "v8.h"
#if defined(V8_TARGET_ARCH_MIPS)
#include "codegen-inl.h"
#include "jump-target-inl.h"
#include "register-allocator-inl.h"
#include "virtual-frame-inl.h"
namespace v8 {
namespace internal {
// -------------------------------------------------------------------------
// JumpTarget implementation.
#define __ ACCESS_MASM(cgen()->masm())
// BRANCH_ARGS_CHECK checks that conditional jump arguments are correct.
#define BRANCH_ARGS_CHECK(cond, rs, rt) ASSERT( \
(cond == cc_always && rs.is(zero_reg) && rt.rm().is(zero_reg)) || \
(cond != cc_always && (!rs.is(zero_reg) || !rt.rm().is(zero_reg))))
void JumpTarget::DoJump() {
UNIMPLEMENTED_MIPS();
}
// Original prototype for mips, needs arch-indep change. Leave out for now.
// void JumpTarget::DoBranch(Condition cc, Hint ignored,
// Register src1, const Operand& src2) {
void JumpTarget::DoBranch(Condition cc, Hint ignored) {
UNIMPLEMENTED_MIPS();
}
void JumpTarget::Call() {
UNIMPLEMENTED_MIPS();
}
void JumpTarget::DoBind() {
UNIMPLEMENTED_MIPS();
}
#undef __
#undef BRANCH_ARGS_CHECK
} } // namespace v8::internal
#endif // V8_TARGET_ARCH_MIPS
src/mips/lithium-codegen-mips.h
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// Copyright 2010 the V8 project authors. All rights reserved.
// Copyright 2011 the V8 project authors. All rights reserved.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
......
src/mips/lithium-mips.h
View file @ 40172e6a
......@@ -78,7 +78,7 @@ class LInstruction: public ZoneObject {
bool HasEnvironment() const {
UNIMPLEMENTED();
return NULL;
return false;
}
virtual void PrintTo(StringStream* stream) const { UNIMPLEMENTED(); }
......@@ -213,15 +213,13 @@ class LOsrEntry: public LInstruction {
class LChunk: public ZoneObject {
public:
explicit LChunk(CompilationInfo* info, HGraph* graph) { }
explicit LChunk(HGraph* graph) { }
HGraph* graph() const {
UNIMPLEMENTED();
return NULL;
}
CompilationInfo* info() const { return NULL; }
const ZoneList<LPointerMap*>* pointer_maps() const {
UNIMPLEMENTED();
return NULL;
......@@ -271,6 +269,11 @@ class LChunk: public ZoneObject {
void MarkEmptyBlocks() { UNIMPLEMENTED(); }
CompilationInfo* info() const {
UNIMPLEMENTED();
return NULL;
}
#ifdef DEBUG
void Verify() { UNIMPLEMENTED(); }
#endif
......@@ -279,7 +282,7 @@ class LChunk: public ZoneObject {
class LChunkBuilder BASE_EMBEDDED {
public:
LChunkBuilder(CompilationInfo* info, HGraph* graph, LAllocator* allocator) { }
LChunkBuilder(CompilationInfo*&, HGraph* graph, LAllocator* allocator) { }
// Build the sequence for the graph.
LChunk* Build() {
......
src/mips/macro-assembler-mips.cc
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src/mips/macro-assembler-mips.h
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src/mips/regexp-macro-assembler-mips.cc
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......@@ -106,7 +106,7 @@ namespace internal {
RegExpMacroAssemblerMIPS::RegExpMacroAssemblerMIPS(
Mode mode,
int registers_to_save)
: masm_(new MacroAssembler(NULL, kRegExpCodeSize)),
: masm_(new MacroAssembler(Isolate::Current(), NULL, kRegExpCodeSize)),
mode_(mode),
num_registers_(registers_to_save),
num_saved_registers_(registers_to_save),
......
src/mips/register-allocator-mips-inl.h deleted 100644 → 0
View file @ 07ed2f12
// Copyright 2010 the V8 project authors. All rights reserved.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
// * Neither the name of Google Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#ifndef V8_IA32_REGISTER_ALLOCATOR_MIPS_INL_H_
#define V8_IA32_REGISTER_ALLOCATOR_MIPS_INL_H_
#include "v8.h"
#include "mips/assembler-mips.h"
namespace v8 {
namespace internal {
// -------------------------------------------------------------------------
// RegisterAllocator implementation.
bool RegisterAllocator::IsReserved(Register reg) {
// The code for this test relies on the order of register codes.
return reg.is(cp) || reg.is(s8_fp) || reg.is(sp);
}
int RegisterAllocator::ToNumber(Register reg) {
ASSERT(reg.is_valid() && !IsReserved(reg));
const int kNumbers[] = {
0, // zero_reg
1, // at
2, // v0
3, // v1
4, // a0
5, // a1
6, // a2
7, // a3
8, // t0
9, // t1
10, // t2
11, // t3
12, // t4
13, // t5
14, // t
15, // t7
16, // t8
17, // t9
18, // s0
19, // s1
20, // s2
21, // s3
22, // s4
23, // s5
24, // s6
25, // s7
26, // k0
27, // k1
28, // gp
29, // sp
30, // s8_fp
31, // ra
};
return kNumbers[reg.code()];
}
Register RegisterAllocator::ToRegister(int num) {
ASSERT(num >= 0 && num < kNumRegisters);
const Register kRegisters[] = {
zero_reg,
at,
v0,
v1,
a0,
a1,
a2,
a3,
t0,
t1,
t2,
t3,
t4,
t5,
t6,
t7,
s0,
s1,
s2,
s3,
s4,
s5,
s6,
s7,
t8,
t9,
k0,
k1,
gp,
sp,
s8_fp,
ra
};
return kRegisters[num];
}
void RegisterAllocator::Initialize() {
Reset();
}
} } // namespace v8::internal
#endif // V8_IA32_REGISTER_ALLOCATOR_MIPS_INL_H_
src/mips/register-allocator-mips.cc deleted 100644 → 0
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// Copyright 2010 the V8 project authors. All rights reserved.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
// * Neither the name of Google Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#include "v8.h"
#if defined(V8_TARGET_ARCH_MIPS)
#include "codegen-inl.h"
#include "register-allocator-inl.h"
namespace v8 {
namespace internal {
// -------------------------------------------------------------------------
// Result implementation.
void Result::ToRegister() {
UNIMPLEMENTED_MIPS();
}
void Result::ToRegister(Register target) {
UNIMPLEMENTED_MIPS();
}
// -------------------------------------------------------------------------
// RegisterAllocator implementation.
Result RegisterAllocator::AllocateByteRegisterWithoutSpilling() {
// No byte registers on MIPS.
UNREACHABLE();
return Result();
}
} } // namespace v8::internal
#endif // V8_TARGET_ARCH_MIPS
src/mips/register-allocator-mips.h deleted 100644 → 0
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// Copyright 2010 the V8 project authors. All rights reserved.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
// * Neither the name of Google Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#ifndef V8_MIPS_REGISTER_ALLOCATOR_MIPS_H_
#define V8_MIPS_REGISTER_ALLOCATOR_MIPS_H_
#include "mips/constants-mips.h"
namespace v8 {
namespace internal {
class RegisterAllocatorConstants : public AllStatic {
public:
// No registers are currently managed by the register allocator on MIPS.
static const int kNumRegisters = 0;
static const int kInvalidRegister = -1;
};
} } // namespace v8::internal
#endif // V8_MIPS_REGISTER_ALLOCATOR_MIPS_H_
src/mips/simulator-mips.cc
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src/mips/simulator-mips.h
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src/mips/stub-cache-mips.cc
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......@@ -30,7 +30,7 @@
#if defined(V8_TARGET_ARCH_MIPS)
#include "ic-inl.h"
#include "codegen-inl.h"
#include "codegen.h"
#include "stub-cache.h"
namespace v8 {
......
src/mips/virtual-frame-mips-inl.h deleted 100644 → 0
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src/mips/virtual-frame-mips.cc deleted 100644 → 0
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src/mips/virtual-frame-mips.h deleted 100644 → 0
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test/cctest/SConscript
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......@@ -97,7 +97,8 @@ SOURCES = {
'arch:x64': ['test-assembler-x64.cc',
'test-macro-assembler-x64.cc',
'test-log-stack-tracer.cc'],
'arch:mips': ['test-assembler-mips.cc'],
'arch:mips': ['test-assembler-mips.cc',
'test-disasm-mips.cc'],
'os:linux': ['test-platform-linux.cc'],
'os:macos': ['test-platform-macos.cc'],
'os:nullos': ['test-platform-nullos.cc'],
......
test/cctest/cctest.gyp
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test/cctest/cctest.status
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......@@ -92,6 +92,7 @@ test-deoptimization: SKIP
test-func-name-inference: SKIP
test-heap: SKIP
test-heap-profiler: SKIP
test-lockers: SKIP
test-log: SKIP
test-log-utils: SKIP
test-mark-compact: SKIP
......
test/cctest/test-assembler-mips.cc
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