disasm-x64.cc 94.3 KB
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// Copyright 2011 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
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#include <assert.h>
#include <stdarg.h>
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#include <stdio.h>
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#if V8_TARGET_ARCH_X64
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#include "src/base/compiler-specific.h"
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#include "src/base/lazy-instance.h"
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#include "src/base/v8-fallthrough.h"
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#include "src/disasm.h"
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#include "src/x64/register-x64.h"
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#include "src/x64/sse-instr.h"
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namespace disasm {

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enum OperandType {
  UNSET_OP_ORDER = 0,
  // Operand size decides between 16, 32 and 64 bit operands.
  REG_OPER_OP_ORDER = 1,  // Register destination, operand source.
  OPER_REG_OP_ORDER = 2,  // Operand destination, register source.
  // Fixed 8-bit operands.
  BYTE_SIZE_OPERAND_FLAG = 4,
  BYTE_REG_OPER_OP_ORDER = REG_OPER_OP_ORDER | BYTE_SIZE_OPERAND_FLAG,
  BYTE_OPER_REG_OP_ORDER = OPER_REG_OP_ORDER | BYTE_SIZE_OPERAND_FLAG
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};

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//------------------------------------------------------------------
// Tables
//------------------------------------------------------------------
struct ByteMnemonic {
  int b;  // -1 terminates, otherwise must be in range (0..255)
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  OperandType op_order_;
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  const char* mnem;
};


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static const ByteMnemonic two_operands_instr[] = {
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  { 0x00, BYTE_OPER_REG_OP_ORDER, "add" },
  { 0x01, OPER_REG_OP_ORDER,      "add" },
  { 0x02, BYTE_REG_OPER_OP_ORDER, "add" },
  { 0x03, REG_OPER_OP_ORDER,      "add" },
  { 0x08, BYTE_OPER_REG_OP_ORDER, "or" },
  { 0x09, OPER_REG_OP_ORDER,      "or" },
  { 0x0A, BYTE_REG_OPER_OP_ORDER, "or" },
  { 0x0B, REG_OPER_OP_ORDER,      "or" },
  { 0x10, BYTE_OPER_REG_OP_ORDER, "adc" },
  { 0x11, OPER_REG_OP_ORDER,      "adc" },
  { 0x12, BYTE_REG_OPER_OP_ORDER, "adc" },
  { 0x13, REG_OPER_OP_ORDER,      "adc" },
  { 0x18, BYTE_OPER_REG_OP_ORDER, "sbb" },
  { 0x19, OPER_REG_OP_ORDER,      "sbb" },
  { 0x1A, BYTE_REG_OPER_OP_ORDER, "sbb" },
  { 0x1B, REG_OPER_OP_ORDER,      "sbb" },
  { 0x20, BYTE_OPER_REG_OP_ORDER, "and" },
  { 0x21, OPER_REG_OP_ORDER,      "and" },
  { 0x22, BYTE_REG_OPER_OP_ORDER, "and" },
  { 0x23, REG_OPER_OP_ORDER,      "and" },
  { 0x28, BYTE_OPER_REG_OP_ORDER, "sub" },
  { 0x29, OPER_REG_OP_ORDER,      "sub" },
  { 0x2A, BYTE_REG_OPER_OP_ORDER, "sub" },
  { 0x2B, REG_OPER_OP_ORDER,      "sub" },
  { 0x30, BYTE_OPER_REG_OP_ORDER, "xor" },
  { 0x31, OPER_REG_OP_ORDER,      "xor" },
  { 0x32, BYTE_REG_OPER_OP_ORDER, "xor" },
  { 0x33, REG_OPER_OP_ORDER,      "xor" },
  { 0x38, BYTE_OPER_REG_OP_ORDER, "cmp" },
  { 0x39, OPER_REG_OP_ORDER,      "cmp" },
  { 0x3A, BYTE_REG_OPER_OP_ORDER, "cmp" },
  { 0x3B, REG_OPER_OP_ORDER,      "cmp" },
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  { 0x63, REG_OPER_OP_ORDER,      "movsxl" },
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  { 0x84, BYTE_REG_OPER_OP_ORDER, "test" },
  { 0x85, REG_OPER_OP_ORDER,      "test" },
  { 0x86, BYTE_REG_OPER_OP_ORDER, "xchg" },
  { 0x87, REG_OPER_OP_ORDER,      "xchg" },
  { 0x88, BYTE_OPER_REG_OP_ORDER, "mov" },
  { 0x89, OPER_REG_OP_ORDER,      "mov" },
  { 0x8A, BYTE_REG_OPER_OP_ORDER, "mov" },
  { 0x8B, REG_OPER_OP_ORDER,      "mov" },
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  { 0x8D, REG_OPER_OP_ORDER,      "lea" },
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  { -1, UNSET_OP_ORDER, "" }
};


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static const ByteMnemonic zero_operands_instr[] = {
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  { 0xC3, UNSET_OP_ORDER, "ret" },
  { 0xC9, UNSET_OP_ORDER, "leave" },
  { 0xF4, UNSET_OP_ORDER, "hlt" },
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  { 0xFC, UNSET_OP_ORDER, "cld" },
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  { 0xCC, UNSET_OP_ORDER, "int3" },
  { 0x60, UNSET_OP_ORDER, "pushad" },
  { 0x61, UNSET_OP_ORDER, "popad" },
  { 0x9C, UNSET_OP_ORDER, "pushfd" },
  { 0x9D, UNSET_OP_ORDER, "popfd" },
  { 0x9E, UNSET_OP_ORDER, "sahf" },
  { 0x99, UNSET_OP_ORDER, "cdq" },
  { 0x9B, UNSET_OP_ORDER, "fwait" },
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  { 0xA4, UNSET_OP_ORDER, "movs" },
  { 0xA5, UNSET_OP_ORDER, "movs" },
  { 0xA6, UNSET_OP_ORDER, "cmps" },
  { 0xA7, UNSET_OP_ORDER, "cmps" },
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  { -1, UNSET_OP_ORDER, "" }
};


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static const ByteMnemonic call_jump_instr[] = {
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  { 0xE8, UNSET_OP_ORDER, "call" },
  { 0xE9, UNSET_OP_ORDER, "jmp" },
  { -1, UNSET_OP_ORDER, "" }
};


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static const ByteMnemonic short_immediate_instr[] = {
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  { 0x05, UNSET_OP_ORDER, "add" },
  { 0x0D, UNSET_OP_ORDER, "or" },
  { 0x15, UNSET_OP_ORDER, "adc" },
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  { 0x1D, UNSET_OP_ORDER, "sbb" },
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  { 0x25, UNSET_OP_ORDER, "and" },
  { 0x2D, UNSET_OP_ORDER, "sub" },
  { 0x35, UNSET_OP_ORDER, "xor" },
  { 0x3D, UNSET_OP_ORDER, "cmp" },
  { -1, UNSET_OP_ORDER, "" }
};


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static const char* const conditional_code_suffix[] = {
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  "o", "no", "c", "nc", "z", "nz", "na", "a",
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  "s", "ns", "pe", "po", "l", "ge", "le", "g"
};


enum InstructionType {
  NO_INSTR,
  ZERO_OPERANDS_INSTR,
  TWO_OPERANDS_INSTR,
  JUMP_CONDITIONAL_SHORT_INSTR,
  REGISTER_INSTR,
  PUSHPOP_INSTR,  // Has implicit 64-bit operand size.
  MOVE_REG_INSTR,
  CALL_JUMP_INSTR,
  SHORT_IMMEDIATE_INSTR
};

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enum Prefixes {
  ESCAPE_PREFIX = 0x0F,
  OPERAND_SIZE_OVERRIDE_PREFIX = 0x66,
  ADDRESS_SIZE_OVERRIDE_PREFIX = 0x67,
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  VEX3_PREFIX = 0xC4,
  VEX2_PREFIX = 0xC5,
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  LOCK_PREFIX = 0xF0,
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  REPNE_PREFIX = 0xF2,
  REP_PREFIX = 0xF3,
  REPEQ_PREFIX = REP_PREFIX
};

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struct InstructionDesc {
  const char* mnem;
  InstructionType type;
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  OperandType op_order_;
  bool byte_size_operation;  // Fixed 8-bit operation.
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};


class InstructionTable {
 public:
  InstructionTable();
  const InstructionDesc& Get(byte x) const {
    return instructions_[x];
  }

 private:
  InstructionDesc instructions_[256];
  void Clear();
  void Init();
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  void CopyTable(const ByteMnemonic bm[], InstructionType type);
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  void SetTableRange(InstructionType type, byte start, byte end, bool byte_size,
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                     const char* mnem);
  void AddJumpConditionalShort();
};


InstructionTable::InstructionTable() {
  Clear();
  Init();
}


void InstructionTable::Clear() {
  for (int i = 0; i < 256; i++) {
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    instructions_[i].mnem = "(bad)";
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    instructions_[i].type = NO_INSTR;
    instructions_[i].op_order_ = UNSET_OP_ORDER;
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    instructions_[i].byte_size_operation = false;
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  }
}


void InstructionTable::Init() {
  CopyTable(two_operands_instr, TWO_OPERANDS_INSTR);
  CopyTable(zero_operands_instr, ZERO_OPERANDS_INSTR);
  CopyTable(call_jump_instr, CALL_JUMP_INSTR);
  CopyTable(short_immediate_instr, SHORT_IMMEDIATE_INSTR);
  AddJumpConditionalShort();
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  SetTableRange(PUSHPOP_INSTR, 0x50, 0x57, false, "push");
  SetTableRange(PUSHPOP_INSTR, 0x58, 0x5F, false, "pop");
  SetTableRange(MOVE_REG_INSTR, 0xB8, 0xBF, false, "mov");
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}


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void InstructionTable::CopyTable(const ByteMnemonic bm[],
                                 InstructionType type) {
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  for (int i = 0; bm[i].b >= 0; i++) {
    InstructionDesc* id = &instructions_[bm[i].b];
    id->mnem = bm[i].mnem;
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    OperandType op_order = bm[i].op_order_;
    id->op_order_ =
        static_cast<OperandType>(op_order & ~BYTE_SIZE_OPERAND_FLAG);
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    DCHECK_EQ(NO_INSTR, id->type);  // Information not already entered
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    id->type = type;
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    id->byte_size_operation = ((op_order & BYTE_SIZE_OPERAND_FLAG) != 0);
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  }
}


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void InstructionTable::SetTableRange(InstructionType type,
                                     byte start,
                                     byte end,
                                     bool byte_size,
                                     const char* mnem) {
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  for (byte b = start; b <= end; b++) {
    InstructionDesc* id = &instructions_[b];
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    DCHECK_EQ(NO_INSTR, id->type);  // Information not already entered
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    id->mnem = mnem;
    id->type = type;
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    id->byte_size_operation = byte_size;
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  }
}


void InstructionTable::AddJumpConditionalShort() {
  for (byte b = 0x70; b <= 0x7F; b++) {
    InstructionDesc* id = &instructions_[b];
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    DCHECK_EQ(NO_INSTR, id->type);  // Information not already entered
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    id->mnem = nullptr;             // Computed depending on condition code.
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    id->type = JUMP_CONDITIONAL_SHORT_INSTR;
  }
}

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namespace {
DEFINE_LAZY_LEAKY_OBJECT_GETTER(InstructionTable, GetInstructionTable);
}
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static const InstructionDesc cmov_instructions[16] = {
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  {"cmovo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovno", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovnc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovnz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovna", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmova", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovs", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovns", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovpe", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovpo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovl", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovge", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovle", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovg", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}
};
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//------------------------------------------------------------------------------
// DisassemblerX64 implementation.

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// A new DisassemblerX64 object is created to disassemble each instruction.
// The object can only disassemble a single instruction.
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class DisassemblerX64 {
 public:
  DisassemblerX64(const NameConverter& converter,
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                  Disassembler::UnimplementedOpcodeAction unimplemented_action)
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      : converter_(converter),
        tmp_buffer_pos_(0),
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        abort_on_unimplemented_(unimplemented_action ==
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                                Disassembler::kAbortOnUnimplementedOpcode),
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        rex_(0),
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        operand_size_(0),
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        group_1_prefix_(0),
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        vex_byte0_(0),
        vex_byte1_(0),
        vex_byte2_(0),
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        byte_size_operand_(false),
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        instruction_table_(GetInstructionTable()) {
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    tmp_buffer_[0] = '\0';
  }

  // Writes one disassembled instruction into 'buffer' (0-terminated).
  // Returns the length of the disassembled machine instruction in bytes.
  int InstructionDecode(v8::internal::Vector<char> buffer, byte* instruction);

 private:
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  enum OperandSize {
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    OPERAND_BYTE_SIZE = 0,
    OPERAND_WORD_SIZE = 1,
    OPERAND_DOUBLEWORD_SIZE = 2,
    OPERAND_QUADWORD_SIZE = 3
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  };
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  const NameConverter& converter_;
  v8::internal::EmbeddedVector<char, 128> tmp_buffer_;
  unsigned int tmp_buffer_pos_;
  bool abort_on_unimplemented_;
  // Prefixes parsed
  byte rex_;
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  byte operand_size_;  // 0x66 or (if no group 3 prefix is present) 0x0.
  byte group_1_prefix_;  // 0xF2, 0xF3, or (if no group 1 prefix is present) 0.
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  byte vex_byte0_;       // 0xC4 or 0xC5
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  byte vex_byte1_;
  byte vex_byte2_;  // only for 3 bytes vex prefix
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  // Byte size operand override.
  bool byte_size_operand_;
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  const InstructionTable* const instruction_table_;
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  void setRex(byte rex) {
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    DCHECK_EQ(0x40, rex & 0xF0);
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    rex_ = rex;
  }

  bool rex() { return rex_ != 0; }

  bool rex_b() { return (rex_ & 0x01) != 0; }

  // Actual number of base register given the low bits and the rex.b state.
  int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); }

  bool rex_x() { return (rex_ & 0x02) != 0; }

  bool rex_r() { return (rex_ & 0x04) != 0; }

  bool rex_w() { return (rex_ & 0x08) != 0; }

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  bool vex_w() {
    DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
    return vex_byte0_ == VEX3_PREFIX ? (vex_byte2_ & 0x80) != 0 : false;
  }

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  bool vex_128() {
    DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
    byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
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    return (checked & 4) == 0;
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  }

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  bool vex_none() {
    DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
    byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
    return (checked & 3) == 0;
  }

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  bool vex_66() {
    DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
    byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
    return (checked & 3) == 1;
  }

  bool vex_f3() {
    DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
    byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
    return (checked & 3) == 2;
  }

  bool vex_f2() {
    DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
    byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
    return (checked & 3) == 3;
  }

  bool vex_0f() {
    if (vex_byte0_ == VEX2_PREFIX) return true;
    return (vex_byte1_ & 3) == 1;
  }

  bool vex_0f38() {
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    if (vex_byte0_ == VEX2_PREFIX) return false;
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    return (vex_byte1_ & 3) == 2;
  }

  bool vex_0f3a() {
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    if (vex_byte0_ == VEX2_PREFIX) return false;
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    return (vex_byte1_ & 3) == 3;
  }

  int vex_vreg() {
    DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
    byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
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    return ~(checked >> 3) & 0xF;
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  }

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  OperandSize operand_size() {
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    if (byte_size_operand_) return OPERAND_BYTE_SIZE;
    if (rex_w()) return OPERAND_QUADWORD_SIZE;
    if (operand_size_ != 0) return OPERAND_WORD_SIZE;
    return OPERAND_DOUBLEWORD_SIZE;
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  }

  char operand_size_code() {
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    return "bwlq"[operand_size()];
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  }

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  char float_size_code() { return "sd"[rex_w()]; }

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  const char* NameOfCPURegister(int reg) const {
    return converter_.NameOfCPURegister(reg);
  }

  const char* NameOfByteCPURegister(int reg) const {
    return converter_.NameOfByteCPURegister(reg);
  }

  const char* NameOfXMMRegister(int reg) const {
    return converter_.NameOfXMMRegister(reg);
  }

  const char* NameOfAddress(byte* addr) const {
    return converter_.NameOfAddress(addr);
  }

  // Disassembler helper functions.
  void get_modrm(byte data,
                 int* mod,
                 int* regop,
                 int* rm) {
    *mod = (data >> 6) & 3;
    *regop = ((data & 0x38) >> 3) | (rex_r() ? 8 : 0);
    *rm = (data & 7) | (rex_b() ? 8 : 0);
  }

  void get_sib(byte data,
               int* scale,
               int* index,
               int* base) {
    *scale = (data >> 6) & 3;
    *index = ((data >> 3) & 7) | (rex_x() ? 8 : 0);
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    *base = (data & 7) | (rex_b() ? 8 : 0);
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  }

  typedef const char* (DisassemblerX64::*RegisterNameMapping)(int reg) const;

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  void TryAppendRootRelativeName(int offset);
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  int PrintRightOperandHelper(byte* modrmp,
                              RegisterNameMapping register_name);
  int PrintRightOperand(byte* modrmp);
  int PrintRightByteOperand(byte* modrmp);
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  int PrintRightXMMOperand(byte* modrmp);
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  int PrintOperands(const char* mnem,
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                    OperandType op_order,
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                    byte* data);
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  int PrintImmediate(byte* data, OperandSize size);
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  int PrintImmediateOp(byte* data);
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  const char* TwoByteMnemonic(byte opcode);
  int TwoByteOpcodeInstruction(byte* data);
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  int F6F7Instruction(byte* data);
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  int ShiftInstruction(byte* data);
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  int JumpShort(byte* data);
  int JumpConditional(byte* data);
  int JumpConditionalShort(byte* data);
  int SetCC(byte* data);
  int FPUInstruction(byte* data);
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  int MemoryFPUInstruction(int escape_opcode, int regop, byte* modrm_start);
  int RegisterFPUInstruction(int escape_opcode, byte modrm_byte);
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  int AVXInstruction(byte* data);
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  PRINTF_FORMAT(2, 3) void AppendToBuffer(const char* format, ...);
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  void UnimplementedInstruction() {
    if (abort_on_unimplemented_) {
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      FATAL("'Unimplemented Instruction'");
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    } else {
      AppendToBuffer("'Unimplemented Instruction'");
    }
  }
};


void DisassemblerX64::AppendToBuffer(const char* format, ...) {
  v8::internal::Vector<char> buf = tmp_buffer_ + tmp_buffer_pos_;
  va_list args;
  va_start(args, format);
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  int result = v8::internal::VSNPrintF(buf, format, args);
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  va_end(args);
  tmp_buffer_pos_ += result;
}

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void DisassemblerX64::TryAppendRootRelativeName(int offset) {
  const char* maybe_name = converter_.RootRelativeName(offset);
  if (maybe_name != nullptr) AppendToBuffer(" (%s)", maybe_name);
}
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int DisassemblerX64::PrintRightOperandHelper(
    byte* modrmp,
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    RegisterNameMapping direct_register_name) {
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  int mod, regop, rm;
  get_modrm(*modrmp, &mod, &regop, &rm);
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  RegisterNameMapping register_name = (mod == 3) ? direct_register_name :
      &DisassemblerX64::NameOfCPURegister;
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  switch (mod) {
    case 0:
      if ((rm & 7) == 5) {
        int32_t disp = *reinterpret_cast<int32_t*>(modrmp + 1);
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        AppendToBuffer("[rip+0x%x]", disp);
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        return 5;
      } else if ((rm & 7) == 4) {
        // Codes for SIB byte.
        byte sib = *(modrmp + 1);
        int scale, index, base;
        get_sib(sib, &scale, &index, &base);
        if (index == 4 && (base & 7) == 4 && scale == 0 /*times_1*/) {
          // index == rsp means no index. Only use sib byte with no index for
          // rsp and r12 base.
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          AppendToBuffer("[%s]", NameOfCPURegister(base));
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          return 2;
        } else if (base == 5) {
          // base == rbp means no base register (when mod == 0).
          int32_t disp = *reinterpret_cast<int32_t*>(modrmp + 2);
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          AppendToBuffer("[%s*%d%s0x%x]",
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                         NameOfCPURegister(index),
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                         1 << scale,
                         disp < 0 ? "-" : "+",
                         disp < 0 ? -disp : disp);
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          return 6;
        } else if (index != 4 && base != 5) {
          // [base+index*scale]
          AppendToBuffer("[%s+%s*%d]",
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                         NameOfCPURegister(base),
                         NameOfCPURegister(index),
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                         1 << scale);
          return 2;
        } else {
          UnimplementedInstruction();
          return 1;
        }
      } else {
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        AppendToBuffer("[%s]", NameOfCPURegister(rm));
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        return 1;
      }
      break;
    case 1:  // fall through
    case 2:
      if ((rm & 7) == 4) {
        byte sib = *(modrmp + 1);
        int scale, index, base;
        get_sib(sib, &scale, &index, &base);
        int disp = (mod == 2) ? *reinterpret_cast<int32_t*>(modrmp + 2)
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                              : *reinterpret_cast<int8_t*>(modrmp + 2);
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        if (index == 4 && (base & 7) == 4 && scale == 0 /*times_1*/) {
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          AppendToBuffer("[%s%s0x%x]",
                         NameOfCPURegister(base),
                         disp < 0 ? "-" : "+",
                         disp < 0 ? -disp : disp);
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        } else {
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          AppendToBuffer("[%s+%s*%d%s0x%x]",
                         NameOfCPURegister(base),
                         NameOfCPURegister(index),
                         1 << scale,
                         disp < 0 ? "-" : "+",
                         disp < 0 ? -disp : disp);
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        }
        return mod == 2 ? 6 : 3;
      } else {
        // No sib.
        int disp = (mod == 2) ? *reinterpret_cast<int32_t*>(modrmp + 1)
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                              : *reinterpret_cast<int8_t*>(modrmp + 1);
        AppendToBuffer("[%s%s0x%x]",
                       NameOfCPURegister(rm),
                       disp < 0 ? "-" : "+",
                       disp < 0 ? -disp : disp);
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        if (rm == i::kRootRegister.code()) {
          // For root-relative accesses, try to append a description.
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          TryAppendRootRelativeName(disp);
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        }
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        return (mod == 2) ? 5 : 2;
      }
      break;
    case 3:
      AppendToBuffer("%s", (this->*register_name)(rm));
      return 1;
    default:
      UnimplementedInstruction();
      return 1;
  }
  UNREACHABLE();
}


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int DisassemblerX64::PrintImmediate(byte* data, OperandSize size) {
  int64_t value;
  int count;
  switch (size) {
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    case OPERAND_BYTE_SIZE:
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      value = *data;
      count = 1;
      break;
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    case OPERAND_WORD_SIZE:
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      value = *reinterpret_cast<int16_t*>(data);
      count = 2;
      break;
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    case OPERAND_DOUBLEWORD_SIZE:
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      value = *reinterpret_cast<uint32_t*>(data);
      count = 4;
      break;
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    case OPERAND_QUADWORD_SIZE:
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      value = *reinterpret_cast<int32_t*>(data);
      count = 4;
      break;
    default:
      UNREACHABLE();
  }
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  AppendToBuffer("%" PRIx64, value);
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  return count;
}


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int DisassemblerX64::PrintRightOperand(byte* modrmp) {
  return PrintRightOperandHelper(modrmp,
                                 &DisassemblerX64::NameOfCPURegister);
}


int DisassemblerX64::PrintRightByteOperand(byte* modrmp) {
  return PrintRightOperandHelper(modrmp,
                                 &DisassemblerX64::NameOfByteCPURegister);
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}
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int DisassemblerX64::PrintRightXMMOperand(byte* modrmp) {
  return PrintRightOperandHelper(modrmp,
                                 &DisassemblerX64::NameOfXMMRegister);
}


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// Returns number of bytes used including the current *data.
// Writes instruction's mnemonic, left and right operands to 'tmp_buffer_'.
int DisassemblerX64::PrintOperands(const char* mnem,
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                                   OperandType op_order,
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                                   byte* data) {
  byte modrm = *data;
  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
  int advance = 0;
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  const char* register_name =
      byte_size_operand_ ? NameOfByteCPURegister(regop)
                         : NameOfCPURegister(regop);
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  switch (op_order) {
    case REG_OPER_OP_ORDER: {
      AppendToBuffer("%s%c %s,",
                     mnem,
                     operand_size_code(),
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                     register_name);
      advance = byte_size_operand_ ? PrintRightByteOperand(data)
                                   : PrintRightOperand(data);
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      break;
    }
    case OPER_REG_OP_ORDER: {
      AppendToBuffer("%s%c ", mnem, operand_size_code());
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      advance = byte_size_operand_ ? PrintRightByteOperand(data)
                                   : PrintRightOperand(data);
      AppendToBuffer(",%s", register_name);
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      break;
    }
    default:
      UNREACHABLE();
      break;
  }
  return advance;
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}
679 680


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// Returns number of bytes used by machine instruction, including *data byte.
// Writes immediate instructions to 'tmp_buffer_'.
int DisassemblerX64::PrintImmediateOp(byte* data) {
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  bool byte_size_immediate = (*data & 0x02) != 0;
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  byte modrm = *(data + 1);
  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
  const char* mnem = "Imm???";
  switch (regop) {
    case 0:
      mnem = "add";
      break;
    case 1:
      mnem = "or";
      break;
    case 2:
      mnem = "adc";
      break;
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    case 3:
      mnem = "sbb";
      break;
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    case 4:
      mnem = "and";
      break;
    case 5:
      mnem = "sub";
      break;
    case 6:
      mnem = "xor";
      break;
    case 7:
      mnem = "cmp";
      break;
    default:
      UnimplementedInstruction();
  }
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  AppendToBuffer("%s%c ", mnem, operand_size_code());
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  int count = PrintRightOperand(data + 1);
719
  AppendToBuffer(",0x");
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  OperandSize immediate_size =
      byte_size_immediate ? OPERAND_BYTE_SIZE : operand_size();
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  count += PrintImmediate(data + 1 + count, immediate_size);
  return 1 + count;
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}


// Returns number of bytes used, including *data.
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int DisassemblerX64::F6F7Instruction(byte* data) {
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  DCHECK(*data == 0xF7 || *data == 0xF6);
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  byte modrm = *(data + 1);
  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
  if (mod == 3 && regop != 0) {
734
    const char* mnem = nullptr;
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    switch (regop) {
      case 2:
        mnem = "not";
        break;
      case 3:
        mnem = "neg";
        break;
      case 4:
        mnem = "mul";
        break;
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      case 5:
        mnem = "imul";
        break;
748 749 750
      case 6:
        mnem = "div";
        break;
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      case 7:
        mnem = "idiv";
        break;
      default:
        UnimplementedInstruction();
    }
    AppendToBuffer("%s%c %s",
                   mnem,
                   operand_size_code(),
                   NameOfCPURegister(rm));
    return 2;
  } else if (regop == 0) {
    AppendToBuffer("test%c ", operand_size_code());
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    int count = PrintRightOperand(data + 1);  // Use name of 64-bit register.
    AppendToBuffer(",0x");
    count += PrintImmediate(data + 1 + count, operand_size());
    return 1 + count;
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  } else {
    UnimplementedInstruction();
    return 2;
  }
}


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int DisassemblerX64::ShiftInstruction(byte* data) {
  byte op = *data & (~1);
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  int count = 1;
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  if (op != 0xD0 && op != 0xD2 && op != 0xC0) {
    UnimplementedInstruction();
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    return count;
781
  }
782 783 784 785 786 787
  // Print mneumonic.
  {
    byte modrm = *(data + count);
    int mod, regop, rm;
    get_modrm(modrm, &mod, &regop, &rm);
    regop &= 0x7;  // The REX.R bit does not affect the operation.
788
    const char* mnem = nullptr;
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    switch (regop) {
      case 0:
        mnem = "rol";
        break;
      case 1:
        mnem = "ror";
        break;
      case 2:
        mnem = "rcl";
        break;
      case 3:
        mnem = "rcr";
        break;
      case 4:
        mnem = "shl";
        break;
      case 5:
        mnem = "shr";
        break;
      case 7:
        mnem = "sar";
        break;
      default:
        UnimplementedInstruction();
        return count + 1;
    }
815
    DCHECK_NOT_NULL(mnem);
816
    AppendToBuffer("%s%c ", mnem, operand_size_code());
817
  }
818
  count += PrintRightOperand(data + count);
819
  if (op == 0xD2) {
820
    AppendToBuffer(", cl");
821
  } else {
822 823 824 825 826 827 828 829 830
    int imm8 = -1;
    if (op == 0xD0) {
      imm8 = 1;
    } else {
      DCHECK_EQ(0xC0, op);
      imm8 = *(data + count);
      count++;
    }
    AppendToBuffer(", %d", imm8);
831
  }
832
  return count;
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}


// Returns number of bytes used, including *data.
int DisassemblerX64::JumpShort(byte* data) {
838
  DCHECK_EQ(0xEB, *data);
839 840 841 842 843 844 845 846 847
  byte b = *(data + 1);
  byte* dest = data + static_cast<int8_t>(b) + 2;
  AppendToBuffer("jmp %s", NameOfAddress(dest));
  return 2;
}


// Returns number of bytes used, including *data.
int DisassemblerX64::JumpConditional(byte* data) {
848
  DCHECK_EQ(0x0F, *data);
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  byte cond = *(data + 1) & 0x0F;
  byte* dest = data + *reinterpret_cast<int32_t*>(data + 2) + 6;
  const char* mnem = conditional_code_suffix[cond];
  AppendToBuffer("j%s %s", mnem, NameOfAddress(dest));
  return 6;  // includes 0x0F
}


// Returns number of bytes used, including *data.
int DisassemblerX64::JumpConditionalShort(byte* data) {
  byte cond = *data & 0x0F;
  byte b = *(data + 1);
  byte* dest = data + static_cast<int8_t>(b) + 2;
  const char* mnem = conditional_code_suffix[cond];
  AppendToBuffer("j%s %s", mnem, NameOfAddress(dest));
  return 2;
}


// Returns number of bytes used, including *data.
int DisassemblerX64::SetCC(byte* data) {
870
  DCHECK_EQ(0x0F, *data);
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  byte cond = *(data + 1) & 0x0F;
  const char* mnem = conditional_code_suffix[cond];
  AppendToBuffer("set%s%c ", mnem, operand_size_code());
  PrintRightByteOperand(data + 2);
  return 3;  // includes 0x0F
}

878
const char* sf_str[4] = {"", "rl", "ra", "ll"};
879

880 881 882
int DisassemblerX64::AVXInstruction(byte* data) {
  byte opcode = *data;
  byte* current = data + 1;
883
  if (vex_66() && vex_0f38()) {
884 885 886 887 888 889 890 891
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
      case 0x99:
        AppendToBuffer("vfmadd132s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
892
      case 0xA9:
893 894 895 896
        AppendToBuffer("vfmadd213s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
897
      case 0xB9:
898 899 900 901
        AppendToBuffer("vfmadd231s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
902
      case 0x9B:
903 904 905 906
        AppendToBuffer("vfmsub132s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
907
      case 0xAB:
908 909 910 911
        AppendToBuffer("vfmsub213s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
912
      case 0xBB:
913 914 915 916
        AppendToBuffer("vfmsub231s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
917
      case 0x9D:
918 919 920 921
        AppendToBuffer("vfnmadd132s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
922
      case 0xAD:
923 924 925 926
        AppendToBuffer("vfnmadd213s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
927
      case 0xBD:
928 929 930 931
        AppendToBuffer("vfnmadd231s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
932
      case 0x9F:
933 934 935 936
        AppendToBuffer("vfnmsub132s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
937
      case 0xAF:
938 939 940 941
        AppendToBuffer("vfnmsub213s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
942
      case 0xBF:
943 944 945 946
        AppendToBuffer("vfnmsub231s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
947
      case 0xF7:
948 949 950 951 952
        AppendToBuffer("shlx%c %s,", operand_size_code(),
                       NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
953 954 955 956 957 958 959 960 961 962 963 964
#define DECLARE_SSE_AVX_DIS_CASE(instruction, notUsed1, notUsed2, notUsed3, \
                                 opcode)                                    \
  case 0x##opcode: {                                                        \
    AppendToBuffer("v" #instruction " %s,%s,", NameOfXMMRegister(regop),    \
                   NameOfXMMRegister(vvvv));                                \
    current += PrintRightXMMOperand(current);                               \
    break;                                                                  \
  }

        SSSE3_INSTRUCTION_LIST(DECLARE_SSE_AVX_DIS_CASE)
        SSE4_INSTRUCTION_LIST(DECLARE_SSE_AVX_DIS_CASE)
#undef DECLARE_SSE_AVX_DIS_CASE
965 966 967
      default:
        UnimplementedInstruction();
    }
968 969 970 971
  } else if (vex_66() && vex_0f3a()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
972
      case 0x0A:
973 974 975 976 977
        AppendToBuffer("vroundss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",0x%x", *current++);
        break;
978
      case 0x0B:
979 980 981 982 983
        AppendToBuffer("vroundsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",0x%x", *current++);
        break;
984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010
      case 0x14:
        AppendToBuffer("vpextrb ");
        current += PrintRightByteOperand(current);
        AppendToBuffer(",%s,0x%x,", NameOfXMMRegister(regop), *current++);
        break;
      case 0x15:
        AppendToBuffer("vpextrw ");
        current += PrintRightOperand(current);
        AppendToBuffer(",%s,0x%x,", NameOfXMMRegister(regop), *current++);
        break;
      case 0x16:
        AppendToBuffer("vpextrd ");
        current += PrintRightOperand(current);
        AppendToBuffer(",%s,0x%x,", NameOfXMMRegister(regop), *current++);
        break;
      case 0x20:
        AppendToBuffer("vpinsrb %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightByteOperand(current);
        AppendToBuffer(",0x%x", *current++);
        break;
      case 0x22:
        AppendToBuffer("vpinsrd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightOperand(current);
        AppendToBuffer(",0x%x", *current++);
        break;
1011 1012 1013
      default:
        UnimplementedInstruction();
    }
1014 1015 1016 1017
  } else if (vex_f3() && vex_0f()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
1018 1019
      case 0x10:
        AppendToBuffer("vmovss %s,", NameOfXMMRegister(regop));
1020 1021 1022
        if (mod == 3) {
          AppendToBuffer("%s,", NameOfXMMRegister(vvvv));
        }
1023 1024 1025 1026 1027
        current += PrintRightXMMOperand(current);
        break;
      case 0x11:
        AppendToBuffer("vmovss ");
        current += PrintRightXMMOperand(current);
1028 1029 1030
        if (mod == 3) {
          AppendToBuffer(",%s", NameOfXMMRegister(vvvv));
        }
1031 1032
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
        break;
1033
      case 0x2A:
1034 1035 1036 1037
        AppendToBuffer("%s %s,%s,", vex_w() ? "vcvtqsi2ss" : "vcvtlsi2ss",
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightOperand(current);
        break;
1038
      case 0x2C:
1039 1040 1041 1042
        AppendToBuffer("vcvttss2si%s %s,", vex_w() ? "q" : "",
                       NameOfCPURegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1043 1044 1045 1046 1047
      case 0x51:
        AppendToBuffer("vsqrtss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1048 1049 1050 1051 1052 1053 1054 1055 1056 1057
      case 0x58:
        AppendToBuffer("vaddss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x59:
        AppendToBuffer("vmulss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1058
      case 0x5A:
1059 1060 1061 1062
        AppendToBuffer("vcvtss2sd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1063
      case 0x5C:
1064 1065 1066 1067
        AppendToBuffer("vsubss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1068
      case 0x5D:
1069 1070 1071 1072
        AppendToBuffer("vminss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1073
      case 0x5E:
1074 1075 1076 1077
        AppendToBuffer("vdivss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1078
      case 0x5F:
1079 1080 1081 1082 1083 1084 1085
        AppendToBuffer("vmaxss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      default:
        UnimplementedInstruction();
    }
1086 1087 1088 1089
  } else if (vex_f2() && vex_0f()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
1090 1091
      case 0x10:
        AppendToBuffer("vmovsd %s,", NameOfXMMRegister(regop));
1092 1093 1094
        if (mod == 3) {
          AppendToBuffer("%s,", NameOfXMMRegister(vvvv));
        }
1095 1096 1097 1098 1099
        current += PrintRightXMMOperand(current);
        break;
      case 0x11:
        AppendToBuffer("vmovsd ");
        current += PrintRightXMMOperand(current);
1100 1101 1102
        if (mod == 3) {
          AppendToBuffer(",%s", NameOfXMMRegister(vvvv));
        }
1103 1104
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
        break;
1105
      case 0x2A:
1106 1107
        AppendToBuffer("%s %s,%s,", vex_w() ? "vcvtqsi2sd" : "vcvtlsi2sd",
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
1108 1109
        current += PrintRightOperand(current);
        break;
1110
      case 0x2C:
1111 1112 1113 1114
        AppendToBuffer("vcvttsd2si%s %s,", vex_w() ? "q" : "",
                       NameOfCPURegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1115
      case 0x2D:
1116 1117 1118 1119
        AppendToBuffer("vcvtsd2si%s %s,", vex_w() ? "q" : "",
                       NameOfCPURegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1120 1121 1122 1123 1124
      case 0x51:
        AppendToBuffer("vsqrtsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1125 1126 1127 1128 1129 1130 1131 1132 1133 1134
      case 0x58:
        AppendToBuffer("vaddsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x59:
        AppendToBuffer("vmulsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1135
      case 0x5A:
1136 1137 1138 1139
        AppendToBuffer("vcvtsd2ss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1140
      case 0x5C:
1141 1142 1143 1144
        AppendToBuffer("vsubsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1145
      case 0x5D:
1146 1147 1148 1149
        AppendToBuffer("vminsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1150
      case 0x5E:
1151 1152 1153 1154
        AppendToBuffer("vdivsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1155
      case 0x5F:
1156 1157 1158 1159
        AppendToBuffer("vmaxsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1160
      case 0xF0:
1161 1162 1163
        AppendToBuffer("vlddqu %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1164 1165 1166 1167 1168
      case 0x7C:
        AppendToBuffer("vhaddps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1169 1170
      default:
        UnimplementedInstruction();
1171
    }
1172 1173 1174 1175 1176
  } else if (vex_none() && vex_0f38()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    const char* mnem = "?";
    switch (opcode) {
1177
      case 0xF2:
1178 1179 1180 1181
        AppendToBuffer("andn%c %s,%s,", operand_size_code(),
                       NameOfCPURegister(regop), NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        break;
1182
      case 0xF5:
1183 1184 1185 1186 1187
        AppendToBuffer("bzhi%c %s,", operand_size_code(),
                       NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
1188
      case 0xF7:
1189 1190 1191 1192 1193
        AppendToBuffer("bextr%c %s,", operand_size_code(),
                       NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
1194
      case 0xF3:
1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219
        switch (regop) {
          case 1:
            mnem = "blsr";
            break;
          case 2:
            mnem = "blsmsk";
            break;
          case 3:
            mnem = "blsi";
            break;
          default:
            UnimplementedInstruction();
        }
        AppendToBuffer("%s%c %s,", mnem, operand_size_code(),
                       NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        mnem = "?";
        break;
      default:
        UnimplementedInstruction();
    }
  } else if (vex_f2() && vex_0f38()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
1220
      case 0xF5:
1221 1222 1223 1224
        AppendToBuffer("pdep%c %s,%s,", operand_size_code(),
                       NameOfCPURegister(regop), NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        break;
1225
      case 0xF6:
1226 1227 1228 1229
        AppendToBuffer("mulx%c %s,%s,", operand_size_code(),
                       NameOfCPURegister(regop), NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        break;
1230
      case 0xF7:
1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242
        AppendToBuffer("shrx%c %s,", operand_size_code(),
                       NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
      default:
        UnimplementedInstruction();
    }
  } else if (vex_f3() && vex_0f38()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
1243
      case 0xF5:
1244 1245 1246 1247
        AppendToBuffer("pext%c %s,%s,", operand_size_code(),
                       NameOfCPURegister(regop), NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        break;
1248
      case 0xF7:
1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260
        AppendToBuffer("sarx%c %s,", operand_size_code(),
                       NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
      default:
        UnimplementedInstruction();
    }
  } else if (vex_f2() && vex_0f3a()) {
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
1261
      case 0xF0:
1262 1263 1264 1265 1266
        AppendToBuffer("rorx%c %s,", operand_size_code(),
                       NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        switch (operand_size()) {
          case OPERAND_DOUBLEWORD_SIZE:
1267
            AppendToBuffer(",%d", *current & 0x1F);
1268 1269
            break;
          case OPERAND_QUADWORD_SIZE:
1270
            AppendToBuffer(",%d", *current & 0x3F);
1271 1272 1273 1274 1275 1276 1277 1278 1279
            break;
          default:
            UnimplementedInstruction();
        }
        current += 1;
        break;
      default:
        UnimplementedInstruction();
    }
1280 1281 1282 1283
  } else if (vex_none() && vex_0f()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
1284 1285 1286 1287 1288 1289 1290 1291 1292
      case 0x10:
        AppendToBuffer("vmovups %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
      case 0x11:
        AppendToBuffer("vmovups ");
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
        break;
1293 1294 1295 1296 1297 1298 1299 1300 1301
      case 0x28:
        AppendToBuffer("vmovaps %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
      case 0x29:
        AppendToBuffer("vmovaps ");
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
        break;
1302
      case 0x2E:
1303 1304 1305
        AppendToBuffer("vucomiss %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1306 1307 1308 1309
      case 0x50:
        AppendToBuffer("vmovmskps %s,", NameOfCPURegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1310 1311 1312 1313 1314 1315 1316 1317 1318 1319
      case 0x54:
        AppendToBuffer("vandps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x57:
        AppendToBuffer("vxorps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1320 1321 1322 1323 1324 1325 1326 1327 1328 1329
      case 0xC2: {
        AppendToBuffer("vcmpps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        const char* const pseudo_op[] = {"eq",  "lt",  "le",  "unord",
                                         "neq", "nlt", "nle", "ord"};
        AppendToBuffer(", (%s)", pseudo_op[*current]);
        current += 1;
        break;
      }
1330 1331 1332 1333 1334 1335 1336
      default:
        UnimplementedInstruction();
    }
  } else if (vex_66() && vex_0f()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
1337 1338 1339 1340 1341 1342 1343 1344 1345
      case 0x10:
        AppendToBuffer("vmovupd %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
      case 0x11:
        AppendToBuffer("vmovupd ");
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
        break;
1346 1347 1348 1349 1350 1351 1352 1353 1354
      case 0x28:
        AppendToBuffer("vmovapd %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
      case 0x29:
        AppendToBuffer("vmovapd ");
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
        break;
1355
      case 0x2E:
1356 1357 1358
        AppendToBuffer("vucomisd %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1359 1360 1361 1362
      case 0x50:
        AppendToBuffer("vmovmskpd %s,", NameOfCPURegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1363 1364 1365 1366 1367
      case 0x54:
        AppendToBuffer("vandpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1368 1369 1370 1371 1372
      case 0x56:
        AppendToBuffer("vorpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1373 1374 1375 1376 1377
      case 0x57:
        AppendToBuffer("vxorpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1378
      case 0x6E:
1379 1380 1381 1382
        AppendToBuffer("vmov%c %s,", vex_w() ? 'q' : 'd',
                       NameOfXMMRegister(regop));
        current += PrintRightOperand(current);
        break;
1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395
      case 0x70:
        AppendToBuffer("vpshufd %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",0x%x", *current++);
        break;
      case 0x71:
        AppendToBuffer("vps%sw %s,", sf_str[regop / 2],
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%u", *current++);
        break;
      case 0x72:
        AppendToBuffer("vps%sd %s,", sf_str[regop / 2],
1396 1397 1398 1399
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%u", *current++);
        break;
1400 1401
      case 0x73:
        AppendToBuffer("vps%sq %s,", sf_str[regop / 2],
1402 1403
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
1404
        AppendToBuffer(",%u", *current++);
1405
        break;
1406
      case 0x7E:
1407 1408 1409 1410
        AppendToBuffer("vmov%c ", vex_w() ? 'q' : 'd');
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
        break;
1411 1412 1413 1414 1415 1416 1417 1418 1419 1420
      case 0xC2: {
        AppendToBuffer("vcmppd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        const char* const pseudo_op[] = {"eq",  "lt",  "le",  "unord",
                                         "neq", "nlt", "nle", "ord"};
        AppendToBuffer(", (%s)", pseudo_op[*current]);
        current += 1;
        break;
      }
1421
      case 0xC4:
1422 1423 1424 1425 1426
        AppendToBuffer("vpinsrw %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightOperand(current);
        AppendToBuffer(",0x%x", *current++);
        break;
1427
      case 0xC5:
1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441
        AppendToBuffer("vpextrw %s,", NameOfCPURegister(regop));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",0x%x", *current++);
        break;
#define DECLARE_SSE_AVX_DIS_CASE(instruction, notUsed1, notUsed2, opcode) \
  case 0x##opcode: {                                                      \
    AppendToBuffer("v" #instruction " %s,%s,", NameOfXMMRegister(regop),  \
                   NameOfXMMRegister(vvvv));                              \
    current += PrintRightXMMOperand(current);                             \
    break;                                                                \
  }

        SSE2_INSTRUCTION_LIST(DECLARE_SSE_AVX_DIS_CASE)
#undef DECLARE_SSE_AVX_DIS_CASE
1442 1443 1444 1445
      default:
        UnimplementedInstruction();
    }

1446
  } else {
1447
    UnimplementedInstruction();
1448 1449 1450 1451 1452
  }

  return static_cast<int>(current - data);
}

1453 1454
// Returns number of bytes used, including *data.
int DisassemblerX64::FPUInstruction(byte* data) {
1455
  byte escape_opcode = *data;
1456
  DCHECK_EQ(0xD8, escape_opcode & 0xF8);
1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476
  byte modrm_byte = *(data+1);

  if (modrm_byte >= 0xC0) {
    return RegisterFPUInstruction(escape_opcode, modrm_byte);
  } else {
    return MemoryFPUInstruction(escape_opcode, modrm_byte, data+1);
  }
}

int DisassemblerX64::MemoryFPUInstruction(int escape_opcode,
                                           int modrm_byte,
                                           byte* modrm_start) {
  const char* mnem = "?";
  int regop = (modrm_byte >> 3) & 0x7;  // reg/op field of modrm byte.
  switch (escape_opcode) {
    case 0xD9: switch (regop) {
        case 0: mnem = "fld_s"; break;
        case 3: mnem = "fstp_s"; break;
        case 7: mnem = "fstcw"; break;
        default: UnimplementedInstruction();
1477
      }
1478 1479 1480 1481 1482 1483 1484 1485
      break;

    case 0xDB: switch (regop) {
        case 0: mnem = "fild_s"; break;
        case 1: mnem = "fisttp_s"; break;
        case 2: mnem = "fist_s"; break;
        case 3: mnem = "fistp_s"; break;
        default: UnimplementedInstruction();
1486
      }
1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521
      break;

    case 0xDD: switch (regop) {
        case 0: mnem = "fld_d"; break;
        case 3: mnem = "fstp_d"; break;
        default: UnimplementedInstruction();
      }
      break;

    case 0xDF: switch (regop) {
        case 5: mnem = "fild_d"; break;
        case 7: mnem = "fistp_d"; break;
        default: UnimplementedInstruction();
      }
      break;

    default: UnimplementedInstruction();
  }
  AppendToBuffer("%s ", mnem);
  int count = PrintRightOperand(modrm_start);
  return count + 1;
}

int DisassemblerX64::RegisterFPUInstruction(int escape_opcode,
                                             byte modrm_byte) {
  bool has_register = false;  // Is the FPU register encoded in modrm_byte?
  const char* mnem = "?";

  switch (escape_opcode) {
    case 0xD8:
      UnimplementedInstruction();
      break;

    case 0xD9:
      switch (modrm_byte & 0xF8) {
1522 1523 1524 1525
        case 0xC0:
          mnem = "fld";
          has_register = true;
          break;
1526 1527 1528
        case 0xC8:
          mnem = "fxch";
          has_register = true;
1529 1530
          break;
        default:
1531 1532 1533
          switch (modrm_byte) {
            case 0xE0: mnem = "fchs"; break;
            case 0xE1: mnem = "fabs"; break;
1534
            case 0xE3: mnem = "fninit"; break;
1535 1536
            case 0xE4: mnem = "ftst"; break;
            case 0xE8: mnem = "fld1"; break;
1537
            case 0xEB: mnem = "fldpi"; break;
1538
            case 0xED: mnem = "fldln2"; break;
1539
            case 0xEE: mnem = "fldz"; break;
1540
            case 0xF0: mnem = "f2xm1"; break;
1541
            case 0xF1: mnem = "fyl2x"; break;
1542
            case 0xF2: mnem = "fptan"; break;
1543 1544 1545
            case 0xF5: mnem = "fprem1"; break;
            case 0xF7: mnem = "fincstp"; break;
            case 0xF8: mnem = "fprem"; break;
1546
            case 0xFC: mnem = "frndint"; break;
1547
            case 0xFD: mnem = "fscale"; break;
1548 1549 1550 1551
            case 0xFE: mnem = "fsin"; break;
            case 0xFF: mnem = "fcos"; break;
            default: UnimplementedInstruction();
          }
1552
      }
1553 1554 1555 1556 1557 1558
      break;

    case 0xDA:
      if (modrm_byte == 0xE9) {
        mnem = "fucompp";
      } else {
1559
        UnimplementedInstruction();
1560 1561 1562 1563 1564 1565 1566 1567 1568
      }
      break;

    case 0xDB:
      if ((modrm_byte & 0xF8) == 0xE8) {
        mnem = "fucomi";
        has_register = true;
      } else if (modrm_byte  == 0xE2) {
        mnem = "fclex";
1569 1570
      } else if (modrm_byte == 0xE3) {
        mnem = "fninit";
1571
      } else {
1572
        UnimplementedInstruction();
1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625
      }
      break;

    case 0xDC:
      has_register = true;
      switch (modrm_byte & 0xF8) {
        case 0xC0: mnem = "fadd"; break;
        case 0xE8: mnem = "fsub"; break;
        case 0xC8: mnem = "fmul"; break;
        case 0xF8: mnem = "fdiv"; break;
        default: UnimplementedInstruction();
      }
      break;

    case 0xDD:
      has_register = true;
      switch (modrm_byte & 0xF8) {
        case 0xC0: mnem = "ffree"; break;
        case 0xD8: mnem = "fstp"; break;
        default: UnimplementedInstruction();
      }
      break;

    case 0xDE:
      if (modrm_byte  == 0xD9) {
        mnem = "fcompp";
      } else {
        has_register = true;
        switch (modrm_byte & 0xF8) {
          case 0xC0: mnem = "faddp"; break;
          case 0xE8: mnem = "fsubp"; break;
          case 0xC8: mnem = "fmulp"; break;
          case 0xF8: mnem = "fdivp"; break;
          default: UnimplementedInstruction();
        }
      }
      break;

    case 0xDF:
      if (modrm_byte == 0xE0) {
        mnem = "fnstsw_ax";
      } else if ((modrm_byte & 0xF8) == 0xE8) {
        mnem = "fucomip";
        has_register = true;
      }
      break;

    default: UnimplementedInstruction();
  }

  if (has_register) {
    AppendToBuffer("%s st%d", mnem, modrm_byte & 0x7);
  } else {
1626 1627 1628 1629 1630
    AppendToBuffer("%s", mnem);
  }
  return 2;
}

1631

1632

1633 1634 1635 1636 1637 1638 1639 1640
// Handle all two-byte opcodes, which start with 0x0F.
// These instructions may be affected by an 0x66, 0xF2, or 0xF3 prefix.
// We do not use any three-byte opcodes, which start with 0x0F38 or 0x0F3A.
int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) {
  byte opcode = *(data + 1);
  byte* current = data + 2;
  // At return, "current" points to the start of the next instruction.
  const char* mnemonic = TwoByteMnemonic(opcode);
1641 1642 1643
  if (operand_size_ == 0x66) {
    // 0x66 0x0F prefix.
    int mod, regop, rm;
1644 1645 1646
    if (opcode == 0x38) {
      byte third_byte = *current;
      current = data + 3;
1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660
      get_modrm(*current, &mod, &regop, &rm);
      switch (third_byte) {
#define SSE34_DIS_CASE(instruction, notUsed1, notUsed2, notUsed3, opcode) \
  case 0x##opcode: {                                                      \
    AppendToBuffer(#instruction " %s,", NameOfXMMRegister(regop));        \
    current += PrintRightXMMOperand(current);                             \
    break;                                                                \
  }

        SSSE3_INSTRUCTION_LIST(SSE34_DIS_CASE)
        SSE4_INSTRUCTION_LIST(SSE34_DIS_CASE)
#undef SSE34_DIS_CASE
        default:
          UnimplementedInstruction();
1661 1662
      }
    } else if (opcode == 0x3A) {
1663 1664 1665 1666 1667 1668
      byte third_byte = *current;
      current = data + 3;
      if (third_byte == 0x17) {
        get_modrm(*current, &mod, &regop, &rm);
        AppendToBuffer("extractps ");  // reg/m32, xmm, imm8
        current += PrintRightOperand(current);
1669
        AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), (*current) & 3);
1670
        current += 1;
1671
      } else if (third_byte == 0x0A) {
1672 1673 1674 1675 1676
        get_modrm(*current, &mod, &regop, &rm);
        AppendToBuffer("roundss %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",0x%x", (*current) & 3);
        current += 1;
1677
      } else if (third_byte == 0x0B) {
1678 1679
        get_modrm(*current, &mod, &regop, &rm);
         // roundsd xmm, xmm/m64, imm8
1680 1681
        AppendToBuffer("roundsd %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
1682
        AppendToBuffer(",0x%x", (*current) & 3);
1683
        current += 1;
1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695
      } else if (third_byte == 0x0E) {
        get_modrm(*current, &mod, &regop, &rm);
        AppendToBuffer("pblendw %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(data);
        AppendToBuffer(",0x%x", (*current) & 3);
        current += 1;
      } else if (third_byte == 0x0F) {
        get_modrm(*data, &mod, &regop, &rm);
        AppendToBuffer("palignr %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(data);
        AppendToBuffer(",0x%x", (*current) & 3);
        current += 1;
1696 1697 1698 1699 1700 1701 1702 1703 1704 1705
      } else if (third_byte == 0x14) {
        get_modrm(*current, &mod, &regop, &rm);
        AppendToBuffer("pextrb ");  // reg/m32, xmm, imm8
        current += PrintRightOperand(current);
        AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), (*current) & 3);
        current += 1;
      } else if (third_byte == 0x15) {
        get_modrm(*current, &mod, &regop, &rm);
        AppendToBuffer("pextrw ");  // reg/m32, xmm, imm8
        current += PrintRightOperand(current);
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        AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), (*current) & 7);
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        current += 1;
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      } else if (third_byte == 0x16) {
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        get_modrm(*current, &mod, &regop, &rm);
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        AppendToBuffer("pextrd ");  // reg/m32, xmm, imm8
        current += PrintRightOperand(current);
        AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), (*current) & 3);
        current += 1;
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      } else if (third_byte == 0x20) {
        get_modrm(*current, &mod, &regop, &rm);
        AppendToBuffer("pinsrd ");  // xmm, reg/m32, imm8
        AppendToBuffer(" %s,", NameOfXMMRegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%d", (*current) & 3);
        current += 1;
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      } else if (third_byte == 0x21) {
        get_modrm(*current, &mod, &regop, &rm);
        // insertps xmm, xmm/m32, imm8
        AppendToBuffer("insertps %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",0x%x", (*current) & 3);
        current += 1;
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      } else if (third_byte == 0x22) {
        get_modrm(*current, &mod, &regop, &rm);
        AppendToBuffer("pinsrd ");  // xmm, reg/m32, imm8
        AppendToBuffer(" %s,", NameOfXMMRegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%d", (*current) & 3);
        current += 1;
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      } else {
        UnimplementedInstruction();
      }
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    } else {
      get_modrm(*current, &mod, &regop, &rm);
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      if (opcode == 0x1F) {
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        current++;
        if (rm == 4) {  // SIB byte present.
          current++;
        }
        if (mod == 1) {  // Byte displacement.
          current += 1;
        } else if (mod == 2) {  // 32-bit displacement.
          current += 4;
        }  // else no immediate displacement.
        AppendToBuffer("nop");
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      } else if (opcode == 0x10) {
        AppendToBuffer("movupd %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
      } else if (opcode == 0x11) {
        AppendToBuffer("movupd ");
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
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      } else if (opcode == 0x28) {
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        AppendToBuffer("movapd %s,", NameOfXMMRegister(regop));
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        current += PrintRightXMMOperand(current);
      } else if (opcode == 0x29) {
        AppendToBuffer("movapd ");
        current += PrintRightXMMOperand(current);
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        AppendToBuffer(",%s", NameOfXMMRegister(regop));
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      } else if (opcode == 0x6E) {
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        AppendToBuffer("mov%c %s,",
                       rex_w() ? 'q' : 'd',
                       NameOfXMMRegister(regop));
        current += PrintRightOperand(current);
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      } else if (opcode == 0x6F) {
        AppendToBuffer("movdqa %s,",
                       NameOfXMMRegister(regop));
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        current += PrintRightXMMOperand(current);
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      } else if (opcode == 0x7E) {
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        AppendToBuffer("mov%c ",
                       rex_w() ? 'q' : 'd');
        current += PrintRightOperand(current);
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        AppendToBuffer(",%s", NameOfXMMRegister(regop));
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      } else if (opcode == 0x7F) {
        AppendToBuffer("movdqa ");
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        current += PrintRightXMMOperand(current);
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        AppendToBuffer(",%s", NameOfXMMRegister(regop));
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      } else if (opcode == 0xD6) {
        AppendToBuffer("movq ");
        current += PrintRightXMMOperand(current);
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        AppendToBuffer(",%s", NameOfXMMRegister(regop));
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      } else if (opcode == 0x50) {
        AppendToBuffer("movmskpd %s,", NameOfCPURegister(regop));
        current += PrintRightXMMOperand(current);
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      } else if (opcode == 0x70) {
        AppendToBuffer("pshufd %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",0x%x", *current);
        current += 1;
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      } else if (opcode == 0x71) {
        current += 1;
        AppendToBuffer("ps%sw %s,%d", sf_str[regop / 2], NameOfXMMRegister(rm),
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                       *current & 0x7F);
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        current += 1;
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      } else if (opcode == 0x72) {
        current += 1;
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        AppendToBuffer("ps%sd %s,%d", sf_str[regop / 2], NameOfXMMRegister(rm),
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                       *current & 0x7F);
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        current += 1;
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      } else if (opcode == 0x73) {
        current += 1;
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        AppendToBuffer("ps%sq %s,%d", sf_str[regop / 2], NameOfXMMRegister(rm),
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                       *current & 0x7F);
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        current += 1;
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      } else if (opcode == 0xB1) {
        current += PrintOperands("cmpxchg", OPER_REG_OP_ORDER, current);
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      } else if (opcode == 0xC4) {
        AppendToBuffer("pinsrw %s,", NameOfXMMRegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",0x%x", (*current) & 7);
        current += 1;
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      } else {
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        const char* mnemonic;
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        if (opcode == 0x54) {
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          mnemonic = "andpd";
        } else  if (opcode == 0x56) {
          mnemonic = "orpd";
        } else  if (opcode == 0x57) {
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          mnemonic = "xorpd";
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        } else if (opcode == 0x5B) {
          mnemonic = "cvtps2dq";
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        } else if (opcode == 0x60) {
          mnemonic = "punpcklbw";
        } else if (opcode == 0x61) {
          mnemonic = "punpcklwd";
        } else if (opcode == 0x62) {
          mnemonic = "punpckldq";
        } else if (opcode == 0x63) {
          mnemonic = "packsswb";
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        } else if (opcode == 0x64) {
          mnemonic = "pcmpgtb";
        } else if (opcode == 0x65) {
          mnemonic = "pcmpgtw";
        } else if (opcode == 0x66) {
          mnemonic = "pcmpgtd";
        } else if (opcode == 0x67) {
          mnemonic = "packuswb";
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        } else if (opcode == 0x68) {
          mnemonic = "punpckhbw";
        } else if (opcode == 0x69) {
          mnemonic = "punpckhwd";
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        } else if (opcode == 0x6A) {
          mnemonic = "punpckhdq";
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        } else if (opcode == 0x6B) {
          mnemonic = "packssdw";
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        } else if (opcode == 0x6C) {
          mnemonic = "punpcklqdq";
        } else if (opcode == 0x6D) {
          mnemonic = "punpckhqdq";
        } else if (opcode == 0x2E) {
          mnemonic = "ucomisd";
        } else if (opcode == 0x2F) {
          mnemonic = "comisd";
        } else if (opcode == 0x74) {
          mnemonic = "pcmpeqb";
        } else if (opcode == 0x75) {
          mnemonic = "pcmpeqw";
        } else if (opcode == 0x76) {
          mnemonic = "pcmpeqd";
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        } else if (opcode == 0xD1) {
          mnemonic = "psrlw";
        } else if (opcode == 0xD2) {
          mnemonic = "psrld";
        } else if (opcode == 0xD5) {
          mnemonic = "pmullw";
        } else if (opcode == 0xD7) {
          mnemonic = "pmovmskb";
        } else if (opcode == 0xD8) {
          mnemonic = "psubusb";
        } else if (opcode == 0xD9) {
          mnemonic = "psubusw";
        } else if (opcode == 0xDA) {
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          mnemonic = "pand";
        } else if (opcode == 0xDB) {
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          mnemonic = "pminub";
        } else if (opcode == 0xDC) {
          mnemonic = "paddusb";
        } else if (opcode == 0xDD) {
          mnemonic = "paddusw";
        } else if (opcode == 0xDE) {
          mnemonic = "pmaxub";
        } else if (opcode == 0xE1) {
          mnemonic = "psraw";
        } else if (opcode == 0xE2) {
          mnemonic = "psrad";
        } else if (opcode == 0xE8) {
          mnemonic = "psubsb";
        } else if (opcode == 0xE9) {
          mnemonic = "psubsw";
        } else if (opcode == 0xEA) {
          mnemonic = "pminsw";
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        } else if (opcode == 0xEB) {
          mnemonic = "por";
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        } else if (opcode == 0xEC) {
          mnemonic = "paddsb";
        } else if (opcode == 0xED) {
          mnemonic = "paddsw";
        } else if (opcode == 0xEE) {
          mnemonic = "pmaxsw";
        } else if (opcode == 0xEF) {
          mnemonic = "pxor";
        } else if (opcode == 0xF1) {
          mnemonic = "psllw";
        } else if (opcode == 0xF2) {
          mnemonic = "pslld";
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        } else if (opcode == 0xF4) {
          mnemonic = "pmuludq";
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        } else if (opcode == 0xF8) {
          mnemonic = "psubb";
        } else if (opcode == 0xF9) {
          mnemonic = "psubw";
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        } else if (opcode == 0xFA) {
          mnemonic = "psubd";
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        } else if (opcode == 0xFC) {
          mnemonic = "paddb";
        } else if (opcode == 0xFD) {
          mnemonic = "paddw";
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        } else if (opcode == 0xFE) {
          mnemonic = "paddd";
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        } else if (opcode == 0xC2) {
          mnemonic = "cmppd";
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        } else {
          UnimplementedInstruction();
        }
        AppendToBuffer("%s %s,", mnemonic, NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
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        if (opcode == 0xC2) {
          const char* const pseudo_op[] = {"eq",  "lt",  "le",  "unord",
                                           "neq", "nlt", "nle", "ord"};
          AppendToBuffer(", (%s)", pseudo_op[*current]);
          current += 1;
        }
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      }
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    }
  } else if (group_1_prefix_ == 0xF2) {
    // Beginning of instructions with prefix 0xF2.

    if (opcode == 0x11 || opcode == 0x10) {
      // MOVSD: Move scalar double-precision fp to/from/between XMM registers.
      AppendToBuffer("movsd ");
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      if (opcode == 0x11) {
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        current += PrintRightXMMOperand(current);
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        AppendToBuffer(",%s", NameOfXMMRegister(regop));
      } else {
        AppendToBuffer("%s,", NameOfXMMRegister(regop));
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        current += PrintRightXMMOperand(current);
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      }
    } else if (opcode == 0x2A) {
      // CVTSI2SD: integer to XMM double conversion.
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
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      AppendToBuffer("%s %s,", mnemonic, NameOfXMMRegister(regop));
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      current += PrintRightOperand(current);
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    } else if (opcode == 0x2C) {
      // CVTTSD2SI:
      // Convert with truncation scalar double-precision FP to integer.
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("cvttsd2si%c %s,",
          operand_size_code(), NameOfCPURegister(regop));
      current += PrintRightXMMOperand(current);
    } else if (opcode == 0x2D) {
      // CVTSD2SI: Convert scalar double-precision FP to integer.
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("cvtsd2si%c %s,",
          operand_size_code(), NameOfCPURegister(regop));
      current += PrintRightXMMOperand(current);
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    } else if (opcode == 0x5B) {
      // CVTTPS2DQ: Convert packed single-precision FP values to packed signed
      // doubleword integer values
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("cvttps2dq%c %s,", operand_size_code(),
                     NameOfCPURegister(regop));
      current += PrintRightXMMOperand(current);
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    } else if ((opcode & 0xF8) == 0x58 || opcode == 0x51) {
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      // XMM arithmetic. Mnemonic was retrieved at the start of this function.
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("%s %s,", mnemonic, NameOfXMMRegister(regop));
      current += PrintRightXMMOperand(current);
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    } else if (opcode == 0x70) {
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("pshuflw %s, ", NameOfXMMRegister(regop));
      current += PrintRightXMMOperand(current);
      AppendToBuffer(", %d", (*current) & 7);
      current += 1;
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    } else if (opcode == 0xC2) {
      // Intel manual 2A, Table 3-18.
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      const char* const pseudo_op[] = {
        "cmpeqsd",
        "cmpltsd",
        "cmplesd",
        "cmpunordsd",
        "cmpneqsd",
        "cmpnltsd",
        "cmpnlesd",
        "cmpordsd"
      };
      AppendToBuffer("%s %s,%s",
                     pseudo_op[current[1]],
                     NameOfXMMRegister(regop),
                     NameOfXMMRegister(rm));
      current += 2;
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    } else if (opcode == 0xF0) {
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("lddqu %s,", NameOfXMMRegister(regop));
      current += PrintRightOperand(current);
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    } else if (opcode == 0x7C) {
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("haddps %s,", NameOfXMMRegister(regop));
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      current += PrintRightXMMOperand(current);
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    } else {
      UnimplementedInstruction();
    }
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  } else if (group_1_prefix_ == 0xF3) {
    // Instructions with prefix 0xF3.
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    if (opcode == 0x11 || opcode == 0x10) {
      // MOVSS: Move scalar double-precision fp to/from/between XMM registers.
      AppendToBuffer("movss ");
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      if (opcode == 0x11) {
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
      } else {
        AppendToBuffer("%s,", NameOfXMMRegister(regop));
        current += PrintRightOperand(current);
      }
    } else if (opcode == 0x2A) {
      // CVTSI2SS: integer to XMM single conversion.
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
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      AppendToBuffer("%s %s,", mnemonic, NameOfXMMRegister(regop));
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      current += PrintRightOperand(current);
    } else if (opcode == 0x2C) {
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      // CVTTSS2SI:
      // Convert with truncation scalar single-precision FP to dword integer.
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      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("cvttss2si%c %s,",
          operand_size_code(), NameOfCPURegister(regop));
      current += PrintRightXMMOperand(current);
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    } else if (opcode == 0x70) {
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("pshufhw %s, ", NameOfXMMRegister(regop));
      current += PrintRightXMMOperand(current);
      AppendToBuffer(", %d", (*current) & 7);
      current += 1;
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    } else if (opcode == 0x6F) {
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("movdqu %s,", NameOfXMMRegister(regop));
      current += PrintRightXMMOperand(current);
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    } else if (opcode == 0x7E) {
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      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
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      AppendToBuffer("movq %s,", NameOfXMMRegister(regop));
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      current += PrintRightXMMOperand(current);
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    } else if (opcode == 0x7F) {
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("movdqu ");
      current += PrintRightXMMOperand(current);
      AppendToBuffer(",%s", NameOfXMMRegister(regop));
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    } else if ((opcode & 0xF8) == 0x58 || opcode == 0x51) {
      // XMM arithmetic. Mnemonic was retrieved at the start of this function.
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      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
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      AppendToBuffer("%s %s,", mnemonic, NameOfXMMRegister(regop));
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      current += PrintRightXMMOperand(current);
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    } else if (opcode == 0xB8) {
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("popcnt%c %s,", operand_size_code(),
                     NameOfCPURegister(regop));
      current += PrintRightOperand(current);
    } else if (opcode == 0xBC) {
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("tzcnt%c %s,", operand_size_code(),
                     NameOfCPURegister(regop));
      current += PrintRightOperand(current);
    } else if (opcode == 0xBD) {
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("lzcnt%c %s,", operand_size_code(),
                     NameOfCPURegister(regop));
      current += PrintRightOperand(current);
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    } else if (opcode == 0xC2) {
      // Intel manual 2A, Table 3-18.
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      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
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      const char* const pseudo_op[] = {"cmpeqss",    "cmpltss",  "cmpless",
                                       "cmpunordss", "cmpneqss", "cmpnltss",
                                       "cmpnless",   "cmpordss"};
      AppendToBuffer("%s %s,%s", pseudo_op[current[1]],
                     NameOfXMMRegister(regop), NameOfXMMRegister(rm));
      current += 2;
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    } else {
      UnimplementedInstruction();
    }
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  } else if (opcode == 0x10 || opcode == 0x11) {
    // movups xmm, xmm/m128
    // movups xmm/m128, xmm
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
    AppendToBuffer("movups ");
    if (opcode == 0x11) {
      current += PrintRightXMMOperand(current);
      AppendToBuffer(",%s", NameOfXMMRegister(regop));
    } else {
      AppendToBuffer("%s,", NameOfXMMRegister(regop));
      current += PrintRightXMMOperand(current);
    }
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  } else if (opcode == 0x1F) {
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    // NOP
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
    current++;
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    if (rm == 4) {  // SIB byte present.
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      current++;
    }
    if (mod == 1) {  // Byte displacement.
      current += 1;
    } else if (mod == 2) {  // 32-bit displacement.
      current += 4;
    }  // else no immediate displacement.
    AppendToBuffer("nop");
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  } else if (opcode == 0x28) {
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    // movaps xmm, xmm/m128
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
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    AppendToBuffer("movaps %s,", NameOfXMMRegister(regop));
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    current += PrintRightXMMOperand(current);

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  } else if (opcode == 0x29) {
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    // movaps xmm/m128, xmm
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
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    AppendToBuffer("movaps ");
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    current += PrintRightXMMOperand(current);
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    AppendToBuffer(",%s", NameOfXMMRegister(regop));
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  } else if (opcode == 0x2E) {
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    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
    AppendToBuffer("ucomiss %s,", NameOfXMMRegister(regop));
    current += PrintRightXMMOperand(current);
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  } else if (opcode == 0xA2) {
    // CPUID
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    AppendToBuffer("%s", mnemonic);
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  } else if ((opcode & 0xF0) == 0x40) {
    // CMOVcc: conditional move.
    int condition = opcode & 0x0F;
    const InstructionDesc& idesc = cmov_instructions[condition];
    byte_size_operand_ = idesc.byte_size_operation;
    current += PrintOperands(idesc.mnem, idesc.op_order_, current);

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  } else if (opcode >= 0x51 && opcode <= 0x5F) {
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    const char* const pseudo_op[] = {
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        "sqrtps",   "rsqrtps", "rcpps", "andps", "andnps",
        "orps",     "xorps",   "addps", "mulps", "cvtps2pd",
        "cvtdq2ps", "subps",   "minps", "divps", "maxps",
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    };
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    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
2183
    AppendToBuffer("%s %s,", pseudo_op[opcode - 0x51],
2184
                   NameOfXMMRegister(regop));
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    current += PrintRightXMMOperand(current);

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  } else if (opcode == 0xC2) {
    // cmpps xmm, xmm/m128, imm8
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
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    const char* const pseudo_op[] = {"eq",  "lt",  "le",  "unord",
                                     "neq", "nlt", "nle", "ord"};
    AppendToBuffer("cmpps %s, ", NameOfXMMRegister(regop));
    current += PrintRightXMMOperand(current);
    AppendToBuffer(", %s", pseudo_op[*current]);
    current += 1;
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  } else if (opcode == 0xC6) {
    // shufps xmm, xmm/m128, imm8
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    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
2201
    AppendToBuffer("shufps %s, ", NameOfXMMRegister(regop));
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    current += PrintRightXMMOperand(current);
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    AppendToBuffer(", %d", (*current) & 3);
    current += 1;
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  } else if (opcode >= 0xC8 && opcode <= 0xCF) {
    // bswap
    int reg = (opcode - 0xC8) | (rex_r() ? 8 : 0);
    AppendToBuffer("bswap%c %s", operand_size_code(), NameOfCPURegister(reg));
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  } else if (opcode == 0x50) {
    // movmskps reg, xmm
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
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    AppendToBuffer("movmskps %s,", NameOfCPURegister(regop));
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    current += PrintRightXMMOperand(current);
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  } else if (opcode == 0x70) {
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
    AppendToBuffer("pshufw %s, ", NameOfXMMRegister(regop));
    current += PrintRightXMMOperand(current);
    AppendToBuffer(", %d", (*current) & 3);
    current += 1;
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  } else if ((opcode & 0xF0) == 0x80) {
    // Jcc: Conditional jump (branch).
    current = data + JumpConditional(data);

  } else if (opcode == 0xBE || opcode == 0xBF || opcode == 0xB6 ||
             opcode == 0xB7 || opcode == 0xAF) {
    // Size-extending moves, IMUL.
    current += PrintOperands(mnemonic, REG_OPER_OP_ORDER, current);
  } else if ((opcode & 0xF0) == 0x90) {
    // SETcc: Set byte on condition. Needs pointer to beginning of instruction.
    current = data + SetCC(data);
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  } else if (opcode == 0xA3 || opcode == 0xA5 || opcode == 0xAB ||
             opcode == 0xAD) {
    // BT (bit test), SHLD, BTS (bit test and set),
    // SHRD (double-precision shift)
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    AppendToBuffer("%s ", mnemonic);
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
    current += PrintRightOperand(current);
    if (opcode == 0xAB) {
      AppendToBuffer(",%s", NameOfCPURegister(regop));
    } else {
      AppendToBuffer(",%s,cl", NameOfCPURegister(regop));
    }
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  } else if (opcode == 0xBA) {
    // BTS / BTR (bit test and set/reset) with immediate
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
    mnemonic = regop == 5 ? "bts" : regop == 6 ? "btr" : "?";
    AppendToBuffer("%s ", mnemonic);
    current += PrintRightOperand(current);
    AppendToBuffer(",%d", *current++);
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  } else if (opcode == 0xB8 || opcode == 0xBC || opcode == 0xBD) {
    // POPCNT, CTZ, CLZ.
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    AppendToBuffer("%s%c ", mnemonic, operand_size_code());
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
    AppendToBuffer("%s,", NameOfCPURegister(regop));
    current += PrintRightOperand(current);
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  } else if (opcode == 0x0B) {
    AppendToBuffer("ud2");
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  } else if (opcode == 0xB0 || opcode == 0xB1) {
    // CMPXCHG.
    if (opcode == 0xB0) {
      byte_size_operand_ = true;
    }
    current += PrintOperands(mnemonic, OPER_REG_OP_ORDER, current);
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  } else if (opcode == 0xAE && (*(data + 2) & 0xF8) == 0xE8) {
    AppendToBuffer("lfence");
    current = data + 3;
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  } else {
    UnimplementedInstruction();
  }
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  return static_cast<int>(current - data);
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}

// Mnemonics for two-byte opcode instructions starting with 0x0F.
// The argument is the second byte of the two-byte opcode.
2280
// Returns nullptr if the instruction is not handled here.
2281
const char* DisassemblerX64::TwoByteMnemonic(byte opcode) {
2282
  if (opcode >= 0xC8 && opcode <= 0xCF) return "bswap";
2283
  switch (opcode) {
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    case 0x1F:
      return "nop";
2286
    case 0x2A:  // F2/F3 prefix.
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      return (group_1_prefix_ == 0xF2) ? "cvtsi2sd" : "cvtsi2ss";
    case 0x51:  // F2/F3 prefix.
      return (group_1_prefix_ == 0xF2) ? "sqrtsd" : "sqrtss";
    case 0x58:  // F2/F3 prefix.
      return (group_1_prefix_ == 0xF2) ? "addsd" : "addss";
    case 0x59:  // F2/F3 prefix.
      return (group_1_prefix_ == 0xF2) ? "mulsd" : "mulss";
    case 0x5A:  // F2/F3 prefix.
      return (group_1_prefix_ == 0xF2) ? "cvtsd2ss" : "cvtss2sd";
    case 0x5D:  // F2/F3 prefix.
      return (group_1_prefix_ == 0xF2) ? "minsd" : "minss";
    case 0x5C:  // F2/F3 prefix.
      return (group_1_prefix_ == 0xF2) ? "subsd" : "subss";
    case 0x5E:  // F2/F3 prefix.
      return (group_1_prefix_ == 0xF2) ? "divsd" : "divss";
    case 0x5F:  // F2/F3 prefix.
      return (group_1_prefix_ == 0xF2) ? "maxsd" : "maxss";
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    case 0xA2:
      return "cpuid";
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    case 0xA3:
      return "bt";
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    case 0xA5:
      return "shld";
    case 0xAB:
      return "bts";
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    case 0xAD:
      return "shrd";
    case 0xAF:
      return "imul";
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    case 0xB0:
    case 0xB1:
      return "cmpxchg";
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    case 0xB6:
      return "movzxb";
    case 0xB7:
      return "movzxw";
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    case 0xBC:
      return "bsf";
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    case 0xBD:
      return "bsr";
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    case 0xBE:
      return "movsxb";
    case 0xBF:
      return "movsxw";
2331
    default:
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      return nullptr;
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  }
}

2336 2337

// Disassembles the instruction at instr, and writes it into out_buffer.
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int DisassemblerX64::InstructionDecode(v8::internal::Vector<char> out_buffer,
                                       byte* instr) {
  tmp_buffer_pos_ = 0;  // starting to write as position 0
  byte* data = instr;
  bool processed = true;  // Will be set to false if the current instruction
                          // is not in 'instructions' table.
  byte current;

  // Scan for prefixes.
  while (true) {
    current = *data;
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    if (current == OPERAND_SIZE_OVERRIDE_PREFIX) {  // Group 3 prefix.
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      operand_size_ = current;
    } else if ((current & 0xF0) == 0x40) {  // REX prefix.
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      setRex(current);
      if (rex_w()) AppendToBuffer("REX.W ");
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    } else if ((current & 0xFE) == 0xF2) {  // Group 1 prefix (0xF2 or 0xF3).
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      group_1_prefix_ = current;
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    } else if (current == LOCK_PREFIX) {
      AppendToBuffer("lock ");
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    } else if (current == VEX3_PREFIX) {
      vex_byte0_ = current;
      vex_byte1_ = *(data + 1);
      vex_byte2_ = *(data + 2);
      setRex(0x40 | (~(vex_byte1_ >> 5) & 7) | ((vex_byte2_ >> 4) & 8));
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      data += 3;
      break;  // Vex is the last prefix.
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    } else if (current == VEX2_PREFIX) {
      vex_byte0_ = current;
      vex_byte1_ = *(data + 1);
      setRex(0x40 | (~(vex_byte1_ >> 5) & 4));
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      data += 2;
      break;  // Vex is the last prefix.
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    } else {  // Not a prefix - an opcode.
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      break;
    }
2374
    data++;
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  }

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  // Decode AVX instructions.
  if (vex_byte0_ != 0) {
    processed = true;
    data += AVXInstruction(data);
  } else {
    const InstructionDesc& idesc = instruction_table_->Get(current);
    byte_size_operand_ = idesc.byte_size_operation;
    switch (idesc.type) {
      case ZERO_OPERANDS_INSTR:
        if (current >= 0xA4 && current <= 0xA7) {
          // String move or compare operations.
          if (group_1_prefix_ == REP_PREFIX) {
            // REP.
            AppendToBuffer("rep ");
          }
          if (rex_w()) AppendToBuffer("REX.W ");
          AppendToBuffer("%s%c", idesc.mnem, operand_size_code());
        } else {
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          AppendToBuffer("%s%c", idesc.mnem, operand_size_code());
2396
        }
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        data++;
        break;
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      case TWO_OPERANDS_INSTR:
        data++;
        data += PrintOperands(idesc.mnem, idesc.op_order_, data);
        break;
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      case JUMP_CONDITIONAL_SHORT_INSTR:
        data += JumpConditionalShort(data);
        break;
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      case REGISTER_INSTR:
        AppendToBuffer("%s%c %s", idesc.mnem, operand_size_code(),
                       NameOfCPURegister(base_reg(current & 0x07)));
        data++;
        break;
      case PUSHPOP_INSTR:
        AppendToBuffer("%s %s", idesc.mnem,
                       NameOfCPURegister(base_reg(current & 0x07)));
        data++;
        break;
      case MOVE_REG_INSTR: {
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        byte* addr = nullptr;
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        switch (operand_size()) {
          case OPERAND_WORD_SIZE:
            addr =
                reinterpret_cast<byte*>(*reinterpret_cast<int16_t*>(data + 1));
            data += 3;
            break;
          case OPERAND_DOUBLEWORD_SIZE:
            addr =
                reinterpret_cast<byte*>(*reinterpret_cast<uint32_t*>(data + 1));
            data += 5;
            break;
          case OPERAND_QUADWORD_SIZE:
            addr =
                reinterpret_cast<byte*>(*reinterpret_cast<int64_t*>(data + 1));
            data += 9;
            break;
          default:
            UNREACHABLE();
        }
        AppendToBuffer("mov%c %s,%s", operand_size_code(),
                       NameOfCPURegister(base_reg(current & 0x07)),
                       NameOfAddress(addr));
        break;
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      }

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      case CALL_JUMP_INSTR: {
        byte* addr = data + *reinterpret_cast<int32_t*>(data + 1) + 5;
        AppendToBuffer("%s %s", idesc.mnem, NameOfAddress(addr));
        data += 5;
        break;
      }
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2453
      case SHORT_IMMEDIATE_INSTR: {
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        int32_t imm;
        if (operand_size() == OPERAND_WORD_SIZE) {
          imm = *reinterpret_cast<int16_t*>(data + 1);
          data += 3;
        } else {
          imm = *reinterpret_cast<int32_t*>(data + 1);
          data += 5;
        }
        AppendToBuffer("%s rax,0x%x", idesc.mnem, imm);
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        break;
      }
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      case NO_INSTR:
        processed = false;
        break;
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      default:
        UNIMPLEMENTED();  // This type is not implemented.
    }
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  }

  // The first byte didn't match any of the simple opcodes, so we
  // need to do special processing on it.
  if (!processed) {
    switch (*data) {
      case 0xC2:
        AppendToBuffer("ret 0x%x", *reinterpret_cast<uint16_t*>(data + 1));
        data += 3;
        break;

      case 0x69:  // fall through
      case 0x6B: {
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        int count = 1;
        count += PrintOperands("imul", REG_OPER_OP_ORDER, data + count);
        AppendToBuffer(",0x");
        if (*data == 0x69) {
          count += PrintImmediate(data + count, operand_size());
        } else {
          count += PrintImmediate(data + count, OPERAND_BYTE_SIZE);
        }
        data += count;
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        break;
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      }
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      case 0x81:  // fall through
      case 0x83:  // 0x81 with sign extension bit set
        data += PrintImmediateOp(data);
        break;

2503 2504
      case 0x0F:
        data += TwoByteOpcodeInstruction(data);
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        break;

      case 0x8F: {
        data++;
        int mod, regop, rm;
        get_modrm(*data, &mod, &regop, &rm);
        if (regop == 0) {
          AppendToBuffer("pop ");
          data += PrintRightOperand(data);
        }
      }
        break;

      case 0xFF: {
        data++;
        int mod, regop, rm;
        get_modrm(*data, &mod, &regop, &rm);
2522
        const char* mnem = nullptr;
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        switch (regop) {
          case 0:
            mnem = "inc";
            break;
          case 1:
            mnem = "dec";
            break;
          case 2:
            mnem = "call";
            break;
          case 4:
            mnem = "jmp";
            break;
          case 6:
            mnem = "push";
            break;
          default:
            mnem = "???";
        }
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        if (regop <= 1) {
          AppendToBuffer("%s%c ", mnem, operand_size_code());
        } else {
          AppendToBuffer("%s ", mnem);
        }
2547 2548 2549 2550 2551 2552 2553 2554 2555
        data += PrintRightOperand(data);
      }
        break;

      case 0xC7:  // imm32, fall through
      case 0xC6:  // imm8
      {
        bool is_byte = *data == 0xC6;
        data++;
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        if (is_byte) {
          AppendToBuffer("movb ");
          data += PrintRightByteOperand(data);
          int32_t imm = *data;
          AppendToBuffer(",0x%x", imm);
          data++;
        } else {
          AppendToBuffer("mov%c ", operand_size_code());
          data += PrintRightOperand(data);
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          if (operand_size() == OPERAND_WORD_SIZE) {
            int16_t imm = *reinterpret_cast<int16_t*>(data);
            AppendToBuffer(",0x%x", imm);
            data += 2;
          } else {
            int32_t imm = *reinterpret_cast<int32_t*>(data);
            AppendToBuffer(",0x%x", imm);
            data += 4;
          }
2574
        }
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      }
        break;

      case 0x80: {
        data++;
        AppendToBuffer("cmpb ");
2581
        data += PrintRightByteOperand(data);
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        int32_t imm = *data;
        AppendToBuffer(",0x%x", imm);
        data++;
      }
        break;

      case 0x88:  // 8bit, fall through
      case 0x89:  // 32bit
      {
        bool is_byte = *data == 0x88;
        int mod, regop, rm;
        data++;
        get_modrm(*data, &mod, &regop, &rm);
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        if (is_byte) {
          AppendToBuffer("movb ");
          data += PrintRightByteOperand(data);
          AppendToBuffer(",%s", NameOfByteCPURegister(regop));
        } else {
          AppendToBuffer("mov%c ", operand_size_code());
          data += PrintRightOperand(data);
          AppendToBuffer(",%s", NameOfCPURegister(regop));
        }
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      }
        break;

      case 0x90:
      case 0x91:
      case 0x92:
      case 0x93:
      case 0x94:
      case 0x95:
      case 0x96:
      case 0x97: {
2615
        int reg = (*data & 0x7) | (rex_b() ? 8 : 0);
2616 2617 2618
        if (group_1_prefix_ == 0xF3 && *data == 0x90) {
          AppendToBuffer("pause");
        } else if (reg == 0) {
2619 2620
          AppendToBuffer("nop");  // Common name for xchg rax,rax.
        } else {
2621
          AppendToBuffer("xchg%c rax,%s",
2622
                         operand_size_code(),
2623
                         NameOfCPURegister(reg));
2624
        }
2625
        data++;
2626
      }
2627
        break;
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      case 0xB0:
      case 0xB1:
      case 0xB2:
      case 0xB3:
      case 0xB4:
      case 0xB5:
      case 0xB6:
      case 0xB7:
      case 0xB8:
      case 0xB9:
      case 0xBA:
      case 0xBB:
      case 0xBC:
      case 0xBD:
      case 0xBE:
      case 0xBF: {
        // mov reg8,imm8 or mov reg32,imm32
        byte opcode = *data;
        data++;
        bool is_32bit = (opcode >= 0xB8);
        int reg = (opcode & 0x7) | (rex_b() ? 8 : 0);
        if (is_32bit) {
2650
          AppendToBuffer("mov%c %s,",
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                         operand_size_code(),
                         NameOfCPURegister(reg));
2653
          data += PrintImmediate(data, OPERAND_DOUBLEWORD_SIZE);
2654
        } else {
2655
          AppendToBuffer("movb %s,",
2656
                         NameOfByteCPURegister(reg));
2657
          data += PrintImmediate(data, OPERAND_BYTE_SIZE);
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        }
        break;
      }
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      case 0xFE: {
        data++;
        int mod, regop, rm;
        get_modrm(*data, &mod, &regop, &rm);
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        if (regop == 1) {
          AppendToBuffer("decb ");
2667
          data += PrintRightByteOperand(data);
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        } else {
          UnimplementedInstruction();
        }
        break;
2672
      }
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      case 0x68:
        AppendToBuffer("push 0x%x", *reinterpret_cast<int32_t*>(data + 1));
        data += 5;
        break;

      case 0x6A:
        AppendToBuffer("push 0x%x", *reinterpret_cast<int8_t*>(data + 1));
        data += 2;
        break;

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      case 0xA1:  // Fall through.
      case 0xA3:
        switch (operand_size()) {
2686
          case OPERAND_DOUBLEWORD_SIZE: {
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            const char* memory_location = NameOfAddress(
                reinterpret_cast<byte*>(
                    *reinterpret_cast<int32_t*>(data + 1)));
2690
            if (*data == 0xA1) {  // Opcode 0xA1
2691
              AppendToBuffer("movzxlq rax,(%s)", memory_location);
2692
            } else {  // Opcode 0xA3
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              AppendToBuffer("movzxlq (%s),rax", memory_location);
            }
            data += 5;
            break;
          }
2698
          case OPERAND_QUADWORD_SIZE: {
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            // New x64 instruction mov rax,(imm_64).
            const char* memory_location = NameOfAddress(
                *reinterpret_cast<byte**>(data + 1));
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            if (*data == 0xA1) {  // Opcode 0xA1
2703
              AppendToBuffer("movq rax,(%s)", memory_location);
2704
            } else {  // Opcode 0xA3
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              AppendToBuffer("movq (%s),rax", memory_location);
            }
            data += 9;
            break;
          }
          default:
            UnimplementedInstruction();
            data += 2;
        }
        break;

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      case 0xA8:
        AppendToBuffer("test al,0x%x", *reinterpret_cast<uint8_t*>(data + 1));
        data += 2;
        break;

2721
      case 0xA9: {
2722
        int64_t value = 0;
2723
        switch (operand_size()) {
2724
          case OPERAND_WORD_SIZE:
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            value = *reinterpret_cast<uint16_t*>(data + 1);
            data += 3;
            break;
2728
          case OPERAND_DOUBLEWORD_SIZE:
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            value = *reinterpret_cast<uint32_t*>(data + 1);
            data += 5;
            break;
2732
          case OPERAND_QUADWORD_SIZE:
2733 2734 2735 2736 2737 2738
            value = *reinterpret_cast<int32_t*>(data + 1);
            data += 5;
            break;
          default:
            UNREACHABLE();
        }
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        AppendToBuffer("test%c rax,0x%" PRIx64, operand_size_code(), value);
2740
        break;
2741
      }
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      case 0xD1:  // fall through
      case 0xD3:  // fall through
      case 0xC1:
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        data += ShiftInstruction(data);
        break;
      case 0xD0:  // fall through
      case 0xD2:  // fall through
      case 0xC0:
        byte_size_operand_ = true;
        data += ShiftInstruction(data);
2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767
        break;

      case 0xD9:  // fall through
      case 0xDA:  // fall through
      case 0xDB:  // fall through
      case 0xDC:  // fall through
      case 0xDD:  // fall through
      case 0xDE:  // fall through
      case 0xDF:
        data += FPUInstruction(data);
        break;

      case 0xEB:
        data += JumpShort(data);
        break;

2768
      case 0xF6:
2769 2770
        byte_size_operand_ = true;
        V8_FALLTHROUGH;
2771
      case 0xF7:
2772
        data += F6F7Instruction(data);
2773 2774
        break;

2775
      case 0x3C:
2776
        AppendToBuffer("cmp al,0x%x", *reinterpret_cast<int8_t*>(data + 1));
2777 2778 2779
        data +=2;
        break;

2780 2781
      default:
        UnimplementedInstruction();
2782
        data += 1;
2783 2784 2785 2786 2787 2788 2789
    }
  }  // !processed

  if (tmp_buffer_pos_ < sizeof tmp_buffer_) {
    tmp_buffer_[tmp_buffer_pos_] = '\0';
  }

2790
  int instr_len = static_cast<int>(data - instr);
2791
  DCHECK_GT(instr_len, 0);  // Ensure progress.
2792 2793 2794 2795

  int outp = 0;
  // Instruction bytes.
  for (byte* bp = instr; bp < data; bp++) {
2796
    outp += v8::internal::SNPrintF(out_buffer + outp, "%02x", *bp);
2797 2798
  }
  for (int i = 6 - instr_len; i >= 0; i--) {
2799
    outp += v8::internal::SNPrintF(out_buffer + outp, "  ");
2800 2801
  }

2802 2803
  outp += v8::internal::SNPrintF(out_buffer + outp, " %s",
                                 tmp_buffer_.start());
2804 2805 2806
  return instr_len;
}

2807

2808 2809 2810
//------------------------------------------------------------------------------


2811
static const char* const cpu_regs[16] = {
2812 2813 2814 2815 2816
  "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
};


2817
static const char* const byte_cpu_regs[16] = {
2818 2819 2820 2821 2822
  "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
  "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l"
};


2823
static const char* const xmm_regs[16] = {
2824 2825 2826 2827 2828 2829
  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
};


const char* NameConverter::NameOfAddress(byte* addr) const {
2830
  v8::internal::SNPrintF(tmp_buffer_, "%p", static_cast<void*>(addr));
2831
  return tmp_buffer_.start();
2832 2833 2834 2835 2836
}


const char* NameConverter::NameOfConstant(byte* addr) const {
  return NameOfAddress(addr);
2837
}
2838 2839


2840
const char* NameConverter::NameOfCPURegister(int reg) const {
2841 2842 2843
  if (0 <= reg && reg < 16)
    return cpu_regs[reg];
  return "noreg";
2844
}
2845 2846


2847 2848 2849 2850
const char* NameConverter::NameOfByteCPURegister(int reg) const {
  if (0 <= reg && reg < 16)
    return byte_cpu_regs[reg];
  return "noreg";
2851
}
2852 2853


2854 2855 2856 2857
const char* NameConverter::NameOfXMMRegister(int reg) const {
  if (0 <= reg && reg < 16)
    return xmm_regs[reg];
  return "noxmmreg";
2858
}
2859

2860 2861 2862 2863

const char* NameConverter::NameInCode(byte* addr) const {
  // X64 does not embed debug strings at the moment.
  UNREACHABLE();
2864 2865
}

2866

2867 2868 2869 2870
//------------------------------------------------------------------------------

int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
                                    byte* instruction) {
2871
  DisassemblerX64 d(converter_, unimplemented_opcode_action());
2872 2873
  return d.InstructionDecode(buffer, instruction);
}
2874 2875 2876 2877

// The X64 assembler does not use constant pools.
int Disassembler::ConstantPoolSizeAt(byte* instruction) {
  return -1;
2878 2879
}

2880 2881
void Disassembler::Disassemble(FILE* f, byte* begin, byte* end,
                               UnimplementedOpcodeAction unimplemented_action) {
2882
  NameConverter converter;
2883
  Disassembler d(converter, unimplemented_action);
2884 2885 2886 2887 2888
  for (byte* pc = begin; pc < end;) {
    v8::internal::EmbeddedVector<char, 128> buffer;
    buffer[0] = '\0';
    byte* prev_pc = pc;
    pc += d.InstructionDecode(buffer, pc);
2889
    fprintf(f, "%p", static_cast<void*>(prev_pc));
2890 2891 2892 2893 2894
    fprintf(f, "    ");

    for (byte* bp = prev_pc; bp < pc; bp++) {
      fprintf(f, "%02x", *bp);
    }
2895
    for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) {
2896 2897 2898 2899
      fprintf(f, "  ");
    }
    fprintf(f, "  %s\n", buffer.start());
  }
2900
}
2901 2902

}  // namespace disasm
2903 2904

#endif  // V8_TARGET_ARCH_X64