instruction-selector-ppc.cc 66.9 KB
Newer Older
1 2 3 4
// Copyright 2014 the V8 project authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.

5
#include "src/base/adapters.h"
6 7 8
#include "src/compiler/instruction-selector-impl.h"
#include "src/compiler/node-matchers.h"
#include "src/compiler/node-properties.h"
9
#include "src/ppc/frames-ppc.h"
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

namespace v8 {
namespace internal {
namespace compiler {

enum ImmediateMode {
  kInt16Imm,
  kInt16Imm_Unsigned,
  kInt16Imm_Negate,
  kInt16Imm_4ByteAligned,
  kShift32Imm,
  kShift64Imm,
  kNoImmediate
};


// Adds PPC-specific methods for generating operands.
27
class PPCOperandGenerator final : public OperandGenerator {
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71
 public:
  explicit PPCOperandGenerator(InstructionSelector* selector)
      : OperandGenerator(selector) {}

  InstructionOperand UseOperand(Node* node, ImmediateMode mode) {
    if (CanBeImmediate(node, mode)) {
      return UseImmediate(node);
    }
    return UseRegister(node);
  }

  bool CanBeImmediate(Node* node, ImmediateMode mode) {
    int64_t value;
    if (node->opcode() == IrOpcode::kInt32Constant)
      value = OpParameter<int32_t>(node);
    else if (node->opcode() == IrOpcode::kInt64Constant)
      value = OpParameter<int64_t>(node);
    else
      return false;
    return CanBeImmediate(value, mode);
  }

  bool CanBeImmediate(int64_t value, ImmediateMode mode) {
    switch (mode) {
      case kInt16Imm:
        return is_int16(value);
      case kInt16Imm_Unsigned:
        return is_uint16(value);
      case kInt16Imm_Negate:
        return is_int16(-value);
      case kInt16Imm_4ByteAligned:
        return is_int16(value) && !(value & 3);
      case kShift32Imm:
        return 0 <= value && value < 32;
      case kShift64Imm:
        return 0 <= value && value < 64;
      case kNoImmediate:
        return false;
    }
    return false;
  }
};


72
namespace {
73

74 75
void VisitRR(InstructionSelector* selector, InstructionCode opcode,
             Node* node) {
76 77
  PPCOperandGenerator g(selector);
  selector->Emit(opcode, g.DefineAsRegister(node),
78
                 g.UseRegister(node->InputAt(0)));
79 80
}

81 82
void VisitRRR(InstructionSelector* selector, InstructionCode opcode,
              Node* node) {
83 84 85 86 87 88
  PPCOperandGenerator g(selector);
  selector->Emit(opcode, g.DefineAsRegister(node),
                 g.UseRegister(node->InputAt(0)),
                 g.UseRegister(node->InputAt(1)));
}

89
void VisitRRO(InstructionSelector* selector, InstructionCode opcode, Node* node,
90
              ImmediateMode operand_mode) {
91 92 93 94 95 96 97
  PPCOperandGenerator g(selector);
  selector->Emit(opcode, g.DefineAsRegister(node),
                 g.UseRegister(node->InputAt(0)),
                 g.UseOperand(node->InputAt(1), operand_mode));
}


98
#if V8_TARGET_ARCH_PPC64
99 100
void VisitTryTruncateDouble(InstructionSelector* selector,
                            InstructionCode opcode, Node* node) {
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116
  PPCOperandGenerator g(selector);
  InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0))};
  InstructionOperand outputs[2];
  size_t output_count = 0;
  outputs[output_count++] = g.DefineAsRegister(node);

  Node* success_output = NodeProperties::FindProjection(node, 1);
  if (success_output) {
    outputs[output_count++] = g.DefineAsRegister(success_output);
  }

  selector->Emit(opcode, output_count, outputs, 1, inputs);
}
#endif


117 118
// Shared routine for multiple binary operations.
template <typename Matcher>
119 120 121
void VisitBinop(InstructionSelector* selector, Node* node,
                InstructionCode opcode, ImmediateMode operand_mode,
                FlagsContinuation* cont) {
122 123 124 125 126 127 128 129 130 131 132 133 134 135 136
  PPCOperandGenerator g(selector);
  Matcher m(node);
  InstructionOperand inputs[4];
  size_t input_count = 0;
  InstructionOperand outputs[2];
  size_t output_count = 0;

  inputs[input_count++] = g.UseRegister(m.left().node());
  inputs[input_count++] = g.UseOperand(m.right().node(), operand_mode);

  if (cont->IsBranch()) {
    inputs[input_count++] = g.Label(cont->true_block());
    inputs[input_count++] = g.Label(cont->false_block());
  }

137 138 139 140 141 142 143 144
  if (cont->IsDeoptimize()) {
    // If we can deoptimize as a result of the binop, we need to make sure that
    // the deopt inputs are not overwritten by the binop result. One way
    // to achieve that is to declare the output register as same-as-first.
    outputs[output_count++] = g.DefineSameAsFirst(node);
  } else {
    outputs[output_count++] = g.DefineAsRegister(node);
  }
145 146 147 148 149 150 151 152 153
  if (cont->IsSet()) {
    outputs[output_count++] = g.DefineAsRegister(cont->result());
  }

  DCHECK_NE(0u, input_count);
  DCHECK_NE(0u, output_count);
  DCHECK_GE(arraysize(inputs), input_count);
  DCHECK_GE(arraysize(outputs), output_count);

154 155 156
  opcode = cont->Encode(opcode);
  if (cont->IsDeoptimize()) {
    selector->EmitDeoptimize(opcode, output_count, outputs, input_count, inputs,
157
                             cont->reason(), cont->frame_state());
158 159 160
  } else {
    selector->Emit(opcode, output_count, outputs, input_count, inputs);
  }
161 162 163 164 165
}


// Shared routine for multiple binary operations.
template <typename Matcher>
166 167
void VisitBinop(InstructionSelector* selector, Node* node,
                InstructionCode opcode, ImmediateMode operand_mode) {
168 169 170 171
  FlagsContinuation cont;
  VisitBinop<Matcher>(selector, node, opcode, operand_mode, &cont);
}

172 173
}  // namespace

174 175

void InstructionSelector::VisitLoad(Node* node) {
176
  LoadRepresentation load_rep = LoadRepresentationOf(node->op());
177 178 179
  PPCOperandGenerator g(this);
  Node* base = node->InputAt(0);
  Node* offset = node->InputAt(1);
180
  ArchOpcode opcode = kArchNop;
181
  ImmediateMode mode = kInt16Imm;
182 183
  switch (load_rep.representation()) {
    case MachineRepresentation::kFloat32:
184 185
      opcode = kPPC_LoadFloat32;
      break;
186
    case MachineRepresentation::kFloat64:
187
      opcode = kPPC_LoadDouble;
188
      break;
189 190 191
    case MachineRepresentation::kBit:  // Fall through.
    case MachineRepresentation::kWord8:
      opcode = load_rep.IsSigned() ? kPPC_LoadWordS8 : kPPC_LoadWordU8;
192
      break;
193 194
    case MachineRepresentation::kWord16:
      opcode = load_rep.IsSigned() ? kPPC_LoadWordS16 : kPPC_LoadWordU16;
195 196
      break;
#if !V8_TARGET_ARCH_PPC64
197 198
    case MachineRepresentation::kTaggedSigned:   // Fall through.
    case MachineRepresentation::kTaggedPointer:  // Fall through.
199
    case MachineRepresentation::kTagged:  // Fall through.
200
#endif
201
    case MachineRepresentation::kWord32:
202
      opcode = kPPC_LoadWordU32;
203 204
      break;
#if V8_TARGET_ARCH_PPC64
205 206
    case MachineRepresentation::kTaggedSigned:   // Fall through.
    case MachineRepresentation::kTaggedPointer:  // Fall through.
207 208
    case MachineRepresentation::kTagged:  // Fall through.
    case MachineRepresentation::kWord64:
209 210 211
      opcode = kPPC_LoadWord64;
      mode = kInt16Imm_4ByteAligned;
      break;
212 213
#else
    case MachineRepresentation::kWord64:  // Fall through.
214
#endif
215
    case MachineRepresentation::kSimd128:  // Fall through.
216
    case MachineRepresentation::kNone:
217 218 219 220 221 222 223 224 225 226 227 228 229 230 231
      UNREACHABLE();
      return;
  }
  if (g.CanBeImmediate(offset, mode)) {
    Emit(opcode | AddressingModeField::encode(kMode_MRI),
         g.DefineAsRegister(node), g.UseRegister(base), g.UseImmediate(offset));
  } else if (g.CanBeImmediate(base, mode)) {
    Emit(opcode | AddressingModeField::encode(kMode_MRI),
         g.DefineAsRegister(node), g.UseRegister(offset), g.UseImmediate(base));
  } else {
    Emit(opcode | AddressingModeField::encode(kMode_MRR),
         g.DefineAsRegister(node), g.UseRegister(base), g.UseRegister(offset));
  }
}

232 233 234 235
void InstructionSelector::VisitProtectedLoad(Node* node) {
  // TODO(eholk)
  UNIMPLEMENTED();
}
236 237 238 239 240 241 242

void InstructionSelector::VisitStore(Node* node) {
  PPCOperandGenerator g(this);
  Node* base = node->InputAt(0);
  Node* offset = node->InputAt(1);
  Node* value = node->InputAt(2);

243
  StoreRepresentation store_rep = StoreRepresentationOf(node->op());
244
  WriteBarrierKind write_barrier_kind = store_rep.write_barrier_kind();
245
  MachineRepresentation rep = store_rep.representation();
246 247

  if (write_barrier_kind != kNoWriteBarrier) {
248
    DCHECK_EQ(MachineRepresentation::kTagged, rep);
249
    AddressingMode addressing_mode;
250 251 252
    InstructionOperand inputs[3];
    size_t input_count = 0;
    inputs[input_count++] = g.UseUniqueRegister(base);
253 254 255 256 257 258 259 260 261 262 263 264 265
    // OutOfLineRecordWrite uses the offset in an 'add' instruction as well as
    // for the store itself, so we must check compatibility with both.
    if (g.CanBeImmediate(offset, kInt16Imm)
#if V8_TARGET_ARCH_PPC64
        && g.CanBeImmediate(offset, kInt16Imm_4ByteAligned)
#endif
            ) {
      inputs[input_count++] = g.UseImmediate(offset);
      addressing_mode = kMode_MRI;
    } else {
      inputs[input_count++] = g.UseUniqueRegister(offset);
      addressing_mode = kMode_MRR;
    }
266
    inputs[input_count++] = g.UseUniqueRegister(value);
267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284
    RecordWriteMode record_write_mode = RecordWriteMode::kValueIsAny;
    switch (write_barrier_kind) {
      case kNoWriteBarrier:
        UNREACHABLE();
        break;
      case kMapWriteBarrier:
        record_write_mode = RecordWriteMode::kValueIsMap;
        break;
      case kPointerWriteBarrier:
        record_write_mode = RecordWriteMode::kValueIsPointer;
        break;
      case kFullWriteBarrier:
        record_write_mode = RecordWriteMode::kValueIsAny;
        break;
    }
    InstructionOperand temps[] = {g.TempRegister(), g.TempRegister()};
    size_t const temp_count = arraysize(temps);
    InstructionCode code = kArchStoreWithWriteBarrier;
285
    code |= AddressingModeField::encode(addressing_mode);
286 287 288
    code |= MiscField::encode(static_cast<int>(record_write_mode));
    Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
  } else {
289
    ArchOpcode opcode = kArchNop;
290 291
    ImmediateMode mode = kInt16Imm;
    switch (rep) {
292
      case MachineRepresentation::kFloat32:
293 294
        opcode = kPPC_StoreFloat32;
        break;
295
      case MachineRepresentation::kFloat64:
296 297
        opcode = kPPC_StoreDouble;
        break;
298 299
      case MachineRepresentation::kBit:  // Fall through.
      case MachineRepresentation::kWord8:
300 301
        opcode = kPPC_StoreWord8;
        break;
302
      case MachineRepresentation::kWord16:
303 304
        opcode = kPPC_StoreWord16;
        break;
305
#if !V8_TARGET_ARCH_PPC64
306 307
      case MachineRepresentation::kTaggedSigned:   // Fall through.
      case MachineRepresentation::kTaggedPointer:  // Fall through.
308
      case MachineRepresentation::kTagged:  // Fall through.
309
#endif
310
      case MachineRepresentation::kWord32:
311 312
        opcode = kPPC_StoreWord32;
        break;
313
#if V8_TARGET_ARCH_PPC64
314 315
      case MachineRepresentation::kTaggedSigned:   // Fall through.
      case MachineRepresentation::kTaggedPointer:  // Fall through.
316 317
      case MachineRepresentation::kTagged:  // Fall through.
      case MachineRepresentation::kWord64:
318 319 320
        opcode = kPPC_StoreWord64;
        mode = kInt16Imm_4ByteAligned;
        break;
321 322
#else
      case MachineRepresentation::kWord64:  // Fall through.
323
#endif
324
      case MachineRepresentation::kSimd128:  // Fall through.
325
      case MachineRepresentation::kNone:
326 327 328 329 330 331 332 333 334 335 336 337 338
        UNREACHABLE();
        return;
    }
    if (g.CanBeImmediate(offset, mode)) {
      Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(),
           g.UseRegister(base), g.UseImmediate(offset), g.UseRegister(value));
    } else if (g.CanBeImmediate(base, mode)) {
      Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(),
           g.UseRegister(offset), g.UseImmediate(base), g.UseRegister(value));
    } else {
      Emit(opcode | AddressingModeField::encode(kMode_MRR), g.NoOutput(),
           g.UseRegister(base), g.UseRegister(offset), g.UseRegister(value));
    }
339 340 341
  }
}

342 343 344 345 346
// Architecture supports unaligned access, therefore VisitLoad is used instead
void InstructionSelector::VisitUnalignedLoad(Node* node) { UNREACHABLE(); }

// Architecture supports unaligned access, therefore VisitStore is used instead
void InstructionSelector::VisitUnalignedStore(Node* node) { UNREACHABLE(); }
347 348

void InstructionSelector::VisitCheckedLoad(Node* node) {
349
  CheckedLoadRepresentation load_rep = CheckedLoadRepresentationOf(node->op());
350 351 352 353
  PPCOperandGenerator g(this);
  Node* const base = node->InputAt(0);
  Node* const offset = node->InputAt(1);
  Node* const length = node->InputAt(2);
354
  ArchOpcode opcode = kArchNop;
355 356 357
  switch (load_rep.representation()) {
    case MachineRepresentation::kWord8:
      opcode = load_rep.IsSigned() ? kCheckedLoadInt8 : kCheckedLoadUint8;
358
      break;
359 360
    case MachineRepresentation::kWord16:
      opcode = load_rep.IsSigned() ? kCheckedLoadInt16 : kCheckedLoadUint16;
361
      break;
362
    case MachineRepresentation::kWord32:
363 364
      opcode = kCheckedLoadWord32;
      break;
365
#if V8_TARGET_ARCH_PPC64
366
    case MachineRepresentation::kWord64:
367 368
      opcode = kCheckedLoadWord64;
      break;
369
#endif
370
    case MachineRepresentation::kFloat32:
371 372
      opcode = kCheckedLoadFloat32;
      break;
373
    case MachineRepresentation::kFloat64:
374 375
      opcode = kCheckedLoadFloat64;
      break;
376
    case MachineRepresentation::kBit:     // Fall through.
377 378
    case MachineRepresentation::kTaggedSigned:   // Fall through.
    case MachineRepresentation::kTaggedPointer:  // Fall through.
379 380 381 382
    case MachineRepresentation::kTagged:  // Fall through.
#if !V8_TARGET_ARCH_PPC64
    case MachineRepresentation::kWord64:  // Fall through.
#endif
383
    case MachineRepresentation::kSimd128:  // Fall through.
384
    case MachineRepresentation::kNone:
385 386 387 388 389 390 391 392 393 394 395
      UNREACHABLE();
      return;
  }
  AddressingMode addressingMode = kMode_MRR;
  Emit(opcode | AddressingModeField::encode(addressingMode),
       g.DefineAsRegister(node), g.UseRegister(base), g.UseRegister(offset),
       g.UseOperand(length, kInt16Imm_Unsigned));
}


void InstructionSelector::VisitCheckedStore(Node* node) {
396
  MachineRepresentation rep = CheckedStoreRepresentationOf(node->op());
397 398 399 400 401
  PPCOperandGenerator g(this);
  Node* const base = node->InputAt(0);
  Node* const offset = node->InputAt(1);
  Node* const length = node->InputAt(2);
  Node* const value = node->InputAt(3);
402
  ArchOpcode opcode = kArchNop;
403
  switch (rep) {
404
    case MachineRepresentation::kWord8:
405 406
      opcode = kCheckedStoreWord8;
      break;
407
    case MachineRepresentation::kWord16:
408 409
      opcode = kCheckedStoreWord16;
      break;
410
    case MachineRepresentation::kWord32:
411 412
      opcode = kCheckedStoreWord32;
      break;
413
#if V8_TARGET_ARCH_PPC64
414
    case MachineRepresentation::kWord64:
415 416
      opcode = kCheckedStoreWord64;
      break;
417
#endif
418
    case MachineRepresentation::kFloat32:
419 420
      opcode = kCheckedStoreFloat32;
      break;
421
    case MachineRepresentation::kFloat64:
422 423
      opcode = kCheckedStoreFloat64;
      break;
424
    case MachineRepresentation::kBit:     // Fall through.
425 426
    case MachineRepresentation::kTaggedSigned:   // Fall through.
    case MachineRepresentation::kTaggedPointer:  // Fall through.
427 428 429 430
    case MachineRepresentation::kTagged:  // Fall through.
#if !V8_TARGET_ARCH_PPC64
    case MachineRepresentation::kWord64:  // Fall through.
#endif
431
    case MachineRepresentation::kSimd128:  // Fall through.
432
    case MachineRepresentation::kNone:
433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451
      UNREACHABLE();
      return;
  }
  AddressingMode addressingMode = kMode_MRR;
  Emit(opcode | AddressingModeField::encode(addressingMode), g.NoOutput(),
       g.UseRegister(base), g.UseRegister(offset),
       g.UseOperand(length, kInt16Imm_Unsigned), g.UseRegister(value));
}


template <typename Matcher>
static void VisitLogical(InstructionSelector* selector, Node* node, Matcher* m,
                         ArchOpcode opcode, bool left_can_cover,
                         bool right_can_cover, ImmediateMode imm_mode) {
  PPCOperandGenerator g(selector);

  // Map instruction to equivalent operation with inverted right input.
  ArchOpcode inv_opcode = opcode;
  switch (opcode) {
452 453
    case kPPC_And:
      inv_opcode = kPPC_AndComplement;
454
      break;
455 456
    case kPPC_Or:
      inv_opcode = kPPC_OrComplement;
457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519
      break;
    default:
      UNREACHABLE();
  }

  // Select Logical(y, ~x) for Logical(Xor(x, -1), y).
  if ((m->left().IsWord32Xor() || m->left().IsWord64Xor()) && left_can_cover) {
    Matcher mleft(m->left().node());
    if (mleft.right().Is(-1)) {
      selector->Emit(inv_opcode, g.DefineAsRegister(node),
                     g.UseRegister(m->right().node()),
                     g.UseRegister(mleft.left().node()));
      return;
    }
  }

  // Select Logical(x, ~y) for Logical(x, Xor(y, -1)).
  if ((m->right().IsWord32Xor() || m->right().IsWord64Xor()) &&
      right_can_cover) {
    Matcher mright(m->right().node());
    if (mright.right().Is(-1)) {
      // TODO(all): support shifted operand on right.
      selector->Emit(inv_opcode, g.DefineAsRegister(node),
                     g.UseRegister(m->left().node()),
                     g.UseRegister(mright.left().node()));
      return;
    }
  }

  VisitBinop<Matcher>(selector, node, opcode, imm_mode);
}


static inline bool IsContiguousMask32(uint32_t value, int* mb, int* me) {
  int mask_width = base::bits::CountPopulation32(value);
  int mask_msb = base::bits::CountLeadingZeros32(value);
  int mask_lsb = base::bits::CountTrailingZeros32(value);
  if ((mask_width == 0) || (mask_msb + mask_width + mask_lsb != 32))
    return false;
  *mb = mask_lsb + mask_width - 1;
  *me = mask_lsb;
  return true;
}


#if V8_TARGET_ARCH_PPC64
static inline bool IsContiguousMask64(uint64_t value, int* mb, int* me) {
  int mask_width = base::bits::CountPopulation64(value);
  int mask_msb = base::bits::CountLeadingZeros64(value);
  int mask_lsb = base::bits::CountTrailingZeros64(value);
  if ((mask_width == 0) || (mask_msb + mask_width + mask_lsb != 64))
    return false;
  *mb = mask_lsb + mask_width - 1;
  *me = mask_lsb;
  return true;
}
#endif


// TODO(mbrandy): Absorb rotate-right into rlwinm?
void InstructionSelector::VisitWord32And(Node* node) {
  PPCOperandGenerator g(this);
  Int32BinopMatcher m(node);
520 521
  int mb = 0;
  int me = 0;
522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548
  if (m.right().HasValue() && IsContiguousMask32(m.right().Value(), &mb, &me)) {
    int sh = 0;
    Node* left = m.left().node();
    if ((m.left().IsWord32Shr() || m.left().IsWord32Shl()) &&
        CanCover(node, left)) {
      // Try to absorb left/right shift into rlwinm
      Int32BinopMatcher mleft(m.left().node());
      if (mleft.right().IsInRange(0, 31)) {
        left = mleft.left().node();
        sh = mleft.right().Value();
        if (m.left().IsWord32Shr()) {
          // Adjust the mask such that it doesn't include any rotated bits.
          if (mb > 31 - sh) mb = 31 - sh;
          sh = (32 - sh) & 0x1f;
        } else {
          // Adjust the mask such that it doesn't include any rotated bits.
          if (me < sh) me = sh;
        }
      }
    }
    if (mb >= me) {
      Emit(kPPC_RotLeftAndMask32, g.DefineAsRegister(node), g.UseRegister(left),
           g.TempImmediate(sh), g.TempImmediate(mb), g.TempImmediate(me));
      return;
    }
  }
  VisitLogical<Int32BinopMatcher>(
549
      this, node, &m, kPPC_And, CanCover(node, m.left().node()),
550 551 552 553 554 555 556 557 558
      CanCover(node, m.right().node()), kInt16Imm_Unsigned);
}


#if V8_TARGET_ARCH_PPC64
// TODO(mbrandy): Absorb rotate-right into rldic?
void InstructionSelector::VisitWord64And(Node* node) {
  PPCOperandGenerator g(this);
  Int64BinopMatcher m(node);
559 560
  int mb = 0;
  int me = 0;
561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605
  if (m.right().HasValue() && IsContiguousMask64(m.right().Value(), &mb, &me)) {
    int sh = 0;
    Node* left = m.left().node();
    if ((m.left().IsWord64Shr() || m.left().IsWord64Shl()) &&
        CanCover(node, left)) {
      // Try to absorb left/right shift into rldic
      Int64BinopMatcher mleft(m.left().node());
      if (mleft.right().IsInRange(0, 63)) {
        left = mleft.left().node();
        sh = mleft.right().Value();
        if (m.left().IsWord64Shr()) {
          // Adjust the mask such that it doesn't include any rotated bits.
          if (mb > 63 - sh) mb = 63 - sh;
          sh = (64 - sh) & 0x3f;
        } else {
          // Adjust the mask such that it doesn't include any rotated bits.
          if (me < sh) me = sh;
        }
      }
    }
    if (mb >= me) {
      bool match = false;
      ArchOpcode opcode;
      int mask;
      if (me == 0) {
        match = true;
        opcode = kPPC_RotLeftAndClearLeft64;
        mask = mb;
      } else if (mb == 63) {
        match = true;
        opcode = kPPC_RotLeftAndClearRight64;
        mask = me;
      } else if (sh && me <= sh && m.left().IsWord64Shl()) {
        match = true;
        opcode = kPPC_RotLeftAndClear64;
        mask = mb;
      }
      if (match) {
        Emit(opcode, g.DefineAsRegister(node), g.UseRegister(left),
             g.TempImmediate(sh), g.TempImmediate(mask));
        return;
      }
    }
  }
  VisitLogical<Int64BinopMatcher>(
606
      this, node, &m, kPPC_And, CanCover(node, m.left().node()),
607 608 609 610 611 612 613 614
      CanCover(node, m.right().node()), kInt16Imm_Unsigned);
}
#endif


void InstructionSelector::VisitWord32Or(Node* node) {
  Int32BinopMatcher m(node);
  VisitLogical<Int32BinopMatcher>(
615
      this, node, &m, kPPC_Or, CanCover(node, m.left().node()),
616 617 618 619 620 621 622 623
      CanCover(node, m.right().node()), kInt16Imm_Unsigned);
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Or(Node* node) {
  Int64BinopMatcher m(node);
  VisitLogical<Int64BinopMatcher>(
624
      this, node, &m, kPPC_Or, CanCover(node, m.left().node()),
625 626 627 628 629 630 631 632 633
      CanCover(node, m.right().node()), kInt16Imm_Unsigned);
}
#endif


void InstructionSelector::VisitWord32Xor(Node* node) {
  PPCOperandGenerator g(this);
  Int32BinopMatcher m(node);
  if (m.right().Is(-1)) {
634
    Emit(kPPC_Not, g.DefineAsRegister(node), g.UseRegister(m.left().node()));
635
  } else {
636
    VisitBinop<Int32BinopMatcher>(this, node, kPPC_Xor, kInt16Imm_Unsigned);
637 638 639 640 641 642 643 644 645
  }
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Xor(Node* node) {
  PPCOperandGenerator g(this);
  Int64BinopMatcher m(node);
  if (m.right().Is(-1)) {
646
    Emit(kPPC_Not, g.DefineAsRegister(node), g.UseRegister(m.left().node()));
647
  } else {
648
    VisitBinop<Int64BinopMatcher>(this, node, kPPC_Xor, kInt16Imm_Unsigned);
649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674
  }
}
#endif


void InstructionSelector::VisitWord32Shl(Node* node) {
  PPCOperandGenerator g(this);
  Int32BinopMatcher m(node);
  if (m.left().IsWord32And() && m.right().IsInRange(0, 31)) {
    // Try to absorb logical-and into rlwinm
    Int32BinopMatcher mleft(m.left().node());
    int sh = m.right().Value();
    int mb;
    int me;
    if (mleft.right().HasValue() &&
        IsContiguousMask32(mleft.right().Value() << sh, &mb, &me)) {
      // Adjust the mask such that it doesn't include any rotated bits.
      if (me < sh) me = sh;
      if (mb >= me) {
        Emit(kPPC_RotLeftAndMask32, g.DefineAsRegister(node),
             g.UseRegister(mleft.left().node()), g.TempImmediate(sh),
             g.TempImmediate(mb), g.TempImmediate(me));
        return;
      }
    }
  }
675
  VisitRRO(this, kPPC_ShiftLeft32, node, kShift32Imm);
676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Shl(Node* node) {
  PPCOperandGenerator g(this);
  Int64BinopMatcher m(node);
  // TODO(mbrandy): eliminate left sign extension if right >= 32
  if (m.left().IsWord64And() && m.right().IsInRange(0, 63)) {
    // Try to absorb logical-and into rldic
    Int64BinopMatcher mleft(m.left().node());
    int sh = m.right().Value();
    int mb;
    int me;
    if (mleft.right().HasValue() &&
        IsContiguousMask64(mleft.right().Value() << sh, &mb, &me)) {
      // Adjust the mask such that it doesn't include any rotated bits.
      if (me < sh) me = sh;
      if (mb >= me) {
        bool match = false;
        ArchOpcode opcode;
        int mask;
        if (me == 0) {
          match = true;
          opcode = kPPC_RotLeftAndClearLeft64;
          mask = mb;
        } else if (mb == 63) {
          match = true;
          opcode = kPPC_RotLeftAndClearRight64;
          mask = me;
        } else if (sh && me <= sh) {
          match = true;
          opcode = kPPC_RotLeftAndClear64;
          mask = mb;
        }
        if (match) {
          Emit(opcode, g.DefineAsRegister(node),
               g.UseRegister(mleft.left().node()), g.TempImmediate(sh),
               g.TempImmediate(mask));
          return;
        }
      }
    }
  }
720
  VisitRRO(this, kPPC_ShiftLeft64, node, kShift64Imm);
721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746
}
#endif


void InstructionSelector::VisitWord32Shr(Node* node) {
  PPCOperandGenerator g(this);
  Int32BinopMatcher m(node);
  if (m.left().IsWord32And() && m.right().IsInRange(0, 31)) {
    // Try to absorb logical-and into rlwinm
    Int32BinopMatcher mleft(m.left().node());
    int sh = m.right().Value();
    int mb;
    int me;
    if (mleft.right().HasValue() &&
        IsContiguousMask32((uint32_t)(mleft.right().Value()) >> sh, &mb, &me)) {
      // Adjust the mask such that it doesn't include any rotated bits.
      if (mb > 31 - sh) mb = 31 - sh;
      sh = (32 - sh) & 0x1f;
      if (mb >= me) {
        Emit(kPPC_RotLeftAndMask32, g.DefineAsRegister(node),
             g.UseRegister(mleft.left().node()), g.TempImmediate(sh),
             g.TempImmediate(mb), g.TempImmediate(me));
        return;
      }
    }
  }
747
  VisitRRO(this, kPPC_ShiftRight32, node, kShift32Imm);
748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786
}

#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Shr(Node* node) {
  PPCOperandGenerator g(this);
  Int64BinopMatcher m(node);
  if (m.left().IsWord64And() && m.right().IsInRange(0, 63)) {
    // Try to absorb logical-and into rldic
    Int64BinopMatcher mleft(m.left().node());
    int sh = m.right().Value();
    int mb;
    int me;
    if (mleft.right().HasValue() &&
        IsContiguousMask64((uint64_t)(mleft.right().Value()) >> sh, &mb, &me)) {
      // Adjust the mask such that it doesn't include any rotated bits.
      if (mb > 63 - sh) mb = 63 - sh;
      sh = (64 - sh) & 0x3f;
      if (mb >= me) {
        bool match = false;
        ArchOpcode opcode;
        int mask;
        if (me == 0) {
          match = true;
          opcode = kPPC_RotLeftAndClearLeft64;
          mask = mb;
        } else if (mb == 63) {
          match = true;
          opcode = kPPC_RotLeftAndClearRight64;
          mask = me;
        }
        if (match) {
          Emit(opcode, g.DefineAsRegister(node),
               g.UseRegister(mleft.left().node()), g.TempImmediate(sh),
               g.TempImmediate(mask));
          return;
        }
      }
    }
  }
787
  VisitRRO(this, kPPC_ShiftRight64, node, kShift64Imm);
788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807
}
#endif


void InstructionSelector::VisitWord32Sar(Node* node) {
  PPCOperandGenerator g(this);
  Int32BinopMatcher m(node);
  // Replace with sign extension for (x << K) >> K where K is 16 or 24.
  if (CanCover(node, m.left().node()) && m.left().IsWord32Shl()) {
    Int32BinopMatcher mleft(m.left().node());
    if (mleft.right().Is(16) && m.right().Is(16)) {
      Emit(kPPC_ExtendSignWord16, g.DefineAsRegister(node),
           g.UseRegister(mleft.left().node()));
      return;
    } else if (mleft.right().Is(24) && m.right().Is(24)) {
      Emit(kPPC_ExtendSignWord8, g.DefineAsRegister(node),
           g.UseRegister(mleft.left().node()));
      return;
    }
  }
808
  VisitRRO(this, kPPC_ShiftRightAlg32, node, kShift32Imm);
809 810
}

811
#if !V8_TARGET_ARCH_PPC64
812
void VisitPairBinop(InstructionSelector* selector, InstructionCode opcode,
813
                    InstructionCode opcode2, Node* node) {
814
  PPCOperandGenerator g(selector);
815

816 817 818 819 820 821 822
  Node* projection1 = NodeProperties::FindProjection(node, 1);
  if (projection1) {
    // We use UseUniqueRegister here to avoid register sharing with the output
    // registers.
    InstructionOperand inputs[] = {
        g.UseRegister(node->InputAt(0)), g.UseUniqueRegister(node->InputAt(1)),
        g.UseRegister(node->InputAt(2)), g.UseUniqueRegister(node->InputAt(3))};
823

824 825 826
    InstructionOperand outputs[] = {
        g.DefineAsRegister(node),
        g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
827

828 829 830 831 832 833 834 835
    selector->Emit(opcode, 2, outputs, 4, inputs);
  } else {
    // The high word of the result is not used, so we emit the standard 32 bit
    // instruction.
    selector->Emit(opcode2, g.DefineSameAsFirst(node),
                   g.UseRegister(node->InputAt(0)),
                   g.UseRegister(node->InputAt(2)));
  }
836 837
}

838
void InstructionSelector::VisitInt32PairAdd(Node* node) {
839
  VisitPairBinop(this, kPPC_AddPair, kPPC_Add, node);
840 841 842
}

void InstructionSelector::VisitInt32PairSub(Node* node) {
843
  VisitPairBinop(this, kPPC_SubPair, kPPC_Sub, node);
844
}
845

846 847
void InstructionSelector::VisitInt32PairMul(Node* node) {
  PPCOperandGenerator g(this);
848 849 850 851 852 853
  Node* projection1 = NodeProperties::FindProjection(node, 1);
  if (projection1) {
    InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)),
                                   g.UseUniqueRegister(node->InputAt(1)),
                                   g.UseUniqueRegister(node->InputAt(2)),
                                   g.UseUniqueRegister(node->InputAt(3))};
854

855 856 857
    InstructionOperand outputs[] = {
        g.DefineAsRegister(node),
        g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
858

859
    InstructionOperand temps[] = {g.TempRegister(), g.TempRegister()};
860

861 862 863 864 865 866 867
    Emit(kPPC_MulPair, 2, outputs, 4, inputs, 2, temps);
  } else {
    // The high word of the result is not used, so we emit the standard 32 bit
    // instruction.
    Emit(kPPC_Mul32, g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)),
         g.UseRegister(node->InputAt(2)));
  }
868
}
869

870 871
namespace {
// Shared routine for multiple shift operations.
872
void VisitPairShift(InstructionSelector* selector, InstructionCode opcode,
873 874
                    Node* node) {
  PPCOperandGenerator g(selector);
875 876
  // We use g.UseUniqueRegister here to guarantee that there is
  // no register aliasing of input registers with output registers.
877 878 879 880 881 882 883 884
  Int32Matcher m(node->InputAt(2));
  InstructionOperand shift_operand;
  if (m.HasValue()) {
    shift_operand = g.UseImmediate(m.node());
  } else {
    shift_operand = g.UseUniqueRegister(m.node());
  }

885 886
  InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)),
                                 g.UseUniqueRegister(node->InputAt(1)),
887 888
                                 shift_operand};

889
  Node* projection1 = NodeProperties::FindProjection(node, 1);
890

891 892 893 894 895 896 897 898 899 900 901 902 903
  InstructionOperand outputs[2];
  InstructionOperand temps[1];
  int32_t output_count = 0;
  int32_t temp_count = 0;

  outputs[output_count++] = g.DefineAsRegister(node);
  if (projection1) {
    outputs[output_count++] = g.DefineAsRegister(projection1);
  } else {
    temps[temp_count++] = g.TempRegister();
  }

  selector->Emit(opcode, output_count, outputs, 3, inputs, temp_count, temps);
904
}
905
}  // namespace
906 907 908 909 910 911 912 913 914 915 916

void InstructionSelector::VisitWord32PairShl(Node* node) {
  VisitPairShift(this, kPPC_ShiftLeftPair, node);
}

void InstructionSelector::VisitWord32PairShr(Node* node) {
  VisitPairShift(this, kPPC_ShiftRightPair, node);
}

void InstructionSelector::VisitWord32PairSar(Node* node) {
  VisitPairShift(this, kPPC_ShiftRightAlgPair, node);
917 918
}
#endif
919 920 921

#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Sar(Node* node) {
922 923 924 925 926 927
  PPCOperandGenerator g(this);
  Int64BinopMatcher m(node);
  if (CanCover(m.node(), m.left().node()) && m.left().IsLoad() &&
      m.right().Is(32)) {
    // Just load and sign-extend the interesting 4 bytes instead. This happens,
    // for example, when we're loading and untagging SMIs.
928 929
    BaseWithIndexAndDisplacement64Matcher mleft(m.left().node(),
                                                AddressOption::kAllowAll);
930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946
    if (mleft.matches() && mleft.index() == nullptr) {
      int64_t offset = 0;
      Node* displacement = mleft.displacement();
      if (displacement != nullptr) {
        Int64Matcher mdisplacement(displacement);
        DCHECK(mdisplacement.HasValue());
        offset = mdisplacement.Value();
      }
      offset = SmiWordOffset(offset);
      if (g.CanBeImmediate(offset, kInt16Imm_4ByteAligned)) {
        Emit(kPPC_LoadWordS32 | AddressingModeField::encode(kMode_MRI),
             g.DefineAsRegister(node), g.UseRegister(mleft.base()),
             g.TempImmediate(offset));
        return;
      }
    }
  }
947
  VisitRRO(this, kPPC_ShiftRightAlg64, node, kShift64Imm);
948 949 950 951 952 953
}
#endif


// TODO(mbrandy): Absorb logical-and into rlwinm?
void InstructionSelector::VisitWord32Ror(Node* node) {
954
  VisitRRO(this, kPPC_RotRight32, node, kShift32Imm);
955 956 957 958 959 960
}


#if V8_TARGET_ARCH_PPC64
// TODO(mbrandy): Absorb logical-and into rldic?
void InstructionSelector::VisitWord64Ror(Node* node) {
961
  VisitRRO(this, kPPC_RotRight64, node, kShift64Imm);
962 963 964 965
}
#endif


966 967 968 969 970 971
void InstructionSelector::VisitWord32Clz(Node* node) {
  PPCOperandGenerator g(this);
  Emit(kPPC_Cntlz32, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)));
}


972 973 974 975 976 977 978 979
#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Clz(Node* node) {
  PPCOperandGenerator g(this);
  Emit(kPPC_Cntlz64, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)));
}
#endif


980 981 982 983 984
void InstructionSelector::VisitWord32Popcnt(Node* node) {
  PPCOperandGenerator g(this);
  Emit(kPPC_Popcnt32, g.DefineAsRegister(node),
       g.UseRegister(node->InputAt(0)));
}
985 986


987 988 989 990 991 992 993 994 995
#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Popcnt(Node* node) {
  PPCOperandGenerator g(this);
  Emit(kPPC_Popcnt64, g.DefineAsRegister(node),
       g.UseRegister(node->InputAt(0)));
}
#endif


996
void InstructionSelector::VisitWord32Ctz(Node* node) { UNREACHABLE(); }
997 998


999 1000 1001 1002 1003
#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Ctz(Node* node) { UNREACHABLE(); }
#endif


1004 1005 1006 1007 1008 1009 1010
void InstructionSelector::VisitWord32ReverseBits(Node* node) { UNREACHABLE(); }


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64ReverseBits(Node* node) { UNREACHABLE(); }
#endif

1011 1012 1013
void InstructionSelector::VisitWord64ReverseBytes(Node* node) { UNREACHABLE(); }

void InstructionSelector::VisitWord32ReverseBytes(Node* node) { UNREACHABLE(); }
1014

1015
void InstructionSelector::VisitInt32Add(Node* node) {
1016
  VisitBinop<Int32BinopMatcher>(this, node, kPPC_Add, kInt16Imm);
1017 1018 1019 1020 1021
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitInt64Add(Node* node) {
1022
  VisitBinop<Int64BinopMatcher>(this, node, kPPC_Add, kInt16Imm);
1023 1024 1025 1026 1027 1028 1029
}
#endif

void InstructionSelector::VisitInt32Sub(Node* node) {
  PPCOperandGenerator g(this);
  Int32BinopMatcher m(node);
  if (m.left().Is(0)) {
1030
    Emit(kPPC_Neg, g.DefineAsRegister(node), g.UseRegister(m.right().node()));
1031
  } else {
1032
    VisitBinop<Int32BinopMatcher>(this, node, kPPC_Sub, kInt16Imm_Negate);
1033 1034 1035 1036 1037 1038 1039 1040 1041
  }
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitInt64Sub(Node* node) {
  PPCOperandGenerator g(this);
  Int64BinopMatcher m(node);
  if (m.left().Is(0)) {
1042
    Emit(kPPC_Neg, g.DefineAsRegister(node), g.UseRegister(m.right().node()));
1043
  } else {
1044
    VisitBinop<Int64BinopMatcher>(this, node, kPPC_Sub, kInt16Imm_Negate);
1045 1046 1047 1048
  }
}
#endif

1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078
namespace {

void VisitCompare(InstructionSelector* selector, InstructionCode opcode,
                  InstructionOperand left, InstructionOperand right,
                  FlagsContinuation* cont);
void EmitInt32MulWithOverflow(InstructionSelector* selector, Node* node,
                              FlagsContinuation* cont) {
  PPCOperandGenerator g(selector);
  Int32BinopMatcher m(node);
  InstructionOperand result_operand = g.DefineAsRegister(node);
  InstructionOperand high32_operand = g.TempRegister();
  InstructionOperand temp_operand = g.TempRegister();
  {
    InstructionOperand outputs[] = {result_operand, high32_operand};
    InstructionOperand inputs[] = {g.UseRegister(m.left().node()),
                                   g.UseRegister(m.right().node())};
    selector->Emit(kPPC_Mul32WithHigh32, 2, outputs, 2, inputs);
  }
  {
    InstructionOperand shift_31 = g.UseImmediate(31);
    InstructionOperand outputs[] = {temp_operand};
    InstructionOperand inputs[] = {result_operand, shift_31};
    selector->Emit(kPPC_ShiftRightAlg32, 1, outputs, 2, inputs);
  }

  VisitCompare(selector, kPPC_Cmp32, high32_operand, temp_operand, cont);
}

}  // namespace

1079 1080

void InstructionSelector::VisitInt32Mul(Node* node) {
1081
  VisitRRR(this, kPPC_Mul32, node);
1082 1083 1084 1085 1086
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitInt64Mul(Node* node) {
1087
  VisitRRR(this, kPPC_Mul64, node);
1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106
}
#endif


void InstructionSelector::VisitInt32MulHigh(Node* node) {
  PPCOperandGenerator g(this);
  Emit(kPPC_MulHigh32, g.DefineAsRegister(node),
       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}


void InstructionSelector::VisitUint32MulHigh(Node* node) {
  PPCOperandGenerator g(this);
  Emit(kPPC_MulHighU32, g.DefineAsRegister(node),
       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}


void InstructionSelector::VisitInt32Div(Node* node) {
1107
  VisitRRR(this, kPPC_Div32, node);
1108 1109 1110 1111 1112
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitInt64Div(Node* node) {
1113
  VisitRRR(this, kPPC_Div64, node);
1114 1115 1116 1117 1118
}
#endif


void InstructionSelector::VisitUint32Div(Node* node) {
1119
  VisitRRR(this, kPPC_DivU32, node);
1120 1121 1122 1123 1124
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitUint64Div(Node* node) {
1125
  VisitRRR(this, kPPC_DivU64, node);
1126 1127 1128 1129 1130
}
#endif


void InstructionSelector::VisitInt32Mod(Node* node) {
1131
  VisitRRR(this, kPPC_Mod32, node);
1132 1133 1134 1135 1136
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitInt64Mod(Node* node) {
1137
  VisitRRR(this, kPPC_Mod64, node);
1138 1139 1140 1141 1142
}
#endif


void InstructionSelector::VisitUint32Mod(Node* node) {
1143
  VisitRRR(this, kPPC_ModU32, node);
1144 1145 1146 1147 1148
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitUint64Mod(Node* node) {
1149
  VisitRRR(this, kPPC_ModU64, node);
1150 1151 1152 1153 1154
}
#endif


void InstructionSelector::VisitChangeFloat32ToFloat64(Node* node) {
1155
  VisitRR(this, kPPC_Float32ToDouble, node);
1156 1157 1158
}


1159 1160 1161 1162 1163
void InstructionSelector::VisitRoundInt32ToFloat32(Node* node) {
  VisitRR(this, kPPC_Int32ToFloat32, node);
}


1164
void InstructionSelector::VisitRoundUint32ToFloat32(Node* node) {
1165
  VisitRR(this, kPPC_Uint32ToFloat32, node);
1166 1167 1168
}


1169
void InstructionSelector::VisitChangeInt32ToFloat64(Node* node) {
1170
  VisitRR(this, kPPC_Int32ToDouble, node);
1171 1172 1173 1174
}


void InstructionSelector::VisitChangeUint32ToFloat64(Node* node) {
1175
  VisitRR(this, kPPC_Uint32ToDouble, node);
1176 1177 1178 1179
}


void InstructionSelector::VisitChangeFloat64ToInt32(Node* node) {
1180
  VisitRR(this, kPPC_DoubleToInt32, node);
1181 1182 1183 1184
}


void InstructionSelector::VisitChangeFloat64ToUint32(Node* node) {
1185
  VisitRR(this, kPPC_DoubleToUint32, node);
1186 1187
}

1188 1189 1190
void InstructionSelector::VisitTruncateFloat64ToUint32(Node* node) {
  VisitRR(this, kPPC_DoubleToUint32, node);
}
1191 1192

#if V8_TARGET_ARCH_PPC64
1193
void InstructionSelector::VisitTryTruncateFloat32ToInt64(Node* node) {
1194
  VisitTryTruncateDouble(this, kPPC_DoubleToInt64, node);
1195 1196 1197
}


1198
void InstructionSelector::VisitTryTruncateFloat64ToInt64(Node* node) {
1199
  VisitTryTruncateDouble(this, kPPC_DoubleToInt64, node);
1200 1201 1202
}


1203
void InstructionSelector::VisitTryTruncateFloat32ToUint64(Node* node) {
1204
  VisitTryTruncateDouble(this, kPPC_DoubleToUint64, node);
1205 1206 1207
}


1208
void InstructionSelector::VisitTryTruncateFloat64ToUint64(Node* node) {
1209
  VisitTryTruncateDouble(this, kPPC_DoubleToUint64, node);
1210 1211 1212
}


1213 1214
void InstructionSelector::VisitChangeInt32ToInt64(Node* node) {
  // TODO(mbrandy): inspect input to see if nop is appropriate.
1215
  VisitRR(this, kPPC_ExtendSignWord32, node);
1216 1217 1218 1219 1220
}


void InstructionSelector::VisitChangeUint32ToUint64(Node* node) {
  // TODO(mbrandy): inspect input to see if nop is appropriate.
1221
  VisitRR(this, kPPC_Uint32ToUint64, node);
1222 1223 1224 1225 1226
}
#endif


void InstructionSelector::VisitTruncateFloat64ToFloat32(Node* node) {
1227 1228 1229
  VisitRR(this, kPPC_DoubleToFloat32, node);
}

1230
void InstructionSelector::VisitTruncateFloat64ToWord32(Node* node) {
1231 1232 1233 1234 1235
  VisitRR(this, kArchTruncateDoubleToI, node);
}

void InstructionSelector::VisitRoundFloat64ToInt32(Node* node) {
  VisitRR(this, kPPC_DoubleToInt32, node);
1236 1237 1238
}


1239
void InstructionSelector::VisitTruncateFloat32ToInt32(Node* node) {
1240
  VisitRR(this, kPPC_DoubleToInt32, node);
1241 1242 1243
}


1244
void InstructionSelector::VisitTruncateFloat32ToUint32(Node* node) {
1245
  VisitRR(this, kPPC_DoubleToUint32, node);
1246 1247 1248
}


1249 1250 1251
#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitTruncateInt64ToInt32(Node* node) {
  // TODO(mbrandy): inspect input to see if nop is appropriate.
1252
  VisitRR(this, kPPC_Int64ToInt32, node);
1253
}
1254 1255


1256 1257 1258 1259 1260
void InstructionSelector::VisitRoundInt64ToFloat32(Node* node) {
  VisitRR(this, kPPC_Int64ToFloat32, node);
}


1261 1262 1263
void InstructionSelector::VisitRoundInt64ToFloat64(Node* node) {
  VisitRR(this, kPPC_Int64ToDouble, node);
}
1264 1265


1266 1267 1268 1269 1270
void InstructionSelector::VisitRoundUint64ToFloat32(Node* node) {
  VisitRR(this, kPPC_Uint64ToFloat32, node);
}


1271
void InstructionSelector::VisitRoundUint64ToFloat64(Node* node) {
1272
  VisitRR(this, kPPC_Uint64ToDouble, node);
1273
}
1274 1275 1276
#endif


1277
void InstructionSelector::VisitBitcastFloat32ToInt32(Node* node) {
1278
  VisitRR(this, kPPC_BitcastFloat32ToInt32, node);
1279 1280 1281 1282 1283
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitBitcastFloat64ToInt64(Node* node) {
1284
  VisitRR(this, kPPC_BitcastDoubleToInt64, node);
1285 1286 1287 1288 1289
}
#endif


void InstructionSelector::VisitBitcastInt32ToFloat32(Node* node) {
1290
  VisitRR(this, kPPC_BitcastInt32ToFloat32, node);
1291 1292 1293 1294 1295
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitBitcastInt64ToFloat64(Node* node) {
1296
  VisitRR(this, kPPC_BitcastInt64ToDouble, node);
1297 1298 1299 1300
}
#endif


1301
void InstructionSelector::VisitFloat32Add(Node* node) {
1302
  VisitRRR(this, kPPC_AddDouble | MiscField::encode(1), node);
1303 1304 1305
}


1306 1307
void InstructionSelector::VisitFloat64Add(Node* node) {
  // TODO(mbrandy): detect multiply-add
1308 1309 1310 1311 1312
  VisitRRR(this, kPPC_AddDouble, node);
}


void InstructionSelector::VisitFloat32Sub(Node* node) {
1313 1314
  VisitRRR(this, kPPC_SubDouble | MiscField::encode(1), node);
}
1315 1316 1317

void InstructionSelector::VisitFloat64Sub(Node* node) {
  // TODO(mbrandy): detect multiply-subtract
1318 1319
  VisitRRR(this, kPPC_SubDouble, node);
}
1320 1321

void InstructionSelector::VisitFloat32Mul(Node* node) {
1322
  VisitRRR(this, kPPC_MulDouble | MiscField::encode(1), node);
1323 1324 1325 1326 1327
}


void InstructionSelector::VisitFloat64Mul(Node* node) {
  // TODO(mbrandy): detect negate
1328 1329 1330 1331 1332
  VisitRRR(this, kPPC_MulDouble, node);
}


void InstructionSelector::VisitFloat32Div(Node* node) {
1333
  VisitRRR(this, kPPC_DivDouble | MiscField::encode(1), node);
1334 1335 1336 1337
}


void InstructionSelector::VisitFloat64Div(Node* node) {
1338
  VisitRRR(this, kPPC_DivDouble, node);
1339 1340 1341 1342 1343
}


void InstructionSelector::VisitFloat64Mod(Node* node) {
  PPCOperandGenerator g(this);
1344
  Emit(kPPC_ModDouble, g.DefineAsFixed(node, d1),
1345 1346 1347 1348
       g.UseFixed(node->InputAt(0), d1),
       g.UseFixed(node->InputAt(1), d2))->MarkAsCall();
}

1349 1350 1351
void InstructionSelector::VisitFloat32Max(Node* node) {
  VisitRRR(this, kPPC_MaxDouble | MiscField::encode(1), node);
}
1352

1353 1354 1355
void InstructionSelector::VisitFloat64Max(Node* node) {
  VisitRRR(this, kPPC_MaxDouble, node);
}
1356 1357


1358 1359 1360 1361
void InstructionSelector::VisitFloat64SilenceNaN(Node* node) {
  VisitRR(this, kPPC_Float64SilenceNaN, node);
}

1362 1363 1364
void InstructionSelector::VisitFloat32Min(Node* node) {
  VisitRRR(this, kPPC_MinDouble | MiscField::encode(1), node);
}
1365

1366 1367 1368
void InstructionSelector::VisitFloat64Min(Node* node) {
  VisitRRR(this, kPPC_MinDouble, node);
}
1369 1370


1371
void InstructionSelector::VisitFloat32Abs(Node* node) {
1372
  VisitRR(this, kPPC_AbsDouble | MiscField::encode(1), node);
1373
}
1374 1375


1376 1377 1378
void InstructionSelector::VisitFloat64Abs(Node* node) {
  VisitRR(this, kPPC_AbsDouble, node);
}
1379

1380
void InstructionSelector::VisitFloat32Sqrt(Node* node) {
1381
  VisitRR(this, kPPC_SqrtDouble | MiscField::encode(1), node);
1382
}
1383

1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397
void InstructionSelector::VisitFloat64Ieee754Unop(Node* node,
                                                  InstructionCode opcode) {
  PPCOperandGenerator g(this);
  Emit(opcode, g.DefineAsFixed(node, d1), g.UseFixed(node->InputAt(0), d1))
       ->MarkAsCall();
}

void InstructionSelector::VisitFloat64Ieee754Binop(Node* node,
                                                  InstructionCode opcode) {
  PPCOperandGenerator g(this);
  Emit(opcode, g.DefineAsFixed(node, d1),
       g.UseFixed(node->InputAt(0), d1),
       g.UseFixed(node->InputAt(1), d2))->MarkAsCall();
}
1398

1399
void InstructionSelector::VisitFloat64Sqrt(Node* node) {
1400
  VisitRR(this, kPPC_SqrtDouble, node);
1401 1402 1403
}


1404
void InstructionSelector::VisitFloat32RoundDown(Node* node) {
1405
  VisitRR(this, kPPC_FloorDouble | MiscField::encode(1), node);
1406
}
1407 1408


1409
void InstructionSelector::VisitFloat64RoundDown(Node* node) {
1410
  VisitRR(this, kPPC_FloorDouble, node);
1411 1412 1413
}


1414
void InstructionSelector::VisitFloat32RoundUp(Node* node) {
1415
  VisitRR(this, kPPC_CeilDouble | MiscField::encode(1), node);
1416
}
1417 1418


1419 1420 1421 1422 1423
void InstructionSelector::VisitFloat64RoundUp(Node* node) {
  VisitRR(this, kPPC_CeilDouble, node);
}


1424
void InstructionSelector::VisitFloat32RoundTruncate(Node* node) {
1425
  VisitRR(this, kPPC_TruncateDouble | MiscField::encode(1), node);
1426 1427 1428
}


1429
void InstructionSelector::VisitFloat64RoundTruncate(Node* node) {
1430
  VisitRR(this, kPPC_TruncateDouble, node);
1431 1432 1433 1434
}


void InstructionSelector::VisitFloat64RoundTiesAway(Node* node) {
1435
  VisitRR(this, kPPC_RoundDouble, node);
1436 1437 1438
}


1439 1440 1441 1442 1443
void InstructionSelector::VisitFloat32RoundTiesEven(Node* node) {
  UNREACHABLE();
}


1444 1445 1446 1447
void InstructionSelector::VisitFloat64RoundTiesEven(Node* node) {
  UNREACHABLE();
}

1448 1449 1450
void InstructionSelector::VisitFloat32Neg(Node* node) {
  VisitRR(this, kPPC_NegDouble, node);
}
1451

1452 1453 1454
void InstructionSelector::VisitFloat64Neg(Node* node) {
  VisitRR(this, kPPC_NegDouble, node);
}
1455

1456 1457
void InstructionSelector::VisitInt32AddWithOverflow(Node* node) {
  if (Node* ovf = NodeProperties::FindProjection(node, 1)) {
1458
    FlagsContinuation cont = FlagsContinuation::ForSet(kOverflow, ovf);
1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469
    return VisitBinop<Int32BinopMatcher>(this, node, kPPC_AddWithOverflow32,
                                         kInt16Imm, &cont);
  }
  FlagsContinuation cont;
  VisitBinop<Int32BinopMatcher>(this, node, kPPC_AddWithOverflow32, kInt16Imm,
                                &cont);
}


void InstructionSelector::VisitInt32SubWithOverflow(Node* node) {
  if (Node* ovf = NodeProperties::FindProjection(node, 1)) {
1470
    FlagsContinuation cont = FlagsContinuation::ForSet(kOverflow, ovf);
1471 1472 1473 1474 1475 1476 1477 1478 1479
    return VisitBinop<Int32BinopMatcher>(this, node, kPPC_SubWithOverflow32,
                                         kInt16Imm_Negate, &cont);
  }
  FlagsContinuation cont;
  VisitBinop<Int32BinopMatcher>(this, node, kPPC_SubWithOverflow32,
                                kInt16Imm_Negate, &cont);
}


1480 1481 1482
#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitInt64AddWithOverflow(Node* node) {
  if (Node* ovf = NodeProperties::FindProjection(node, 1)) {
1483
    FlagsContinuation cont = FlagsContinuation::ForSet(kOverflow, ovf);
1484 1485 1486 1487 1488 1489 1490 1491 1492 1493
    return VisitBinop<Int64BinopMatcher>(this, node, kPPC_Add, kInt16Imm,
                                         &cont);
  }
  FlagsContinuation cont;
  VisitBinop<Int64BinopMatcher>(this, node, kPPC_Add, kInt16Imm, &cont);
}


void InstructionSelector::VisitInt64SubWithOverflow(Node* node) {
  if (Node* ovf = NodeProperties::FindProjection(node, 1)) {
1494
    FlagsContinuation cont = FlagsContinuation::ForSet(kOverflow, ovf);
1495 1496 1497 1498 1499 1500 1501 1502 1503
    return VisitBinop<Int64BinopMatcher>(this, node, kPPC_Sub, kInt16Imm_Negate,
                                         &cont);
  }
  FlagsContinuation cont;
  VisitBinop<Int64BinopMatcher>(this, node, kPPC_Sub, kInt16Imm_Negate, &cont);
}
#endif


1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518
static bool CompareLogical(FlagsContinuation* cont) {
  switch (cont->condition()) {
    case kUnsignedLessThan:
    case kUnsignedGreaterThanOrEqual:
    case kUnsignedLessThanOrEqual:
    case kUnsignedGreaterThan:
      return true;
    default:
      return false;
  }
  UNREACHABLE();
  return false;
}


1519 1520
namespace {

1521
// Shared routine for multiple compare operations.
1522 1523 1524
void VisitCompare(InstructionSelector* selector, InstructionCode opcode,
                  InstructionOperand left, InstructionOperand right,
                  FlagsContinuation* cont) {
1525 1526 1527 1528
  PPCOperandGenerator g(selector);
  opcode = cont->Encode(opcode);
  if (cont->IsBranch()) {
    selector->Emit(opcode, g.NoOutput(), left, right,
1529
                   g.Label(cont->true_block()), g.Label(cont->false_block()));
1530
  } else if (cont->IsDeoptimize()) {
1531
    selector->EmitDeoptimize(opcode, g.NoOutput(), left, right, cont->reason(),
1532
                             cont->frame_state());
1533 1534 1535 1536 1537 1538 1539 1540
  } else {
    DCHECK(cont->IsSet());
    selector->Emit(opcode, g.DefineAsRegister(cont->result()), left, right);
  }
}


// Shared routine for multiple word compare operations.
1541 1542 1543
void VisitWordCompare(InstructionSelector* selector, Node* node,
                      InstructionCode opcode, FlagsContinuation* cont,
                      bool commutative, ImmediateMode immediate_mode) {
1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562
  PPCOperandGenerator g(selector);
  Node* left = node->InputAt(0);
  Node* right = node->InputAt(1);

  // Match immediates on left or right side of comparison.
  if (g.CanBeImmediate(right, immediate_mode)) {
    VisitCompare(selector, opcode, g.UseRegister(left), g.UseImmediate(right),
                 cont);
  } else if (g.CanBeImmediate(left, immediate_mode)) {
    if (!commutative) cont->Commute();
    VisitCompare(selector, opcode, g.UseRegister(right), g.UseImmediate(left),
                 cont);
  } else {
    VisitCompare(selector, opcode, g.UseRegister(left), g.UseRegister(right),
                 cont);
  }
}


1563 1564
void VisitWord32Compare(InstructionSelector* selector, Node* node,
                        FlagsContinuation* cont) {
1565 1566 1567 1568 1569 1570
  ImmediateMode mode = (CompareLogical(cont) ? kInt16Imm_Unsigned : kInt16Imm);
  VisitWordCompare(selector, node, kPPC_Cmp32, cont, false, mode);
}


#if V8_TARGET_ARCH_PPC64
1571 1572
void VisitWord64Compare(InstructionSelector* selector, Node* node,
                        FlagsContinuation* cont) {
1573 1574 1575 1576 1577 1578
  ImmediateMode mode = (CompareLogical(cont) ? kInt16Imm_Unsigned : kInt16Imm);
  VisitWordCompare(selector, node, kPPC_Cmp64, cont, false, mode);
}
#endif


1579 1580 1581
// Shared routine for multiple float32 compare operations.
void VisitFloat32Compare(InstructionSelector* selector, Node* node,
                         FlagsContinuation* cont) {
1582 1583 1584
  PPCOperandGenerator g(selector);
  Node* left = node->InputAt(0);
  Node* right = node->InputAt(1);
1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596
  VisitCompare(selector, kPPC_CmpDouble, g.UseRegister(left),
               g.UseRegister(right), cont);
}


// Shared routine for multiple float64 compare operations.
void VisitFloat64Compare(InstructionSelector* selector, Node* node,
                         FlagsContinuation* cont) {
  PPCOperandGenerator g(selector);
  Node* left = node->InputAt(0);
  Node* right = node->InputAt(1);
  VisitCompare(selector, kPPC_CmpDouble, g.UseRegister(left),
1597 1598 1599 1600 1601
               g.UseRegister(right), cont);
}


// Shared routine for word comparisons against zero.
1602 1603 1604
void VisitWordCompareZero(InstructionSelector* selector, Node* user,
                          Node* value, InstructionCode opcode,
                          FlagsContinuation* cont) {
1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616
  // Try to combine with comparisons against 0 by simply inverting the branch.
  while (value->opcode() == IrOpcode::kWord32Equal &&
         selector->CanCover(user, value)) {
    Int32BinopMatcher m(value);
    if (!m.right().Is(0)) break;

    user = value;
    value = m.left().node();
    cont->Negate();
  }

  if (selector->CanCover(user, value)) {
1617
    switch (value->opcode()) {
1618
      case IrOpcode::kWord32Equal:
1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633
        cont->OverwriteAndNegateIfEqual(kEqual);
        return VisitWord32Compare(selector, value, cont);
      case IrOpcode::kInt32LessThan:
        cont->OverwriteAndNegateIfEqual(kSignedLessThan);
        return VisitWord32Compare(selector, value, cont);
      case IrOpcode::kInt32LessThanOrEqual:
        cont->OverwriteAndNegateIfEqual(kSignedLessThanOrEqual);
        return VisitWord32Compare(selector, value, cont);
      case IrOpcode::kUint32LessThan:
        cont->OverwriteAndNegateIfEqual(kUnsignedLessThan);
        return VisitWord32Compare(selector, value, cont);
      case IrOpcode::kUint32LessThanOrEqual:
        cont->OverwriteAndNegateIfEqual(kUnsignedLessThanOrEqual);
        return VisitWord32Compare(selector, value, cont);
#if V8_TARGET_ARCH_PPC64
1634
      case IrOpcode::kWord64Equal:
1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645
        cont->OverwriteAndNegateIfEqual(kEqual);
        return VisitWord64Compare(selector, value, cont);
      case IrOpcode::kInt64LessThan:
        cont->OverwriteAndNegateIfEqual(kSignedLessThan);
        return VisitWord64Compare(selector, value, cont);
      case IrOpcode::kInt64LessThanOrEqual:
        cont->OverwriteAndNegateIfEqual(kSignedLessThanOrEqual);
        return VisitWord64Compare(selector, value, cont);
      case IrOpcode::kUint64LessThan:
        cont->OverwriteAndNegateIfEqual(kUnsignedLessThan);
        return VisitWord64Compare(selector, value, cont);
1646 1647 1648
      case IrOpcode::kUint64LessThanOrEqual:
        cont->OverwriteAndNegateIfEqual(kUnsignedLessThanOrEqual);
        return VisitWord64Compare(selector, value, cont);
1649
#endif
1650 1651 1652 1653 1654 1655 1656 1657 1658
      case IrOpcode::kFloat32Equal:
        cont->OverwriteAndNegateIfEqual(kEqual);
        return VisitFloat32Compare(selector, value, cont);
      case IrOpcode::kFloat32LessThan:
        cont->OverwriteAndNegateIfEqual(kUnsignedLessThan);
        return VisitFloat32Compare(selector, value, cont);
      case IrOpcode::kFloat32LessThanOrEqual:
        cont->OverwriteAndNegateIfEqual(kUnsignedLessThanOrEqual);
        return VisitFloat32Compare(selector, value, cont);
1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673
      case IrOpcode::kFloat64Equal:
        cont->OverwriteAndNegateIfEqual(kEqual);
        return VisitFloat64Compare(selector, value, cont);
      case IrOpcode::kFloat64LessThan:
        cont->OverwriteAndNegateIfEqual(kUnsignedLessThan);
        return VisitFloat64Compare(selector, value, cont);
      case IrOpcode::kFloat64LessThanOrEqual:
        cont->OverwriteAndNegateIfEqual(kUnsignedLessThanOrEqual);
        return VisitFloat64Compare(selector, value, cont);
      case IrOpcode::kProjection:
        // Check if this is the overflow output projection of an
        // <Operation>WithOverflow node.
        if (ProjectionIndexOf(value->op()) == 1u) {
          // We cannot combine the <Operation>WithOverflow with this branch
          // unless the 0th projection (the use of the actual value of the
1674
          // <Operation> is either nullptr, which means there's no use of the
1675 1676 1677 1678
          // actual value, or was already defined, which means it is scheduled
          // *AFTER* this branch).
          Node* const node = value->InputAt(0);
          Node* const result = NodeProperties::FindProjection(node, 0);
1679
          if (result == nullptr || selector->IsDefined(result)) {
1680 1681 1682 1683 1684 1685 1686 1687 1688 1689
            switch (node->opcode()) {
              case IrOpcode::kInt32AddWithOverflow:
                cont->OverwriteAndNegateIfEqual(kOverflow);
                return VisitBinop<Int32BinopMatcher>(
                    selector, node, kPPC_AddWithOverflow32, kInt16Imm, cont);
              case IrOpcode::kInt32SubWithOverflow:
                cont->OverwriteAndNegateIfEqual(kOverflow);
                return VisitBinop<Int32BinopMatcher>(selector, node,
                                                     kPPC_SubWithOverflow32,
                                                     kInt16Imm_Negate, cont);
1690 1691 1692
              case IrOpcode::kInt32MulWithOverflow:
                cont->OverwriteAndNegateIfEqual(kNotEqual);
                return EmitInt32MulWithOverflow(selector, node, cont);
1693 1694 1695 1696 1697 1698 1699 1700 1701 1702
#if V8_TARGET_ARCH_PPC64
              case IrOpcode::kInt64AddWithOverflow:
                cont->OverwriteAndNegateIfEqual(kOverflow);
                return VisitBinop<Int64BinopMatcher>(selector, node, kPPC_Add,
                                                     kInt16Imm, cont);
              case IrOpcode::kInt64SubWithOverflow:
                cont->OverwriteAndNegateIfEqual(kOverflow);
                return VisitBinop<Int64BinopMatcher>(selector, node, kPPC_Sub,
                                                     kInt16Imm_Negate, cont);
#endif
1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750
              default:
                break;
            }
          }
        }
        break;
      case IrOpcode::kInt32Sub:
        return VisitWord32Compare(selector, value, cont);
      case IrOpcode::kWord32And:
        // TODO(mbandy): opportunity for rlwinm?
        return VisitWordCompare(selector, value, kPPC_Tst32, cont, true,
                                kInt16Imm_Unsigned);
// TODO(mbrandy): Handle?
// case IrOpcode::kInt32Add:
// case IrOpcode::kWord32Or:
// case IrOpcode::kWord32Xor:
// case IrOpcode::kWord32Sar:
// case IrOpcode::kWord32Shl:
// case IrOpcode::kWord32Shr:
// case IrOpcode::kWord32Ror:
#if V8_TARGET_ARCH_PPC64
      case IrOpcode::kInt64Sub:
        return VisitWord64Compare(selector, value, cont);
      case IrOpcode::kWord64And:
        // TODO(mbandy): opportunity for rldic?
        return VisitWordCompare(selector, value, kPPC_Tst64, cont, true,
                                kInt16Imm_Unsigned);
// TODO(mbrandy): Handle?
// case IrOpcode::kInt64Add:
// case IrOpcode::kWord64Or:
// case IrOpcode::kWord64Xor:
// case IrOpcode::kWord64Sar:
// case IrOpcode::kWord64Shl:
// case IrOpcode::kWord64Shr:
// case IrOpcode::kWord64Ror:
#endif
      default:
        break;
    }
  }

  // Branch could not be combined with a compare, emit compare against 0.
  PPCOperandGenerator g(selector);
  VisitCompare(selector, opcode, g.UseRegister(value), g.TempImmediate(0),
               cont);
}


1751 1752
void VisitWord32CompareZero(InstructionSelector* selector, Node* user,
                            Node* value, FlagsContinuation* cont) {
1753 1754 1755 1756 1757
  VisitWordCompareZero(selector, user, value, kPPC_Cmp32, cont);
}


#if V8_TARGET_ARCH_PPC64
1758 1759
void VisitWord64CompareZero(InstructionSelector* selector, Node* user,
                            Node* value, FlagsContinuation* cont) {
1760 1761 1762 1763
  VisitWordCompareZero(selector, user, value, kPPC_Cmp64, cont);
}
#endif

1764 1765
}  // namespace

1766 1767 1768 1769 1770 1771 1772

void InstructionSelector::VisitBranch(Node* branch, BasicBlock* tbranch,
                                      BasicBlock* fbranch) {
  FlagsContinuation cont(kNotEqual, tbranch, fbranch);
  VisitWord32CompareZero(this, branch, branch->InputAt(0), &cont);
}

1773
void InstructionSelector::VisitDeoptimizeIf(Node* node) {
1774 1775
  FlagsContinuation cont = FlagsContinuation::ForDeoptimize(
      kNotEqual, DeoptimizeReasonOf(node->op()), node->InputAt(1));
1776 1777 1778 1779
  VisitWord32CompareZero(this, node, node->InputAt(0), &cont);
}

void InstructionSelector::VisitDeoptimizeUnless(Node* node) {
1780 1781
  FlagsContinuation cont = FlagsContinuation::ForDeoptimize(
      kEqual, DeoptimizeReasonOf(node->op()), node->InputAt(1));
1782 1783
  VisitWord32CompareZero(this, node, node->InputAt(0), &cont);
}
1784

1785
void InstructionSelector::VisitSwitch(Node* node, const SwitchInfo& sw) {
1786 1787 1788
  PPCOperandGenerator g(this);
  InstructionOperand value_operand = g.UseRegister(node->InputAt(0));

1789 1790
  // Emit either ArchTableSwitch or ArchLookupSwitch.
  size_t table_space_cost = 4 + sw.value_range;
1791
  size_t table_time_cost = 3;
1792 1793 1794
  size_t lookup_space_cost = 3 + 2 * sw.case_count;
  size_t lookup_time_cost = sw.case_count;
  if (sw.case_count > 0 &&
1795 1796
      table_space_cost + 3 * table_time_cost <=
          lookup_space_cost + 3 * lookup_time_cost &&
1797
      sw.min_value > std::numeric_limits<int32_t>::min()) {
1798
    InstructionOperand index_operand = value_operand;
1799
    if (sw.min_value) {
1800
      index_operand = g.TempRegister();
1801
      Emit(kPPC_Sub, index_operand, value_operand,
1802
           g.TempImmediate(sw.min_value));
1803
    }
1804 1805
    // Generate a table lookup.
    return EmitTableSwitch(sw, index_operand);
1806 1807 1808
  }

  // Generate a sequence of conditional jumps.
1809
  return EmitLookupSwitch(sw, value_operand);
1810 1811 1812
}


1813
void InstructionSelector::VisitWord32Equal(Node* const node) {
1814
  FlagsContinuation cont = FlagsContinuation::ForSet(kEqual, node);
1815 1816 1817 1818 1819 1820 1821 1822 1823
  Int32BinopMatcher m(node);
  if (m.right().Is(0)) {
    return VisitWord32CompareZero(this, m.node(), m.left().node(), &cont);
  }
  VisitWord32Compare(this, node, &cont);
}


void InstructionSelector::VisitInt32LessThan(Node* node) {
1824
  FlagsContinuation cont = FlagsContinuation::ForSet(kSignedLessThan, node);
1825 1826 1827 1828 1829
  VisitWord32Compare(this, node, &cont);
}


void InstructionSelector::VisitInt32LessThanOrEqual(Node* node) {
1830 1831
  FlagsContinuation cont =
      FlagsContinuation::ForSet(kSignedLessThanOrEqual, node);
1832 1833 1834 1835 1836
  VisitWord32Compare(this, node, &cont);
}


void InstructionSelector::VisitUint32LessThan(Node* node) {
1837
  FlagsContinuation cont = FlagsContinuation::ForSet(kUnsignedLessThan, node);
1838 1839 1840 1841 1842
  VisitWord32Compare(this, node, &cont);
}


void InstructionSelector::VisitUint32LessThanOrEqual(Node* node) {
1843 1844
  FlagsContinuation cont =
      FlagsContinuation::ForSet(kUnsignedLessThanOrEqual, node);
1845 1846 1847 1848 1849 1850
  VisitWord32Compare(this, node, &cont);
}


#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitWord64Equal(Node* const node) {
1851
  FlagsContinuation cont = FlagsContinuation::ForSet(kEqual, node);
1852 1853 1854 1855 1856 1857 1858 1859 1860
  Int64BinopMatcher m(node);
  if (m.right().Is(0)) {
    return VisitWord64CompareZero(this, m.node(), m.left().node(), &cont);
  }
  VisitWord64Compare(this, node, &cont);
}


void InstructionSelector::VisitInt64LessThan(Node* node) {
1861
  FlagsContinuation cont = FlagsContinuation::ForSet(kSignedLessThan, node);
1862 1863 1864 1865 1866
  VisitWord64Compare(this, node, &cont);
}


void InstructionSelector::VisitInt64LessThanOrEqual(Node* node) {
1867 1868
  FlagsContinuation cont =
      FlagsContinuation::ForSet(kSignedLessThanOrEqual, node);
1869 1870 1871 1872
  VisitWord64Compare(this, node, &cont);
}


1873
void InstructionSelector::VisitUint64LessThan(Node* node) {
1874
  FlagsContinuation cont = FlagsContinuation::ForSet(kUnsignedLessThan, node);
1875 1876 1877 1878
  VisitWord64Compare(this, node, &cont);
}


1879
void InstructionSelector::VisitUint64LessThanOrEqual(Node* node) {
1880 1881
  FlagsContinuation cont =
      FlagsContinuation::ForSet(kUnsignedLessThanOrEqual, node);
1882 1883 1884 1885
  VisitWord64Compare(this, node, &cont);
}
#endif

1886 1887 1888 1889 1890 1891 1892 1893 1894
void InstructionSelector::VisitInt32MulWithOverflow(Node* node) {
  if (Node* ovf = NodeProperties::FindProjection(node, 1)) {
    FlagsContinuation cont = FlagsContinuation::ForSet(kNotEqual, ovf);
    return EmitInt32MulWithOverflow(this, node, &cont);
  }
  FlagsContinuation cont;
  EmitInt32MulWithOverflow(this, node, &cont);
}

1895

1896
void InstructionSelector::VisitFloat32Equal(Node* node) {
1897
  FlagsContinuation cont = FlagsContinuation::ForSet(kEqual, node);
1898 1899 1900 1901 1902
  VisitFloat32Compare(this, node, &cont);
}


void InstructionSelector::VisitFloat32LessThan(Node* node) {
1903
  FlagsContinuation cont = FlagsContinuation::ForSet(kUnsignedLessThan, node);
1904 1905 1906 1907 1908
  VisitFloat32Compare(this, node, &cont);
}


void InstructionSelector::VisitFloat32LessThanOrEqual(Node* node) {
1909 1910
  FlagsContinuation cont =
      FlagsContinuation::ForSet(kUnsignedLessThanOrEqual, node);
1911 1912 1913 1914
  VisitFloat32Compare(this, node, &cont);
}


1915
void InstructionSelector::VisitFloat64Equal(Node* node) {
1916
  FlagsContinuation cont = FlagsContinuation::ForSet(kEqual, node);
1917 1918 1919 1920 1921
  VisitFloat64Compare(this, node, &cont);
}


void InstructionSelector::VisitFloat64LessThan(Node* node) {
1922
  FlagsContinuation cont = FlagsContinuation::ForSet(kUnsignedLessThan, node);
1923 1924 1925 1926 1927
  VisitFloat64Compare(this, node, &cont);
}


void InstructionSelector::VisitFloat64LessThanOrEqual(Node* node) {
1928 1929
  FlagsContinuation cont =
      FlagsContinuation::ForSet(kUnsignedLessThanOrEqual, node);
1930 1931 1932 1933
  VisitFloat64Compare(this, node, &cont);
}


1934 1935 1936
void InstructionSelector::EmitPrepareArguments(
    ZoneVector<PushParameter>* arguments, const CallDescriptor* descriptor,
    Node* node) {
1937
  PPCOperandGenerator g(this);
1938 1939 1940 1941

  // Prepare for C function call.
  if (descriptor->IsCFunctionCall()) {
    Emit(kArchPrepareCallCFunction |
1942
             MiscField::encode(static_cast<int>(descriptor->ParameterCount())),
1943 1944 1945 1946
         0, nullptr, 0, nullptr);

    // Poke any stack arguments.
    int slot = kStackFrameExtraParamSlot;
1947 1948
    for (PushParameter input : (*arguments)) {
      Emit(kPPC_StoreToStackSlot, g.NoOutput(), g.UseRegister(input.node()),
1949 1950 1951 1952 1953
           g.TempImmediate(slot));
      ++slot;
    }
  } else {
    // Push any stack arguments.
1954
    int num_slots = static_cast<int>(descriptor->StackParameterCount());
1955
    int slot = 0;
1956
    for (PushParameter input : (*arguments)) {
1957
      if (slot == 0) {
1958 1959
        DCHECK(input.node());
        Emit(kPPC_PushFrame, g.NoOutput(), g.UseRegister(input.node()),
1960 1961
             g.TempImmediate(num_slots));
      } else {
1962
        // Skip any alignment holes in pushed nodes.
1963 1964
        if (input.node()) {
          Emit(kPPC_StoreToStackSlot, g.NoOutput(), g.UseRegister(input.node()),
1965 1966
               g.TempImmediate(slot));
        }
1967 1968 1969
      }
      ++slot;
    }
1970
  }
1971 1972 1973
}


1974
bool InstructionSelector::IsTailCallAddressImmediate() { return false; }
1975

1976
int InstructionSelector::GetTempsCountForTailCallFromJSFunction() { return 3; }
1977

1978 1979
void InstructionSelector::VisitFloat64ExtractLowWord32(Node* node) {
  PPCOperandGenerator g(this);
1980
  Emit(kPPC_DoubleExtractLowWord32, g.DefineAsRegister(node),
1981 1982 1983 1984 1985 1986
       g.UseRegister(node->InputAt(0)));
}


void InstructionSelector::VisitFloat64ExtractHighWord32(Node* node) {
  PPCOperandGenerator g(this);
1987
  Emit(kPPC_DoubleExtractHighWord32, g.DefineAsRegister(node),
1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998
       g.UseRegister(node->InputAt(0)));
}


void InstructionSelector::VisitFloat64InsertLowWord32(Node* node) {
  PPCOperandGenerator g(this);
  Node* left = node->InputAt(0);
  Node* right = node->InputAt(1);
  if (left->opcode() == IrOpcode::kFloat64InsertHighWord32 &&
      CanCover(node, left)) {
    left = left->InputAt(1);
1999
    Emit(kPPC_DoubleConstruct, g.DefineAsRegister(node), g.UseRegister(left),
2000 2001 2002
         g.UseRegister(right));
    return;
  }
2003
  Emit(kPPC_DoubleInsertLowWord32, g.DefineSameAsFirst(node),
2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014
       g.UseRegister(left), g.UseRegister(right));
}


void InstructionSelector::VisitFloat64InsertHighWord32(Node* node) {
  PPCOperandGenerator g(this);
  Node* left = node->InputAt(0);
  Node* right = node->InputAt(1);
  if (left->opcode() == IrOpcode::kFloat64InsertLowWord32 &&
      CanCover(node, left)) {
    left = left->InputAt(1);
2015
    Emit(kPPC_DoubleConstruct, g.DefineAsRegister(node), g.UseRegister(right),
2016 2017 2018
         g.UseRegister(left));
    return;
  }
2019
  Emit(kPPC_DoubleInsertHighWord32, g.DefineSameAsFirst(node),
2020 2021 2022
       g.UseRegister(left), g.UseRegister(right));
}

2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045
void InstructionSelector::VisitAtomicLoad(Node* node) {
  LoadRepresentation load_rep = LoadRepresentationOf(node->op());
  PPCOperandGenerator g(this);
  Node* base = node->InputAt(0);
  Node* index = node->InputAt(1);
  ArchOpcode opcode = kArchNop;
  switch (load_rep.representation()) {
    case MachineRepresentation::kWord8:
      opcode = load_rep.IsSigned() ? kAtomicLoadInt8 : kAtomicLoadUint8;
      break;
    case MachineRepresentation::kWord16:
      opcode = load_rep.IsSigned() ? kAtomicLoadInt16 : kAtomicLoadUint16;
      break;
    case MachineRepresentation::kWord32:
      opcode = kAtomicLoadWord32;
      break;
    default:
      UNREACHABLE();
      return;
  }
  Emit(opcode | AddressingModeField::encode(kMode_MRR),
      g.DefineAsRegister(node), g.UseRegister(base), g.UseRegister(index));
}
2046

2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077
void InstructionSelector::VisitAtomicStore(Node* node) {
  MachineRepresentation rep = AtomicStoreRepresentationOf(node->op());
  PPCOperandGenerator g(this);
  Node* base = node->InputAt(0);
  Node* index = node->InputAt(1);
  Node* value = node->InputAt(2);
  ArchOpcode opcode = kArchNop;
  switch (rep) {
    case MachineRepresentation::kWord8:
      opcode = kAtomicStoreWord8;
      break;
    case MachineRepresentation::kWord16:
      opcode = kAtomicStoreWord16;
      break;
    case MachineRepresentation::kWord32:
      opcode = kAtomicStoreWord32;
      break;
    default:
      UNREACHABLE();
      return;
  }

  InstructionOperand inputs[4];
  size_t input_count = 0;
  inputs[input_count++] = g.UseUniqueRegister(base);
  inputs[input_count++] = g.UseUniqueRegister(index);
  inputs[input_count++] = g.UseUniqueRegister(value);
  Emit(opcode | AddressingModeField::encode(kMode_MRR),
      0, nullptr, input_count, inputs);
}

2078 2079 2080
// static
MachineOperatorBuilder::Flags
InstructionSelector::SupportedMachineOperatorFlags() {
2081 2082
  return MachineOperatorBuilder::kFloat32RoundDown |
         MachineOperatorBuilder::kFloat64RoundDown |
2083
         MachineOperatorBuilder::kFloat32RoundUp |
2084
         MachineOperatorBuilder::kFloat64RoundUp |
2085
         MachineOperatorBuilder::kFloat32RoundTruncate |
2086
         MachineOperatorBuilder::kFloat64RoundTruncate |
2087
         MachineOperatorBuilder::kFloat64RoundTiesAway |
2088 2089
         MachineOperatorBuilder::kWord32Popcnt |
         MachineOperatorBuilder::kWord64Popcnt;
2090 2091 2092
  // We omit kWord32ShiftIsSafe as s[rl]w use 0x3f as a mask rather than 0x1f.
}

2093 2094 2095 2096 2097 2098 2099
// static
MachineOperatorBuilder::AlignmentRequirements
InstructionSelector::AlignmentRequirements() {
  return MachineOperatorBuilder::AlignmentRequirements::
      FullUnalignedAccessSupport();
}

2100 2101 2102
}  // namespace compiler
}  // namespace internal
}  // namespace v8