- 31 May, 2017 1 commit
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neis authored
Instead of allocating and embedding certain heap numbers into the code during code assembly, emit dummies but record the allocation requests. Later then, in Assembler::GetCode, allocate the heap numbers and patch the code by replacing the dummies with the actual objects. The RelocInfos for the embedded objects are already recorded correctly when emitting the dummies. R=jarin@chromium.org BUG=v8:6048 Review-Url: https://codereview.chromium.org/2900683002 Cr-Commit-Position: refs/heads/master@{#45635}
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- 16 May, 2017 1 commit
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bbudge authored
- Adds vdup.<size> Dd/Qd, Dm[i] instruction. - Adds vsli, vsri instructions. - Changes VMovExtended to use these to avoid moves to core registers. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2868603002 Cr-Commit-Position: refs/heads/master@{#45351}
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- 24 Apr, 2017 1 commit
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bbudge authored
- Adds new F32x4AddHoriz, I32x4AddHoriz, etc. to WASM opcodes. - Implements them for ARM. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2804883008 Cr-Commit-Position: refs/heads/master@{#44812}
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- 10 Apr, 2017 3 commits
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bbudge authored
LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2797923006 Cr-Original-Commit-Position: refs/heads/master@{#44536} Committed: https://chromium.googlesource.com/v8/v8/+/6588187ae3acaa5b40762c539ee9fe355551bea3 Review-Url: https://codereview.chromium.org/2797923006 Cr-Commit-Position: refs/heads/master@{#44540}
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bbudge authored
Revert of [ARM] Implement D-register versions of vzip, vuzp, and vtrn. (patchset #4 id:60001 of https://codereview.chromium.org/2797923006/ ) Reason for revert: Breaks: http://builders/V8%20Arm%20-%20debug/builds/2751 Original issue's description: > [ARM] Implement D-register versions of vzip, vuzp, and vtrn. > > LOG=N > BUG=v8:6020 > > Review-Url: https://codereview.chromium.org/2797923006 > Cr-Commit-Position: refs/heads/master@{#44536} > Committed: https://chromium.googlesource.com/v8/v8/+/6588187ae3acaa5b40762c539ee9fe355551bea3 TBR=martyn.capewell@arm.com,bmeurer@chromium.org # Skipping CQ checks because original CL landed less than 1 days ago. NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG=v8:6020 Review-Url: https://codereview.chromium.org/2810703003 Cr-Commit-Position: refs/heads/master@{#44537}
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bbudge authored
LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2797923006 Cr-Commit-Position: refs/heads/master@{#44536}
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- 27 Mar, 2017 1 commit
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bbudge authored
- Fixes vmovl for widening 16 to 32, 32 to 64. - Adds vqmovn. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2773303002 Cr-Commit-Position: refs/heads/master@{#44156}
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- 14 Mar, 2017 1 commit
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bbudge authored
- Implements vuzp, vtrn instructions for q-registers. - Refactors vmvn, vswp to use common unary op helper fn. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2739033002 Cr-Commit-Position: refs/heads/master@{#43795}
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- 02 Mar, 2017 1 commit
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bbudge authored
- Implements Select instructions using a single ARM vbsl instruction. - Renames boolean machine operators to match renamed S1xN machine types. - Implements S1xN vector logical ops, AND, OR, XOR, NOT for ARM. - Implements S1xN AnyTrue, AllTrue ops for ARM. - Eliminates unused SIMD op categories in opcodes.h. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2711863002 Cr-Commit-Position: refs/heads/master@{#43556}
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- 28 Feb, 2017 1 commit
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Marja Hölttä authored
The x64 side is included in https://chromium-review.googlesource.com/c/444226/ BUG=v8:5294 Change-Id: Ie255604c5e38c72e3c2b76e1ca3557a5fde108ee Reviewed-on: https://chromium-review.googlesource.com/446394Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Reviewed-by: Yang Guo <yangguo@chromium.org> Commit-Queue: Marja Hölttä <marja@chromium.org> Cr-Commit-Position: refs/heads/master@{#43481}
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- 01 Feb, 2017 1 commit
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bbudge authored
- Adds vqadd.s/u, vqsub.s/u for all integer lane sizes. - Refactors disassembler and simulator, using switches instead of long if-else chains. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2649323012 Cr-Commit-Position: refs/heads/master@{#42865}
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- 23 Jan, 2017 1 commit
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bbudge authored
LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2629223005 Cr-Commit-Position: refs/heads/master@{#42610}
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- 16 Jan, 2017 1 commit
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bbudge authored
- Adds vmin, vmax for FP and integer vectors, both signed and unsigned. - Regularizes switching logic in disasm and simulator for special codes 4 and 6. - Factors vrecpe, vrsqrte, vrecps, vrsqrts into helper fns. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2623993006 Cr-Commit-Position: refs/heads/master@{#42385}
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- 13 Jan, 2017 1 commit
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bbudge authored
The simulator implements these exactly, but on ARM hardware, the estimates are not exact, so CHECK_EQ will fail. This CL adds a tolerance to the checks. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2628153003 Cr-Commit-Position: refs/heads/master@{#42320}
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- 12 Jan, 2017 2 commits
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bbudge authored
LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2620343002 Cr-Commit-Position: refs/heads/master@{#42273}
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bbudge authored
- Floating point, signed, and unsigned. - Disassembler, simulator support too. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2602293002 Cr-Commit-Position: refs/heads/master@{#42262}
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- 10 Jan, 2017 1 commit
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bbudge authored
- Disassembler, simulator support too. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2600153002 Cr-Commit-Position: refs/heads/master@{#42176}
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- 20 Dec, 2016 1 commit
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bbudge authored
LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2593443002 Cr-Commit-Position: refs/heads/master@{#41859}
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- 17 Dec, 2016 1 commit
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bbudge authored
- Adds vabs, vneg, vmul, vext, vzip, vrev instructions. - Adds Swizzle function to macro assembler. - Simplifies if-else logic in disassembler, simulator, for Neon special. - Some refactoring of Neon assembler, macro-assembler tests. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2579913002 Cr-Commit-Position: refs/heads/master@{#41781}
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- 15 Dec, 2016 1 commit
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bbudge authored
- Adds NEON instructions to assembler, disassembler, simulator. - Adds ExtractLane, ReplaceLane functions to macro assembler. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2546933002 Cr-Commit-Position: refs/heads/master@{#41737}
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- 30 Nov, 2016 1 commit
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bbudge authored
Attempt to fix or get insight into failing vswp test on V8 ARM bot. LOG=N BUG= Review-Url: https://codereview.chromium.org/2539533005 Cr-Commit-Position: refs/heads/master@{#41397}
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- 25 Nov, 2016 1 commit
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bbudge authored
- Adds vmov, vswp instructions for QwNeonRegisters. - Refactors existing vswp implementation, moves non-Neon adaption to MacroAssembler. - Adds simd128 support to CodeGenerator AssembleMove, AssembleSwap. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2523933002 Cr-Commit-Position: refs/heads/master@{#41291}
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- 11 Nov, 2016 1 commit
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ulan authored
BUG=v8:5614 Review-Url: https://codereview.chromium.org/2493173002 Cr-Commit-Position: refs/heads/master@{#40916}
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- 23 Sep, 2016 1 commit
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jacob.bramley authored
CpuFeatures::IsSupported(feature) indicates that the feature is available on the target. AssemblerBase::IsEnabled(feature) indicates that we've checked for support (using CpuFeatureScope). The main benefit is that we can test on (for example) ARMv8, but have some assurance that we won't generate ARMv8 instructions on ARMv7 targets. This patch simply cleans up the usage, which had become inconsistent. The instruction emission functions now check not only that their dependent features are supported, but also that we've verified that using CpuFeatureScope. BUG= Review-Url: https://codereview.chromium.org/2360243002 Cr-Commit-Position: refs/heads/master@{#39676}
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- 08 Sep, 2016 2 commits
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rodolph.perfetta authored
The test was using some callee saved registers but tests don't save those. BUG=v8:5354 Review-Url: https://codereview.chromium.org/2322923002 Cr-Commit-Position: refs/heads/master@{#39275}
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martyn.capewell authored
Reason for revert: Breaks g++ build. Original issue's description: > [turbofan] ARM: Implement vswp and use in gap resolver > > Use vswp to switch double-precision registers in the gap resolver, with fall > back temp register-based code if NEON is not available. > > BUG= > > Committed: https://crrev.com/2837c2e65a2ee5b9fc610f30ce1215f52323ecbd > Cr-Commit-Position: refs/heads/master@{#39209} BUG= Review-Url: https://codereview.chromium.org/2314043002 Cr-Commit-Position: refs/heads/master@{#39264}
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- 06 Sep, 2016 4 commits
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machenbach authored
Revert of [turbofan] ARM: Implement vswp and use in gap resolver (patchset #2 id:20001 of https://codereview.chromium.org/2313803003/ ) Reason for revert: Breaks arm compilation: https://build.chromium.org/p/client.v8.ports/builders/V8%20Arm%20-%20builder/builds/3549 Original issue's description: > [turbofan] ARM: Implement vswp and use in gap resolver > > Use vswp to switch double-precision registers in the gap resolver, with fall > back temp register-based code if NEON is not available. > > BUG= > > Committed: https://crrev.com/2837c2e65a2ee5b9fc610f30ce1215f52323ecbd > Cr-Commit-Position: refs/heads/master@{#39209} TBR=bmeurer@chromium.org,epertoso@chromium.org,martyn.capewell@arm.com # Skipping CQ checks because original CL landed less than 1 days ago. NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG= Review-Url: https://codereview.chromium.org/2314003003 Cr-Commit-Position: refs/heads/master@{#39210}
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martyn.capewell authored
Use vswp to switch double-precision registers in the gap resolver, with fall back temp register-based code if NEON is not available. BUG= Review-Url: https://codereview.chromium.org/2313803003 Cr-Commit-Position: refs/heads/master@{#39209}
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jacob.bramley authored
ARMv8 can use vminnm and vmaxnm to handle most inputs. Other platforms use an implementation similar to what was there before, except that out-of-line code is used for the uncommon cases. BUG= Review-Url: https://codereview.chromium.org/2313863003 Cr-Commit-Position: refs/heads/master@{#39202}
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jacob.bramley authored
These are ARMv8 instructions that will be used in a follow-up patch. BUG= Review-Url: https://codereview.chromium.org/2273003002 Cr-Commit-Position: refs/heads/master@{#39193}
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- 27 Jul, 2016 1 commit
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jacob.bramley authored
All supported ARM targets support unaligned accesses for integer accesses. This patch removes the remnants of support for older targets. BUG=v8:5077 Review-Url: https://codereview.chromium.org/2184823002 Cr-Commit-Position: refs/heads/master@{#38099}
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- 12 May, 2016 1 commit
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jacob.bramley authored
The usat instruction is available from ARMv6, so there's no need to check for the ARMv7 feature before using it. ARMv6 is the oldest supported architecture in V8. Correcting this allows the removal of a special case for predictable code size. BUG= Review-Url: https://codereview.chromium.org/1974903002 Cr-Commit-Position: refs/heads/master@{#36218}
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- 06 Apr, 2016 1 commit
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jacob.bramley authored
BUG= Review URL: https://codereview.chromium.org/1862993002 Cr-Commit-Position: refs/heads/master@{#35292}
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- 14 Mar, 2016 1 commit
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martyn.capewell authored
Reduce the amount of code generated for OutOfLineLoadFloat* by computing sqrt(-1) rather than move the NaN as an immediate. Add support for single precision floating point immediate moves to enable this. BUG= Review URL: https://codereview.chromium.org/1758003003 Cr-Commit-Position: refs/heads/master@{#34746}
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- 10 Mar, 2016 1 commit
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jacob.bramley authored
Only CPSR_f is supported, and then only for the flags that we actually simulate (NZCV). This isn't currently used, but will be useful for some tests. BUG= Review URL: https://codereview.chromium.org/1776933003 Cr-Commit-Position: refs/heads/master@{#34662}
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- 16 Feb, 2016 1 commit
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rodolph.perfetta authored
Let me know if this is not the right approach Review URL: https://codereview.chromium.org/1698483002 Cr-Commit-Position: refs/heads/master@{#34028}
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- 09 Dec, 2015 1 commit
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jochen authored
Embedders still can use those APIs by default test-api.cc still has an exception to use the old APIs... BUG=v8:4143 R=vogelheim@chromium.org LOG=n Review URL: https://codereview.chromium.org/1505803004 Cr-Commit-Position: refs/heads/master@{#32701}
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- 07 Dec, 2015 1 commit
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bmeurer authored
The test expectations should fail consistently in both release and debug builds. DCHECK is only meant for debug-only checks in production code. R=yangguo@chromium.org Review URL: https://codereview.chromium.org/1506753002 Cr-Commit-Position: refs/heads/master@{#32639}
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- 25 Nov, 2015 1 commit
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ahaas authored
The Float32RoundTruncate operator rounds float32 numbers towards zero. The operator is currently implemented on x64, ia32, arm, and arm64. Additionally I added support for the float32 vrintz, vrintn, and vrinta instructions to the arm simulator. R=titzer@chromium.org Review URL: https://codereview.chromium.org/1468303005 Cr-Commit-Position: refs/heads/master@{#32301}
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- 23 Nov, 2015 1 commit
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jochen authored
BUG=2487 R=ulan@chromium.org LOG=n Review URL: https://codereview.chromium.org/1457223005 Cr-Commit-Position: refs/heads/master@{#32164}
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