[ARM] Add fp version of vceq to assembler, disassembler, and simulator.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2593443002
Cr-Commit-Position: refs/heads/master@{#41859}

src/arm/assembler-arm.cc

@@ -4257,6 +4257,21 @@ void Assembler::vtst(NeonSize size, QwNeonRegister dst,
        n * B7 | B6 | m * B5 | B4 | vm);
 }
 
+void Assembler::vceq(const QwNeonRegister dst, const QwNeonRegister src1,
+                     const QwNeonRegister src2) {
+  DCHECK(IsEnabled(NEON));
+  // Qd = vceq(Qn, Qm) SIMD integer compare equal.
+  // Instruction details available in ARM DDI 0406C.b, A8-844.
+  int vd, d;
+  dst.split_code(&vd, &d);
+  int vn, n;
+  src1.split_code(&vn, &n);
+  int vm, m;
+  src2.split_code(&vm, &m);
+  emit(0x1E4U * B23 | d * B22 | vn * B16 | vd * B12 | 0xe * B8 | n * B7 | B6 |
+       m * B5 | vm);
+}
+
 void Assembler::vceq(NeonSize size, QwNeonRegister dst,
                      const QwNeonRegister src1, const QwNeonRegister src2) {
   DCHECK(IsEnabled(NEON));

src/arm/assembler-arm.h

@@ -1382,6 +1382,8 @@ class Assembler : public AssemblerBase {
             const QwNeonRegister src2);
   void vtst(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1,
             const QwNeonRegister src2);
+  void vceq(const QwNeonRegister dst, const QwNeonRegister src1,
+            const QwNeonRegister src2);
   void vceq(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1,
             const QwNeonRegister src2);
   void vbsl(const QwNeonRegister dst, const QwNeonRegister src1,

src/arm/disasm-arm.cc

@@ -1892,6 +1892,14 @@ void Decoder::DecodeSpecialCondition(Instruction* instr) {
         // vmul.i<size> Qd, Qm, Qn.
         out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                     "vmul.i%d q%d, q%d, q%d", size, Vd, Vn, Vm);
+      } else if (instr->Bits(21, 20) == 0 && instr->Bits(11, 8) == 0xe &&
+                 instr->Bit(4) == 0) {
+        int Vd = instr->VFPDRegValue(kSimd128Precision);
+        int Vm = instr->VFPMRegValue(kSimd128Precision);
+        int Vn = instr->VFPNRegValue(kSimd128Precision);
+        // vceq.f32 Qd, Qm, Qn.
+        out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
+                                    "vceq.f32 q%d, q%d, q%d", Vd, Vn, Vm);
       } else {
         Unknown(instr);
       }

src/arm/simulator-arm.cc

@@ -3983,6 +3983,21 @@ void Simulator::DecodeSpecialCondition(Instruction* instr) {
             break;
         }
         set_q_register(Vd, src1);
+      } else if (instr->Bits(21, 20) == 0 && instr->Bits(11, 8) == 0xe &&
+                 instr->Bit(4) == 0) {
+        int Vd = instr->VFPDRegValue(kSimd128Precision);
+        int Vm = instr->VFPMRegValue(kSimd128Precision);
+        int Vn = instr->VFPNRegValue(kSimd128Precision);
+        uint32_t src1[4], src2[4];
+        get_q_register(Vn, src1);
+        get_q_register(Vm, src2);
+        for (int i = 0; i < 4; i++) {
+          src1[i] = bit_cast<float>(src1[i]) == bit_cast<float>(src2[i])
+                        ? 0xFFFFFFFF
+                        : 0;
+        }
+        set_q_register(Vd, src1);
+
       } else {
         UNIMPLEMENTED();
       }
@@ -4495,6 +4510,8 @@ void Simulator::DecodeSpecialCondition(Instruction* instr) {
         } else {
           UNIMPLEMENTED();
         }
+      } else {
+        UNIMPLEMENTED();
       }
       break;
     case 8:

test/cctest/test-assembler-arm.cc

@@ -1289,7 +1289,7 @@ TEST(15) {
     uint32_t vadd8[4], vadd16[4], vadd32[4];
     uint32_t vsub8[4], vsub16[4], vsub32[4];
     uint32_t vmul8[4], vmul16[4], vmul32[4];
-    uint32_t vtst[4], vceq[4], vbsl[4];
+    uint32_t vtst[4], vceq[4], vceqf[4], vbsl[4];
     uint32_t vext[4];
     uint32_t vzip8a[4], vzip8b[4], vzip16a[4], vzip16b[4], vzip32a[4],
         vzip32b[4];
@@ -1482,6 +1482,13 @@ TEST(15) {
     __ vmul(q1, q1, q0);
     __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vmulf))));
     __ vst1(Neon8, NeonListOperand(q1), NeonMemOperand(r4));
+    // vceq (float).
+    __ vmov(s4, 1.0);
+    __ vdup(q0, s4);
+    __ vdup(q1, s4);
+    __ vceq(q1, q1, q0);
+    __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vceqf))));
+    __ vst1(Neon8, NeonListOperand(q1), NeonMemOperand(r4));
 
     // vadd (integer).
     __ mov(r4, Operand(0x81));
@@ -1743,6 +1750,7 @@ TEST(15) {
     CHECK_EQ_SPLAT(vaddf, 2.0);
     CHECK_EQ_SPLAT(vsubf, -1.0);
     CHECK_EQ_SPLAT(vmulf, 4.0);
+    CHECK_EQ_SPLAT(vceqf, 0xffffffffu);
     CHECK_EQ_SPLAT(vadd8, 0x03030303u);
     CHECK_EQ_SPLAT(vadd16, 0x00030003u);
     CHECK_EQ_SPLAT(vadd32, 0x00000003u);

test/cctest/test-disasm-arm.cc

@@ -1055,6 +1055,8 @@ TEST(Neon) {
               "f2142870       vtst.i16 q1, q2, q8");
       COMPARE(vtst(Neon32, q15, q0, q8),
               "f260e870       vtst.i32 q15, q0, q8");
+      COMPARE(vceq(q0, q1, q2),
+              "f2020e44       vceq.f32 q0, q1, q2");
       COMPARE(vceq(Neon8, q0, q1, q2),
               "f3020854       vceq.i8 q0, q1, q2");
       COMPARE(vceq(Neon16, q1, q2, q8),