- 01 Jun, 2021 2 commits
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Milad Fa authored
Port 2b77ca20 Original Commit Message: The upper 32 bits of the 64 bit offset register are not guaranteed to be cleared, so a zero-extension is needed. We already do the zero-extension in the case of explicit bounds checking, but this should also be done if the trap handler is enabled. R=thibaudm@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: Ife3ae4f93b85fe1b2c76fe4b98fa408b5b51ed71 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2929661Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#74886}
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Camillo Bruni authored
Various behaviour preserving changes that make it easier to switch on callee-saved registers without having to land refactoring code at the same time. - Use MaybeStoreRegisters / MaybeRestoreRegisters - Use CallRecordWriteStubSaveRegisters everywhere for now. Eventually this will be replaced by CallRecordWriteStub in places with fixed registers. - Use WriteBarrierDescriptor::ComputeSavedRegisters, which for now returns the same as allocatable_registers Full x64 implementation: https://crrev.com/c/2922604 Bug: v8:11420 Change-Id: I04e6ac2f6333edc91cb1030a0217f59ad441a1d3 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2922250Reviewed-by:
Santiago Aboy Solanes <solanes@chromium.org> Reviewed-by:
Andreas Haas <ahaas@chromium.org> Commit-Queue: Camillo Bruni <cbruni@chromium.org> Cr-Commit-Position: refs/heads/master@{#74876}
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- 26 May, 2021 1 commit
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Junliang Yan authored
Change-Id: I55a80003a148c80f2b7a1f644c127d81963f8ac7 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2918141Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#74789}
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- 25 May, 2021 1 commit
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Junliang Yan authored
Change-Id: Ia709a1c578d05d722690c57ae44019bda4eb8d5d Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2918213 Auto-Submit: Junliang Yan <junyan@redhat.com> Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#74768}
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- 20 May, 2021 1 commit
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Junliang Yan authored
Change-Id: Ia1b8bf3ada1957c27334e98207d57bb2e644ecdd Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2910796 Commit-Queue: Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Auto-Submit: Junliang Yan <junyan@redhat.com> Reviewed-by:
Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#74702}
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- 19 May, 2021 1 commit
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Junliang Yan authored
Change-Id: I1ada6628e8d17d313f6ee73fda40bb867e3e0ee4 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2906013 Commit-Queue: Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Auto-Submit: Junliang Yan <junyan@redhat.com> Reviewed-by:
Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#74680}
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- 12 May, 2021 1 commit
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Milad Fa authored
As mentioned in this CL https://crrev.com/c/2510070, PPC_OWNERS file is the only necessary file applied to all *-ppc* files. Change-Id: I2052186660c6d186e3ead3e8e127a9129814377f Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2892602Reviewed-by:
Junliang Yan <junyan@redhat.com> Reviewed-by:
Ross McIlroy <rmcilroy@chromium.org> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#74536}
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- 29 Apr, 2021 2 commits
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Junliang Yan authored
Change-Id: I294c465230b1c1b8bdb21e8e42bc419c8528d217 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2860742Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#74288}
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Junliang Yan authored
Change-Id: Ia3c703dc47744cffc3f86ec46abb341e6c37590c Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2857637Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#74283}
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- 28 Apr, 2021 1 commit
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Junliang Yan authored
Change-Id: Idf927a4c8bc5e4751e5e8913fe9912fd44001190 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2857854Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#74263}
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- 27 Apr, 2021 1 commit
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Junliang Yan authored
Change-Id: Ib492a0165d8aed748d8ece406bc51931ee577391 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2849179Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#74229}
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- 22 Apr, 2021 1 commit
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Junliang Yan authored
Change-Id: I0277bd7de282449fde232777b0482cc52a2d0ef6 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2844995Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#74129}
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- 15 Apr, 2021 1 commit
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Milad Fa authored
Port 06a2c2e0 Original Commit Message: We currently allow OSR (On-Stack Replacement) of arbitrarily deep return addresses. This is in direct violation of Intel CET's shadow stack, which we plan to enable eventually. This change works around this by postponing OSR until after we return to the old code. The main changes are: - Reserve a slot in Liftoff frames to store the OSR target, - Skip the return address modification, and instead store the new code pointer in the dedicated slot, - Upon returning to the old code, check the slot and do an indirect jump to the new code if needed. CET also prevents indirect jumps to arbitrary locations, so the last point is also a CET violation. Valid indirect jump targets must be marked with the ENDBRANCH instruction, which I will do in a follow-up CL. R=thibaudm@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: Id972de1ba7556474cb00b377ea3a38eb4332eae3 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2828870Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#73984}
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- 15 Mar, 2021 1 commit
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Junliang Yan authored
Port 3e689a7d Original Message: Only support empty exceptions for now. Unpacking i32s, and eventually arbitrary types, will be done in separate CLs. Bug: v8:11453 Change-Id: I4f019330bfb1753b424ef3a8c541054f5fa27e84 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2760777Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#73404}
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- 10 Mar, 2021 1 commit
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Ng Zhi An authored
This is done with a script that does something like: files=$(ag 'v\d\d?x\d\d?[._]?all_?true' -l) sed -i 's/V\(8x16\|16x8\|32x4\|64x2\)\([._]\?\)\([aA]ll_\?[tT]rue\)/I\1\2\3/g' $(files) sed -i 's/v\(8x16\|16x8\|32x4\|64x2\)\([._]\?\)\([aA]ll_\?[tT]rue\)/i\1\2\3/g' $(files) And manual fixups in test-run-wasm-simd.cc and wasm-opcodes-inl.h. Bug: v8:10946 Change-Id: Ib5dad388dd6dd9cd0fb575ad961dffc189a2e6ef Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2740488Reviewed-by:
Bill Budge <bbudge@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#73309}
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- 08 Mar, 2021 1 commit
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Junliang Yan authored
Port c2a1d633 Drive-by: port code-generator-s390.cc changes Change-Id: I2090cf136d62cc9db1f17d158b88a1e58cc430d9 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2740341Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#73273}
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- 26 Feb, 2021 1 commit
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Milad Fa authored
Port 52cc7ba9 Original Commit Message: This renames more fields holding "ValueKind" or methods operating on "ValueKind" to contain "kind" instead of "type". It also renames "is_reference_type" to "is_reference" on both ValueType and ValueKind, as the "_type" prefix is kind of implicit from the argument. R=clemensb@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: I3ab73b31b401ed1e9788df33d998b067280cb52c Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2723251Reviewed-by:
Clemens Backes <clemensb@chromium.org> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#73076}
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- 25 Feb, 2021 1 commit
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Milad Fa authored
Port 47ffa7a5 Original Commit Message: This instruction is not in the final SIMD proposal. R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: I7e701fb6a995fb62737e9473cdf76a33c5518cac Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2716055Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#73061}
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- 24 Feb, 2021 2 commits
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Junliang Yan authored
Port 96a0677a The precise type is only used for validation. For code generation, knowing the kind is more than enough. Hence, only store and pass the ValueKind in Liftoff, and not the full ValueType. Change-Id: Ia3a07df393b2f93d8d8c51bd41b3bd3a3bd6c6fe Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2715987Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#73017}
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Milad Fa authored
Port 31aab838 Original Commit Message: Extract code sequence into macro-assembler for sharing between Liftoff and TurboFan. Relax the register aliasing requirements (remove the DCHECKS), this will not affect codegen for TurboFan since the instruction selector already sets the correct restrictions, but makes it more flexible for use in Liftoff. R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: I729095aae0412fce70ec97a1d7c5f27d32b1a932 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2718143Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#73011}
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- 22 Feb, 2021 3 commits
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Milad Fa authored
Port 8136e399 Original Commit Message: Extract code sequence into macro-assembler for reuse between Liftoff and TurboFan. Small tweaks to macro-assembler functions Pmaddwd and Pmaddubsw to move src1 to dst on SSE when src != dst. TurboFan codegen won't be affected by this since it sets the right restrictions in instruction-selector. R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: Idaff4944dbb1ec5e6d7e798b6255a90744155006 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2713842Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#72928}
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Milad Fa authored
Port 1c507667 Original Commit Message: There is no need for write barriers if the stored value is known to be a Smi. R=clemensb@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: I2b79511b7f2789e6fc95ae5cb349b0f2288822fc Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2712787Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#72918}
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Milad Fa authored
Port a3776a63 Original Commit Message: Backends do not care about the concrete type, they only need to know the "kind" (e.g. "ref" or "i32"). In order to prepare Liftoff to use the value kind instead of the value type for all stored data, this CL moves the kind out of the ValueType and makes it a top-level enum. R=clemensb@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: Ia4111941313037aa1a77f2a0a1536d492ae9dc0b Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2712392Reviewed-by:
Clemens Backes <clemensb@chromium.org> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#72915}
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- 19 Feb, 2021 1 commit
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Milad Fa authored
Port b57a0d19 Original Commit Message: Extract code sequence into macro-assembler for reuse between Liftoff and TurboFan. There is a bit of register-aliasing checking due to the rather strict requirements for the code sequence depending on the CpuFetures that are supported. R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: Ia7c8adf67ea04eda43966effe71919334da10b58 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2705157Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#72876}
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- 16 Feb, 2021 1 commit
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Junliang Yan authored
Port adf035fb Original Commit Message: This CL avoids redundant loads of the instance from the frame by caching it in a register if possible. This register will be the first one to be cleared once we run out of registers (hence it's called a "volatile register"). On local tests, this seems to reduce most redundant loads within a function, and it also reduces the load for the stack check in the function prologue. After the stack check, we need to discard the cached instance though, since the potential runtime call for the stack check might clobber it. This will be addressed in a follow-up CL by re-loading the cached instance after the stack check. This is expected to remove another good chunk of instance loads, because the instance would initially be available in a register when starting the function code. R=clemensb@chromium.org, midawson@redhat.com, mfarazma@redhat.com BUG= LOG=N Change-Id: I3756ce98d4dfefb44c946a4948f1a6dbe0ce44dd Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2698291Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#72791}
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- 11 Feb, 2021 2 commits
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Milad Fa authored
Port 1b81ffb1 Original Commit Message: Other archs will come later. R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: I7a1194c3270486de326b74b63cefc4aded5faff5 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2691028Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#72678}
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Milad Fa authored
Port 66964c51 Original Commit Message: Extract codegen into macro-assembler functions for reuse in Liftoff. Some minor tweaks in I32x4TruncSatF64x2SZero and I32x4TruncSatF64x2UZero to check dst and src overlap and move to scratch/dst accordingly. In TurboFan we can set these restrictions in the instruction-selector, but not in Liftoff. This doesn't make TurboFan codegen any worse, since those restrictions are still in place. R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: Iae59472a5e77c1becc5ff880081f2c0c8c149630 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2690828Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#72676}
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- 10 Feb, 2021 1 commit
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Milad Fa authored
This is a reland of 21b3181a Original change's description: > PPC/s390: [wasm-simd][liftoff] Implement i8x16.popcnt > > Port 00babf07 > > Original Commit Message: > > Extract i8x16.popcnt implementation into a macro-assembler function, and > reuse it in Liftoff. > > R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com > BUG= > LOG=N > > Change-Id: Id0f14597a97f90424aa450b2527ea71da1b2e8ce > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2679273 > Reviewed-by: Junliang Yan <junyan@redhat.com> > Commit-Queue: Junliang Yan <junyan@redhat.com> > Cr-Commit-Position: refs/heads/master@{#72601} Change-Id: I396a3f2ee85550df3a8fa92cd6357e7dc6f096a0 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2685364Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#72627}
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- 09 Feb, 2021 2 commits
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Milad Fa authored
This reverts commit 21b3181a. Reason for revert: Original CL is reverted. Original change's description: > PPC/s390: [wasm-simd][liftoff] Implement i8x16.popcnt > > Port 00babf07 > > Original Commit Message: > > Extract i8x16.popcnt implementation into a macro-assembler function, and > reuse it in Liftoff. > > R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com > BUG= > LOG=N > > Change-Id: Id0f14597a97f90424aa450b2527ea71da1b2e8ce > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2679273 > Reviewed-by: Junliang Yan <junyan@redhat.com> > Commit-Queue: Junliang Yan <junyan@redhat.com> > Cr-Commit-Position: refs/heads/master@{#72601} TBR=joransiu@ca.ibm.com,zhin@chromium.org,mfarazma@redhat.com,midawson@redhat.com,junyan@redhat.com Change-Id: I54dd854e305d0fbbd475c0f756bc41acac74fa56 No-Presubmit: true No-Tree-Checks: true No-Try: true Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2685060Reviewed-by:
Milad Fa <mfarazma@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#72604}
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Milad Fa authored
Port 00babf07 Original Commit Message: Extract i8x16.popcnt implementation into a macro-assembler function, and reuse it in Liftoff. R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: Id0f14597a97f90424aa450b2527ea71da1b2e8ce Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2679273Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#72601}
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- 01 Feb, 2021 1 commit
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Milad Fa authored
Port 6d3a53e7 Original Commit Message: This is a reland of commit 9c09c227. The fix for gc stress failure is merged: https://crrev.com/c/2656857. Original change's description: > Bug: v8:11331 > Change-Id: Ie394ec841a1a1c4030c4f589eac2cee8a6a2a1f9 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2639033 > Reviewed-by: Georg Neis <neis@chromium.org> > Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> > Commit-Queue: Zhi An Ng <zhin@chromium.org> > Cr-Commit-Position: refs/heads/master@{#72304} R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: I68991b81c18e06714d272f019dab7994419692bb Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2665894Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#72467}
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- 27 Jan, 2021 1 commit
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Milad Fa authored
Port 97a935ee R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: I68e7e783c22a420d137ebf777f743780fc90e4d9 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2653070Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#72379}
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- 26 Jan, 2021 1 commit
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Milad Fa authored
Port 22e06c7b Original Commit Message: Factor out the code sequence into macro-assembler functions to be reused by Liftoff. R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: I94d4c8ec8a374a030918c7781b5d4a40dc29091b Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2648985Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#72309}
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- 13 Jan, 2021 2 commits
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Milad Fa authored
Port 8c52f66f Original Commit Message: Implement these 4 instructions for x64 Liftoff: - i64x2.widen_low_i32x4_s - i64x2.widen_high_i32x4_s - i64x2.widen_low_i32x4_u - i64x2.widen_high_i32x4_u We move the codegen for the *high* instructions into macro-assembler to allow sharing of the optimized code sequence between TurboFan and Liftoff. R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: I790860cbb0f9854c31959684712cde42254bde2b Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2625878Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#72070}
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Milad Fa authored
Port 6f521386 Original Commit Message: Create a macro-assembler helper function to enable code sharing between Liftoff and TurboFan. R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: I3e72ad3a2d7dfdd9737a5acd2416741c1d486306 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2625880Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#72069}
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- 12 Jan, 2021 1 commit
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Milad Fa authored
Port d6c4c884 R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: I99c91b49c1fda7e50fee7d9a204e9ade3e336220 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2623808Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#72047}
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- 08 Jan, 2021 1 commit
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Milad Fa authored
Port 5af79398 Original Commit Message: Prototype load lane instructions on Liftoff, only for x64. R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: If9429791139d08a3dd7548220b4eb28e99d6fc7e Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2618241Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#71986}
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- 22 Dec, 2020 1 commit
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Milad Fa authored
Port 1215f2a8 Original Commit Message: The codegen is the same as on TurboFan, using Smull, Umull, Smull2, and Umull2. The rest of the changes are adding skeleton functions to the different archs, which bailout for now. Actual codegen will come in future patches. R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: I58bc84ede44a9c90e315d6dc3346ea09b31deaf7 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2600731Reviewed-by:
Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#71863}
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- 16 Dec, 2020 2 commits
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Milad Fa authored
Port 3dffdf03 Original Commit Message: This adds support for the following instructions: ref.eq, array.new_with_rtt, array.new_default_with_rtt, array.get, array.set, array.len. R=jkummerow@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: I5e517967648251f9babbabe4dc9148a5432aa58e Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2595927Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#71807}
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Andreas Haas authored
Registers are spilled differently on arm and intel platforms. Additionally, on arm64 registers are spilled with padding. Therefore the code for safepoint information for spilled registers is platform- dependent now. Additionally the alignment of the frame size is done before the out-of-line code now, so that the safepoint indices can be calculated correctly for spilled registers in out-of-line code. Finally, some code was unimplemented on ia32 and arm, which I added now. R=thibaudm@chromium.org Bug: v8:7581, v8:10929 Change-Id: Ia9b824dfc74cafa9ec3cc0d308fb18b485afd715 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2584952 Commit-Queue: Andreas Haas <ahaas@chromium.org> Reviewed-by:
Thibaud Michaud <thibaudm@chromium.org> Cr-Commit-Position: refs/heads/master@{#71786}
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