[wasm-simd][x64][liftoff] Implement i64x2.abs

Extract code sequence into macro-assembler for sharing between Liftoff
and TurboFan. Relax the register aliasing requirements (remove the
DCHECKS), this will not affect codegen for TurboFan since the
instruction selector already sets the correct restrictions, but makes it
more flexible for use in Liftoff.

Bug: v8:11416
Change-Id: I5f3f37b21d8f7e96ff7e472cb96dcda5f28679cf
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2707765
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/master@{#72984}

src/codegen/x64/macro-assembler-x64.cc

@@ -2485,6 +2485,25 @@ void TurboAssembler::I32x4TruncSatF64x2UZero(XMMRegister dst, XMMRegister src) {
   }
 }
 
+void TurboAssembler::I64x2Abs(XMMRegister dst, XMMRegister src) {
+  if (CpuFeatures::IsSupported(AVX)) {
+    XMMRegister tmp = dst == src ? kScratchDoubleReg : dst;
+    CpuFeatureScope avx_scope(this, AVX);
+    vpxor(tmp, tmp, tmp);
+    vpsubq(tmp, tmp, src);
+    vblendvpd(dst, src, tmp, src);
+  } else {
+    CpuFeatureScope sse_scope(this, SSE3);
+    movshdup(kScratchDoubleReg, src);
+    if (dst != src) {
+      movaps(dst, src);
+    }
+    psrad(kScratchDoubleReg, 31);
+    xorps(dst, kScratchDoubleReg);
+    psubq(dst, kScratchDoubleReg);
+  }
+}
+
 void TurboAssembler::I64x2GtS(XMMRegister dst, XMMRegister src0,
                               XMMRegister src1) {
   if (CpuFeatures::IsSupported(AVX)) {

src/codegen/x64/macro-assembler-x64.h

@@ -628,6 +628,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
   void I32x4TruncSatF64x2SZero(XMMRegister dst, XMMRegister src);
   void I32x4TruncSatF64x2UZero(XMMRegister dst, XMMRegister src);
 
+  void I64x2Abs(XMMRegister dst, XMMRegister src);
   void I64x2GtS(XMMRegister dst, XMMRegister src0, XMMRegister src1);
   void I64x2GeS(XMMRegister dst, XMMRegister src0, XMMRegister src1);
 

src/compiler/backend/x64/code-generator-x64.cc

@@ -2763,22 +2763,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
     }
     case kX64I64x2Abs: {
-      XMMRegister dst = i.OutputSimd128Register();
-      XMMRegister src = i.InputSimd128Register(0);
-      if (CpuFeatures::IsSupported(AVX)) {
-        DCHECK_NE(dst, src);
-        CpuFeatureScope avx_scope(tasm(), AVX);
-        __ vpxor(dst, dst, dst);
-        __ vpsubq(dst, dst, src);
-        __ vblendvpd(dst, src, dst, src);
-      } else {
-        DCHECK_EQ(dst, src);
-        CpuFeatureScope sse_scope(tasm(), SSE3);
-        __ movshdup(kScratchDoubleReg, src);
-        __ psrad(kScratchDoubleReg, 31);
-        __ xorps(dst, kScratchDoubleReg);
-        __ psubq(dst, kScratchDoubleReg);
-      }
+      __ I64x2Abs(i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
     case kX64I64x2Neg: {

src/wasm/baseline/arm/liftoff-assembler-arm.h

@@ -4022,6 +4022,11 @@ void LiftoffAssembler::emit_i32x4_abs(LiftoffRegister dst,
        liftoff::GetSimd128Register(src));
 }
 
+void LiftoffAssembler::emit_i64x2_abs(LiftoffRegister dst,
+                                      LiftoffRegister src) {
+  bailout(kSimd, "i64x2.abs");
+}
+
 void LiftoffAssembler::StackCheck(Label* ool_code, Register limit_address) {
   ldr(limit_address, MemOperand(limit_address));
   cmp(sp, limit_address);

src/wasm/baseline/arm64/liftoff-assembler-arm64.h

@@ -3066,6 +3066,11 @@ void LiftoffAssembler::emit_i32x4_abs(LiftoffRegister dst,
   Abs(dst.fp().V4S(), src.fp().V4S());
 }
 
+void LiftoffAssembler::emit_i64x2_abs(LiftoffRegister dst,
+                                      LiftoffRegister src) {
+  bailout(kSimd, "i64x2.abs");
+}
+
 void LiftoffAssembler::StackCheck(Label* ool_code, Register limit_address) {
   Ldr(limit_address, MemOperand(limit_address));
   Cmp(sp, limit_address);

src/wasm/baseline/ia32/liftoff-assembler-ia32.h

@@ -4632,6 +4632,11 @@ void LiftoffAssembler::emit_i32x4_abs(LiftoffRegister dst,
   Pabsd(dst.fp(), src.fp());
 }
 
+void LiftoffAssembler::emit_i64x2_abs(LiftoffRegister dst,
+                                      LiftoffRegister src) {
+  bailout(kSimd, "i64x2.abs");
+}
+
 void LiftoffAssembler::emit_i8x16_extract_lane_s(LiftoffRegister dst,
                                                  LiftoffRegister lhs,
                                                  uint8_t imm_lane_idx) {

src/wasm/baseline/liftoff-assembler.h

@@ -1310,6 +1310,7 @@ class LiftoffAssembler : public TurboAssembler {
   inline void emit_i8x16_abs(LiftoffRegister dst, LiftoffRegister src);
   inline void emit_i16x8_abs(LiftoffRegister dst, LiftoffRegister src);
   inline void emit_i32x4_abs(LiftoffRegister dst, LiftoffRegister src);
+  inline void emit_i64x2_abs(LiftoffRegister dst, LiftoffRegister src);
   inline void emit_i8x16_extract_lane_s(LiftoffRegister dst,
                                         LiftoffRegister lhs,
                                         uint8_t imm_lane_idx);

src/wasm/baseline/liftoff-compiler.cc

@@ -3431,6 +3431,8 @@ class LiftoffCompiler {
         return EmitUnOp<kS128, kS128>(&LiftoffAssembler::emit_i16x8_abs);
       case wasm::kExprI32x4Abs:
         return EmitUnOp<kS128, kS128>(&LiftoffAssembler::emit_i32x4_abs);
+      case wasm::kExprI64x2Abs:
+        return EmitUnOp<kS128, kS128>(&LiftoffAssembler::emit_i64x2_abs);
       default:
         unsupported(decoder, kSimd, "simd");
     }

src/wasm/baseline/x64/liftoff-assembler-x64.h

@@ -4160,6 +4160,11 @@ void LiftoffAssembler::emit_i32x4_abs(LiftoffRegister dst,
   Pabsd(dst.fp(), src.fp());
 }
 
+void LiftoffAssembler::emit_i64x2_abs(LiftoffRegister dst,
+                                      LiftoffRegister src) {
+  I64x2Abs(dst.fp(), src.fp());
+}
+
 void LiftoffAssembler::emit_i8x16_extract_lane_s(LiftoffRegister dst,
                                                  LiftoffRegister lhs,
                                                  uint8_t imm_lane_idx) {