- 14 Nov, 2018 1 commit
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Ivica Bogosavljevic authored
This CL implements AtomicPair operators: Load, Store, Add, Sub, Or, Xor, And, Exchange and CompareExchange using runtime on MIPS32R2 and older. MIPS32R6 includes instructions for 64-bit atomic access so they are implemented using those. Change-Id: I1309c1ea4771480516ec5a92f7592533bdcb205c Reviewed-on: https://chromium-review.googlesource.com/c/1326466Reviewed-by: Sreten Kovacevic <skovacevic@wavecomp.com> Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Commit-Queue: Ivica Bogosavljevic <ibogosavljevic@wavecomp.com> Cr-Commit-Position: refs/heads/master@{#57496}
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- 06 Jul, 2018 1 commit
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Sigurd Schneider authored
This CL surfaces AssemblerOptions to CodeAssembler::GenerateCode and to pipeline methods. To allow forward declaring AssemblerOptions, AssemblerBase::Options was moved out of the AssemblerBase class. Bug: v8:6666 Change-Id: If9fc50d3d4767bb5dd39a0c3b6e094021f4cae2b Reviewed-on: https://chromium-review.googlesource.com/1127039 Commit-Queue: Sigurd Schneider <sigurds@chromium.org> Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Reviewed-by: Jakob Gruber <jgruber@chromium.org> Cr-Commit-Position: refs/heads/master@{#54286}
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- 21 Jun, 2018 1 commit
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Ben L. Titzer authored
This completes the transition to Assembler::Options, which reduces the assemblers's dependency on isolates, and there is now only one way to create an Assembler, which is to use the options. Note that some operations on assemblers still need an isolate, such as GetCode(), and in these cases, the isolate is an additional argument to the method. R=jgruber@chromium.org CC=mstarzinger@chromium.org Change-Id: I413209d816c63a7c3640f1c226764693dcad1e7f Reviewed-on: https://chromium-review.googlesource.com/1106169 Commit-Queue: Ben Titzer <titzer@chromium.org> Reviewed-by: Jakob Gruber <jgruber@chromium.org> Cr-Commit-Position: refs/heads/master@{#53925}
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- 02 Dec, 2017 1 commit
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Mathias Bynens authored
This patch normalizes the casing of hexadecimal digits in escape sequences of the form `\xNN` and integer literals of the form `0xNNNN`. Previously, the V8 code base used an inconsistent mixture of uppercase and lowercase. Google’s C++ style guide uses uppercase in its examples: https://google.github.io/styleguide/cppguide.html#Non-ASCII_Characters Moreover, uppercase letters more clearly stand out from the lowercase `x` (or `u`) characters at the start, as well as lowercase letters elsewhere in strings. BUG=v8:7109 TBR=marja@chromium.org,titzer@chromium.org,mtrofin@chromium.org,mstarzinger@chromium.org,rossberg@chromium.org,yangguo@chromium.org,mlippautz@chromium.org NOPRESUBMIT=true Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng Change-Id: I790e21c25d96ad5d95c8229724eb45d2aa9e22d6 Reviewed-on: https://chromium-review.googlesource.com/804294 Commit-Queue: Mathias Bynens <mathias@chromium.org> Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#49810}
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- 01 Sep, 2017 1 commit
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Michael Starzinger authored
R=jkummerow@chromium.org Change-Id: I8937933e9ec5b4bd150f5a044700716db458f365 Reviewed-on: https://chromium-review.googlesource.com/645691Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#47758}
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- 17 Aug, 2017 1 commit
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Ivica Bogosavljevic authored
Bug: Change-Id: I5b5477b55f42cdfa7978bbe6b8610302f0ec41fb Reviewed-on: https://chromium-review.googlesource.com/612085Reviewed-by: Miran Karić <Miran.Karic@imgtec.com> Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com> Cr-Commit-Position: refs/heads/master@{#47396}
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- 03 Aug, 2017 1 commit
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Ben L. Titzer authored
Since frames.h no longer defines basic register types like RegList, it is no longer necessary to include it in the macro assemblers. Next step: split out frame-constants.h from frames.h so that it will be possible to get frame constants without include the stackwalking logic, which needs objects.h. R=mstarzinger@chromium.org Bug: Change-Id: Ia12d3c8a8d46a73106c3c90bcb4b470c85f1eaa7 Reviewed-on: https://chromium-review.googlesource.com/597788 Commit-Queue: Ben Titzer <titzer@chromium.org> Reviewed-by: Yang Guo <yangguo@chromium.org> Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#47114}
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- 01 Jun, 2017 1 commit
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dusan.simicic authored
Add support for S1x4And, S1x4Or, S1x4Xor, S1x4Not, S1x4AnyTrue, S1x4AllTrue, S1x8And, S1x8Or, S1x8Xor, S1x8Not, S1x8AnyTrue, S1x8AllTrue, S1x16And, S1x16Or, S1x16Xor, S1x16Not, S1x16AnyTrue, S1x16AllTrue, SimdLoad, SimdStore operations for mips32 and mips64 architectures. BUG= Review-Url: https://codereview.chromium.org/2801683003 Cr-Commit-Position: refs/heads/master@{#45662}
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- 27 Mar, 2017 1 commit
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dusan.simicic authored
This patch adds support for MIPS SIMD (MSA) instructions in Assembler and Decoder (disassembler) classes. MSA instructions are implemented for both mips32 and mips64 architectures. BUG= Review-Url: https://codereview.chromium.org/2740123004 Cr-Commit-Position: refs/heads/master@{#44148}
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- 14 Sep, 2016 1 commit
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Ilija.Pavlovic authored
Implementation MADD.S. MSUB.fmt, MADDF.fmt, MSUBF.fmt and corresponding tests for assembler and disassembler. TEST=cctest/test-assembler-mips[64], cctest/test-disasm-mips[64] BUG= Review-Url: https://codereview.chromium.org/2313623002 Cr-Commit-Position: refs/heads/master@{#39415}
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- 27 Jun, 2016 1 commit
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ivica.bogosavljevic authored
BUG= Review-Url: https://codereview.chromium.org/2069933003 Cr-Commit-Position: refs/heads/master@{#37295}
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- 24 May, 2016 1 commit
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machenbach authored
For cross-compiler-compatibility and standards compliance %p requires a void*, rather than any pointer type. BUG=chromium:474921 Review-Url: https://codereview.chromium.org/2001073002 Cr-Commit-Position: refs/heads/master@{#36466}
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- 09 Dec, 2015 1 commit
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jochen authored
Embedders still can use those APIs by default test-api.cc still has an exception to use the old APIs... BUG=v8:4143 R=vogelheim@chromium.org LOG=n Review URL: https://codereview.chromium.org/1505803004 Cr-Commit-Position: refs/heads/master@{#32701}
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- 30 Nov, 2015 1 commit
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alan.li authored
BUG= Review URL: https://codereview.chromium.org/1481493002 Cr-Commit-Position: refs/heads/master@{#32417}
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- 27 Nov, 2015 1 commit
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Djordje.Pesic authored
These instructions now show FCSR in disassembly, instead f31 BUG= Review URL: https://codereview.chromium.org/1481023002 Cr-Commit-Position: refs/heads/master@{#32366}
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- 20 Nov, 2015 1 commit
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akos.palfi authored
Don't generate FP64 mode specific instructions in FP32 mode. TEST=cctest/test-disasm-mips/Type1, cctest/test-disasm-mips/CVT_DISSASM BUG= Review URL: https://codereview.chromium.org/1462803003 Cr-Commit-Position: refs/heads/master@{#32138}
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- 16 Nov, 2015 1 commit
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jochen authored
BUG=4134 R=epertoso@chromium.org LOG=n Review URL: https://codereview.chromium.org/1451733002 Cr-Commit-Position: refs/heads/master@{#32011}
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- 10 Nov, 2015 1 commit
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balazs.kilvady authored
Jic and jialc compact branch ops are fixed as they does not have 'forbidden slot' restriction. Also COP1 branches (CTI instructions) added to IsForbiddenAfterBranchInstr(). TEST=cctest/test-disasm-mips/Type0 BUG= Review URL: https://codereview.chromium.org/1423493006 Cr-Commit-Position: refs/heads/master@{#31922}
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- 31 Jul, 2015 1 commit
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yangguo authored
R=cbruni@chromium.org Review URL: https://codereview.chromium.org/1265923002 Cr-Commit-Position: refs/heads/master@{#29951}
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- 16 Jul, 2015 1 commit
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Ilija.Pavlovic authored
Improved checking target ranges for J and JAL instructions. Adapted disassembler test for J and JAL instructions. TEST=cctest/test-disasm-mips[64] BUG= Review URL: https://codereview.chromium.org/1237083003 Cr-Commit-Position: refs/heads/master@{#29693}
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- 15 Jul, 2015 2 commits
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balazs.kilvady authored
Port c63e50ed BUG= TEST=test-disasm-mips/Type Review URL: https://codereview.chromium.org/1233323002 Cr-Commit-Position: refs/heads/master@{#29688}
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machenbach authored
Rolling v8/tools/clang to 58128abd44c22255def1163d30bc9bb2cc85e15c Reland after https://codereview.chromium.org/1241643002/ TBR=jochen@chromium.org, thakis@chromium.org Review URL: https://codereview.chromium.org/1237793003 Cr-Commit-Position: refs/heads/master@{#29673}
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- 13 Jul, 2015 2 commits
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https://codereview.chromium.org/1232583002/machenbach authored
Reason for revert: [Sheriff] Looks like another clang option got deprecated: http://build.chromium.org/p/client.v8/builders/V8%20Linux%20ASAN%20mipsel%20-%20debug%20builder/builds/326 Original issue's description: > Update V8 DEPS. > > Rolling v8/tools/clang to 58128abd44c22255def1163d30bc9bb2cc85e15c > > Original CL: https://codereview.chromium.org/1232043002/ > > BUG= > > Committed: https://crrev.com/6211e1660492f653d30ddd1336bce6f9083ede94 > Cr-Commit-Position: refs/heads/master@{#29598} TBR=jochen@chromium.org,akos.palfi@imgtec.com NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG= Review URL: https://codereview.chromium.org/1232803003 Cr-Commit-Position: refs/heads/master@{#29600}
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machenbach authored
Rolling v8/tools/clang to 58128abd44c22255def1163d30bc9bb2cc85e15c Original CL: https://codereview.chromium.org/1232043002/ BUG= Review URL: https://codereview.chromium.org/1232583002 Cr-Commit-Position: refs/heads/master@{#29598}
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- 03 Jul, 2015 1 commit
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Ilija.Pavlovic authored
MIPS: Disassembler enhancement. Disassembled branch instruction displays branch target absolute address. TEST=cctest/test-disasm-mips[64] BUG= Review URL: https://codereview.chromium.org/1213553004 Cr-Commit-Position: refs/heads/master@{#29462}
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- 01 Jul, 2015 1 commit
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Djordje.Pesic authored
Disabling rsqrt and recip for mips32r1 in assembler, disassembler and simulator Review URL: https://codereview.chromium.org/1221663006 Cr-Commit-Position: refs/heads/master@{#29425}
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- 19 Jun, 2015 1 commit
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Ilija.Pavlovic authored
Added: JIC, BEQZC, JIALC, LDPC, LWPC, ALUIPC, ADDIUPC, ALIGN/DAILGN, LWUPC, AUIPC, BC, BALC. Additional fixed compact branch offset. TEST=test-assembler-mips[64]/r6_align, r6_dalign, r6_aluipc, r6_lwpc, r6_jic, r6_beqzc, r6_jialc, r6_addiupc, r6_ldpc, r6_lwupc, r6_auipc, r6_bc, r6_balc BUG= Review URL: https://codereview.chromium.org/1195793002 Cr-Commit-Position: refs/heads/master@{#29143}
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- 22 May, 2015 1 commit
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Djordje.Pesic authored
Implement assembler, disassembler tests for all instructions for mips32 and mips64. Additionally, add missing single precision float instructions for r2 and r6 architecture variants in assembler, simulator and disassembler with corresponding tests. Review URL: https://codereview.chromium.org/1145223002 Cr-Commit-Position: refs/heads/master@{#28595}
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- 19 May, 2015 1 commit
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Djordje.Pesic authored
Implement assembler, disassembler tests for all instructions for mips32 and mips64. Additionally, add missing single precision float instructions for r2 and r6 architecture variants in assembler, simulator and disassembler with corresponding tests. Review URL: https://codereview.chromium.org/1147493002 Cr-Commit-Position: refs/heads/master@{#28472}
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- 14 May, 2015 2 commits
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paul.lind authored
Reason for revert: Simulator test failures in RunChangeFloat64ToInt.., RunChangeTaggedToInt32, div-mul-minus-one Original issue's description: > Implement assembler, disassembler tests for all instructions for mips32 > and mips64. Additionally, add missing single precision float instructions > for r2 and r6 architecture variants in assembler, simulator and disassembler > with corresponding tests. BUG= Review URL: https://codereview.chromium.org/1143473003 Cr-Commit-Position: refs/heads/master@{#28404}
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Djordje.Pesic authored
Implement assembler, disassembler tests for all instructions for mips32 and mips64. Additionally, add missing single precision float instructions for r2 and r6 architecture variants in assembler, simulator and disassembler with corresponding tests. Review URL: https://codereview.chromium.org/1119203003 Cr-Commit-Position: refs/heads/master@{#28402}
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- 30 Apr, 2015 2 commits
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dusan.milosavljevic authored
TEST= BUG= Review URL: https://codereview.chromium.org/1118693002 Cr-Commit-Position: refs/heads/master@{#28181}
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Djordje.Pesic authored
Added rounding according to fcsr, CVT_W_D and RINT.D instruction in assembler, dissasembler and simulator and wrote appropiate tests. BUG= Review URL: https://codereview.chromium.org/1108583003 Cr-Commit-Position: refs/heads/master@{#28143}
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- 06 Apr, 2015 1 commit
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dusan.milosavljevic authored
- Fixed single float register type instruction en[de]coding in assembler and disassembler. - Added max and min instructions for r6 and corresponding tests. - Fixed selection instruction for boundary cases in simulator. - Update assembler tests to be more thorough wrt boundary cases. TEST=cctest/test-assembler-mips64/MIPS17, MIPS18 cctest/test-disasm-mips64/Type1 cctest/test-assembler-mips/MIPS16, MIPS17 cctest/test-disasm-mips/Type1 BUG= Review URL: https://codereview.chromium.org/1057323002 Cr-Commit-Position: refs/heads/master@{#27601}
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- 30 Mar, 2015 1 commit
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dusan.milosavljevic authored
TEST= BUG= Review URL: https://codereview.chromium.org/1046873004 Cr-Commit-Position: refs/heads/master@{#27530}
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- 27 Mar, 2015 1 commit
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yangguo authored
R=jochen@chromium.org Review URL: https://codereview.chromium.org/1041743002 Cr-Commit-Position: refs/heads/master@{#27501}
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- 12 Aug, 2014 1 commit
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dusan.milosavljevic@imgtec.com authored
Fixing gclient runhooks failure caused by reverted commit r23050. TEST= BUG= R=jkummerow@chromium.org, paul.lind@imgtec.com Review URL: https://codereview.chromium.org/467583002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23088 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 11 Aug, 2014 3 commits
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machenbach@chromium.org authored
This reverts commit r23050 for breaking runhooks on chromium. See e.g.: http://build.chromium.org/p/client.v8/builders/Chrome%20Linux%20Perf/builds/1438/steps/runhooks/logs/stdio TBR=jochen@chromium.org Review URL: https://codereview.chromium.org/458983003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23053 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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dusan.milosavljevic@imgtec.com authored
Original commit r23028 breaks ARM64 build due to conflicting FP64 symbolic constant definition in src/globals.h and src/arm64/constants-arm64.h. TEST= BUG= R=jkummerow@chromium.org, paul.lind@imgtec.com Review URL: https://codereview.chromium.org/457313003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23050 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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jochen@chromium.org authored
Breaks compilation of ARM64. | Additional summary: | - Introduce fp64 fpu mode into mips32 port required for r6. | - Implement runtime detections for fpu mode and arch. revision to preserve | compatibility with previous architecture revisions. | | TEST= | BUG= | R=jkummerow@chromium.org, paul.lind@imgtec.com | | Review URL: https://codereview.chromium.org/453043002 BUG=none LOG=n TBR=jkummerow@chromium.org Review URL: https://codereview.chromium.org/458193002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23030 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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