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Commit b287c743 authored by Djordje.Pesic's avatar Djordje.Pesic Committed by Commit bot
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MIPS: Fixup disasembler for ctc1 and cfc1 

These instructions now show FCSR in disassembly, instead f31

BUG=

Review URL: https://codereview.chromium.org/1481023002

Cr-Commit-Position: refs/heads/master@{#32366}
parent afb8bcce
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Showing with 116 additions and 32 deletions
src/mips/disasm-mips.cc
View file @ b287c743
......@@ -66,6 +66,7 @@ class Decoder {
// Printing of common values.
void PrintRegister(int reg);
void PrintFPURegister(int freg);
void PrintFPUStatusRegister(int freg);
void PrintRs(Instruction* instr);
void PrintRt(Instruction* instr);
void PrintRd(Instruction* instr);
......@@ -182,6 +183,17 @@ void Decoder::PrintFPURegister(int freg) {
}
void Decoder::PrintFPUStatusRegister(int freg) {
switch (freg) {
case kFCSRRegister:
Print("FCSR");
break;
default:
Print(converter_.NameOfXMMRegister(freg));
}
}
void Decoder::PrintFs(Instruction* instr) {
int freg = instr->RsValue();
PrintFPURegister(freg);
......@@ -476,22 +488,42 @@ int Decoder::FormatRegister(Instruction* instr, const char* format) {
// complexity of FormatOption.
int Decoder::FormatFPURegister(Instruction* instr, const char* format) {
DCHECK(format[0] == 'f');
if (format[1] == 's') { // 'fs: fs register.
int reg = instr->FsValue();
PrintFPURegister(reg);
return 2;
} else if (format[1] == 't') { // 'ft: ft register.
int reg = instr->FtValue();
PrintFPURegister(reg);
return 2;
} else if (format[1] == 'd') { // 'fd: fd register.
int reg = instr->FdValue();
PrintFPURegister(reg);
return 2;
} else if (format[1] == 'r') { // 'fr: fr register.
int reg = instr->FrValue();
PrintFPURegister(reg);
return 2;
if ((CTC1 == instr->RsFieldRaw()) || (CFC1 == instr->RsFieldRaw())) {
if (format[1] == 's') { // 'fs: fs register.
int reg = instr->FsValue();
PrintFPUStatusRegister(reg);
return 2;
} else if (format[1] == 't') { // 'ft: ft register.
int reg = instr->FtValue();
PrintFPUStatusRegister(reg);
return 2;
} else if (format[1] == 'd') { // 'fd: fd register.
int reg = instr->FdValue();
PrintFPUStatusRegister(reg);
return 2;
} else if (format[1] == 'r') { // 'fr: fr register.
int reg = instr->FrValue();
PrintFPUStatusRegister(reg);
return 2;
}
} else {
if (format[1] == 's') { // 'fs: fs register.
int reg = instr->FsValue();
PrintFPURegister(reg);
return 2;
} else if (format[1] == 't') { // 'ft: ft register.
int reg = instr->FtValue();
PrintFPURegister(reg);
return 2;
} else if (format[1] == 'd') { // 'fd: fd register.
int reg = instr->FdValue();
PrintFPURegister(reg);
return 2;
} else if (format[1] == 'r') { // 'fr: fr register.
int reg = instr->FrValue();
PrintFPURegister(reg);
return 2;
}
}
UNREACHABLE();
return -1;
......
src/mips64/disasm-mips64.cc
View file @ b287c743
......@@ -67,6 +67,7 @@ class Decoder {
// Printing of common values.
void PrintRegister(int reg);
void PrintFPURegister(int freg);
void PrintFPUStatusRegister(int freg);
void PrintRs(Instruction* instr);
void PrintRt(Instruction* instr);
void PrintRd(Instruction* instr);
......@@ -190,6 +191,17 @@ void Decoder::PrintFPURegister(int freg) {
}
void Decoder::PrintFPUStatusRegister(int freg) {
switch (freg) {
case kFCSRRegister:
Print("FCSR");
break;
default:
Print(converter_.NameOfXMMRegister(freg));
}
}
void Decoder::PrintFs(Instruction* instr) {
int freg = instr->RsValue();
PrintFPURegister(freg);
......@@ -481,22 +493,42 @@ int Decoder::FormatRegister(Instruction* instr, const char* format) {
// complexity of FormatOption.
int Decoder::FormatFPURegister(Instruction* instr, const char* format) {
DCHECK(format[0] == 'f');
if (format[1] == 's') { // 'fs: fs register.
int reg = instr->FsValue();
PrintFPURegister(reg);
return 2;
} else if (format[1] == 't') { // 'ft: ft register.
int reg = instr->FtValue();
PrintFPURegister(reg);
return 2;
} else if (format[1] == 'd') { // 'fd: fd register.
int reg = instr->FdValue();
PrintFPURegister(reg);
return 2;
} else if (format[1] == 'r') { // 'fr: fr register.
int reg = instr->FrValue();
PrintFPURegister(reg);
return 2;
if ((CTC1 == instr->RsFieldRaw()) || (CFC1 == instr->RsFieldRaw())) {
if (format[1] == 's') { // 'fs: fs register.
int reg = instr->FsValue();
PrintFPUStatusRegister(reg);
return 2;
} else if (format[1] == 't') { // 'ft: ft register.
int reg = instr->FtValue();
PrintFPUStatusRegister(reg);
return 2;
} else if (format[1] == 'd') { // 'fd: fd register.
int reg = instr->FdValue();
PrintFPUStatusRegister(reg);
return 2;
} else if (format[1] == 'r') { // 'fr: fr register.
int reg = instr->FrValue();
PrintFPUStatusRegister(reg);
return 2;
}
} else {
if (format[1] == 's') { // 'fs: fs register.
int reg = instr->FsValue();
PrintFPURegister(reg);
return 2;
} else if (format[1] == 't') { // 'ft: ft register.
int reg = instr->FtValue();
PrintFPURegister(reg);
return 2;
} else if (format[1] == 'd') { // 'fd: fd register.
int reg = instr->FdValue();
PrintFPURegister(reg);
return 2;
} else if (format[1] == 'r') { // 'fr: fr register.
int reg = instr->FrValue();
PrintFPURegister(reg);
return 2;
}
}
UNREACHABLE();
return -1;
......
test/cctest/test-disasm-mips.cc
View file @ b287c743
......@@ -1066,3 +1066,13 @@ TEST(CVT_DISSASM) {
VERIFY_RUN();
}
TEST(ctc1_cfc1_disasm) {
SET_UP();
COMPARE(abs_d(f10, f31), "4620fa85 abs.d f10, f31");
COMPARE(ceil_w_s(f8, f31), "4600fa0e ceil.w.s f8, f31");
COMPARE(ctc1(a0, FCSR), "44c4f800 ctc1 a0, FCSR");
COMPARE(cfc1(a0, FCSR), "4444f800 cfc1 a0, FCSR");
VERIFY_RUN();
}
test/cctest/test-disasm-mips64.cc
View file @ b287c743
......@@ -1242,3 +1242,13 @@ TEST(CVT_DISSASM) {
VERIFY_RUN();
}
TEST(ctc1_cfc1_disasm) {
SET_UP();
COMPARE(abs_d(f10, f31), "4620fa85 abs.d f10, f31");
COMPARE(ceil_w_s(f8, f31), "4600fa0e ceil.w.s f8, f31");
COMPARE(ctc1(a0, FCSR), "44c4f800 ctc1 a0, FCSR");
COMPARE(cfc1(a0, FCSR), "4444f800 cfc1 a0, FCSR");
VERIFY_RUN();
}
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