disasm-mips.cc 49.9 KB
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// Copyright 2012 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
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// A Disassembler object is used to disassemble a block of code instruction by
// instruction. The default implementation of the NameConverter object can be
// overriden to modify register names or to do symbol lookup on addresses.
//
// The example below will disassemble a block of code and print it to stdout.
//
//   NameConverter converter;
//   Disassembler d(converter);
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//   for (byte* pc = begin; pc < end;) {
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//     v8::internal::EmbeddedVector<char, 256> buffer;
//     byte* prev_pc = pc;
//     pc += d.InstructionDecode(buffer, pc);
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//     printf("%p    %08x      %s\n",
//            prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer);
//   }
//
// The Disassembler class also has a convenience method to disassemble a block
// of code into a FILE*, meaning that the above functionality could also be
// achieved by just calling Disassembler::Disassemble(stdout, begin, end);

#include <assert.h>
#include <stdarg.h>
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#include <stdio.h>
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#include <string.h>

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#if V8_TARGET_ARCH_MIPS
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#include "src/base/platform/platform.h"
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#include "src/disasm.h"
#include "src/macro-assembler.h"
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#include "src/mips/constants-mips.h"
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namespace v8 {
namespace internal {
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//------------------------------------------------------------------------------

// Decoder decodes and disassembles instructions into an output buffer.
// It uses the converter to convert register names and call destinations into
// more informative description.
class Decoder {
 public:
  Decoder(const disasm::NameConverter& converter,
          v8::internal::Vector<char> out_buffer)
    : converter_(converter),
      out_buffer_(out_buffer),
      out_buffer_pos_(0) {
    out_buffer_[out_buffer_pos_] = '\0';
  }

  ~Decoder() {}

  // Writes one disassembled instruction into 'buffer' (0-terminated).
  // Returns the length of the disassembled machine instruction in bytes.
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  int InstructionDecode(byte* instruction);
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 private:
  // Bottleneck functions to print into the out_buffer.
  void PrintChar(const char ch);
  void Print(const char* str);

  // Printing of common values.
  void PrintRegister(int reg);
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  void PrintFPURegister(int freg);
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  void PrintFPUStatusRegister(int freg);
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  void PrintRs(Instruction* instr);
  void PrintRt(Instruction* instr);
  void PrintRd(Instruction* instr);
  void PrintFs(Instruction* instr);
  void PrintFt(Instruction* instr);
  void PrintFd(Instruction* instr);
  void PrintSa(Instruction* instr);
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  void PrintLsaSa(Instruction* instr);
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  void PrintSd(Instruction* instr);
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  void PrintSs1(Instruction* instr);
  void PrintSs2(Instruction* instr);
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  void PrintBc(Instruction* instr);
  void PrintCc(Instruction* instr);
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  void PrintBp2(Instruction* instr);
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  void PrintFunction(Instruction* instr);
  void PrintSecondaryField(Instruction* instr);
  void PrintUImm16(Instruction* instr);
  void PrintSImm16(Instruction* instr);
  void PrintXImm16(Instruction* instr);
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  void PrintPCImm16(Instruction* instr, int delta_pc, int n_bits);
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  void PrintXImm18(Instruction* instr);
  void PrintSImm18(Instruction* instr);
  void PrintXImm19(Instruction* instr);
  void PrintSImm19(Instruction* instr);
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  void PrintXImm21(Instruction* instr);
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  void PrintSImm21(Instruction* instr);
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  void PrintPCImm21(Instruction* instr, int delta_pc, int n_bits);
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  void PrintXImm26(Instruction* instr);
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  void PrintSImm26(Instruction* instr);
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  void PrintPCImm26(Instruction* instr, int delta_pc, int n_bits);
  void PrintPCImm26(Instruction* instr);
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  void PrintCode(Instruction* instr);   // For break and trap instructions.
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  void PrintFormat(Instruction* instr);  // For floating format postfix.
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  // Printing of instruction name.
  void PrintInstructionName(Instruction* instr);

  // Handle formatting of instructions and their options.
  int FormatRegister(Instruction* instr, const char* option);
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  int FormatFPURegister(Instruction* instr, const char* option);
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  int FormatOption(Instruction* instr, const char* option);
  void Format(Instruction* instr, const char* format);
  void Unknown(Instruction* instr);

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  // Each of these functions decodes one particular instruction type.
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  bool DecodeTypeRegisterRsType(Instruction* instr);
  void DecodeTypeRegisterSRsType(Instruction* instr);
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  void DecodeTypeRegisterDRsType(Instruction* instr);
  void DecodeTypeRegisterLRsType(Instruction* instr);
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  void DecodeTypeRegisterWRsType(Instruction* instr);
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  void DecodeTypeRegisterSPECIAL(Instruction* instr);
  void DecodeTypeRegisterSPECIAL2(Instruction* instr);
  void DecodeTypeRegisterSPECIAL3(Instruction* instr);
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  void DecodeTypeRegister(Instruction* instr);
  void DecodeTypeImmediate(Instruction* instr);
  void DecodeTypeJump(Instruction* instr);

  const disasm::NameConverter& converter_;
  v8::internal::Vector<char> out_buffer_;
  int out_buffer_pos_;

  DISALLOW_COPY_AND_ASSIGN(Decoder);
};


// Support for assertions in the Decoder formatting functions.
#define STRING_STARTS_WITH(string, compare_string) \
  (strncmp(string, compare_string, strlen(compare_string)) == 0)


// Append the ch to the output buffer.
void Decoder::PrintChar(const char ch) {
  out_buffer_[out_buffer_pos_++] = ch;
}


// Append the str to the output buffer.
void Decoder::Print(const char* str) {
  char cur = *str++;
  while (cur != '\0' && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
    PrintChar(cur);
    cur = *str++;
  }
  out_buffer_[out_buffer_pos_] = 0;
}


// Print the register name according to the active name converter.
void Decoder::PrintRegister(int reg) {
  Print(converter_.NameOfCPURegister(reg));
}


void Decoder::PrintRs(Instruction* instr) {
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  int reg = instr->RsValue();
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  PrintRegister(reg);
}


void Decoder::PrintRt(Instruction* instr) {
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  int reg = instr->RtValue();
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  PrintRegister(reg);
}


void Decoder::PrintRd(Instruction* instr) {
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  int reg = instr->RdValue();
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  PrintRegister(reg);
}


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// Print the FPUregister name according to the active name converter.
void Decoder::PrintFPURegister(int freg) {
  Print(converter_.NameOfXMMRegister(freg));
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}


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void Decoder::PrintFPUStatusRegister(int freg) {
  switch (freg) {
    case kFCSRRegister:
      Print("FCSR");
      break;
    default:
      Print(converter_.NameOfXMMRegister(freg));
  }
}


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void Decoder::PrintFs(Instruction* instr) {
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  int freg = instr->RsValue();
  PrintFPURegister(freg);
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}


void Decoder::PrintFt(Instruction* instr) {
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  int freg = instr->RtValue();
  PrintFPURegister(freg);
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}


void Decoder::PrintFd(Instruction* instr) {
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  int freg = instr->RdValue();
  PrintFPURegister(freg);
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}


// Print the integer value of the sa field.
void Decoder::PrintSa(Instruction* instr) {
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  int sa = instr->SaValue();
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  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa);
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}


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// Print the integer value of the sa field of a lsa instruction.
void Decoder::PrintLsaSa(Instruction* instr) {
  int sa = instr->LsaSaValue() + 1;
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa);
}


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// Print the integer value of the rd field, when it is not used as reg.
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void Decoder::PrintSd(Instruction* instr) {
  int sd = instr->RdValue();
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  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sd);
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}


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// Print the integer value of the rd field, when used as 'ext' size.
void Decoder::PrintSs1(Instruction* instr) {
  int ss = instr->RdValue();
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  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", ss + 1);
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}


// Print the integer value of the rd field, when used as 'ins' size.
void Decoder::PrintSs2(Instruction* instr) {
  int ss = instr->RdValue();
  int pos = instr->SaValue();
  out_buffer_pos_ +=
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      SNPrintF(out_buffer_ + out_buffer_pos_, "%d", ss - pos + 1);
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}


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// Print the integer value of the cc field for the bc1t/f instructions.
void Decoder::PrintBc(Instruction* instr) {
  int cc = instr->FBccValue();
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  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", cc);
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}


// Print the integer value of the cc field for the FP compare instructions.
void Decoder::PrintCc(Instruction* instr) {
  int cc = instr->FCccValue();
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  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "cc(%d)", cc);
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}


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void Decoder::PrintBp2(Instruction* instr) {
  int bp2 = instr->Bp2Value();
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", bp2);
}


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// Print 16-bit unsigned immediate value.
void Decoder::PrintUImm16(Instruction* instr) {
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  int32_t imm = instr->Imm16Value();
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  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%u", imm);
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}


// Print 16-bit signed immediate value.
void Decoder::PrintSImm16(Instruction* instr) {
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  int32_t imm = ((instr->Imm16Value()) << 16) >> 16;
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  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm);
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}


// Print 16-bit hexa immediate value.
void Decoder::PrintXImm16(Instruction* instr) {
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  int32_t imm = instr->Imm16Value();
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  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
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}


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// Print absoulte address for 16-bit offset or immediate value.
// The absolute address is calculated according following expression:
//      PC + delta_pc + (offset << n_bits)
void Decoder::PrintPCImm16(Instruction* instr, int delta_pc, int n_bits) {
  int16_t offset = instr->Imm16Value();
  out_buffer_pos_ +=
      SNPrintF(out_buffer_ + out_buffer_pos_, "%s",
               converter_.NameOfAddress(reinterpret_cast<byte*>(instr) +
                                        delta_pc + (offset << n_bits)));
}


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// Print 18-bit signed immediate value.
void Decoder::PrintSImm18(Instruction* instr) {
  int32_t imm =
      ((instr->Imm18Value()) << (32 - kImm18Bits)) >> (32 - kImm18Bits);
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm);
}


// Print 18-bit hexa immediate value.
void Decoder::PrintXImm18(Instruction* instr) {
  int32_t imm = instr->Imm18Value();
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
}


// Print 19-bit hexa immediate value.
void Decoder::PrintXImm19(Instruction* instr) {
  int32_t imm = instr->Imm19Value();
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
}


// Print 19-bit signed immediate value.
void Decoder::PrintSImm19(Instruction* instr) {
  int32_t imm19 = instr->Imm19Value();
  // set sign
  imm19 <<= (32 - kImm19Bits);
  imm19 >>= (32 - kImm19Bits);
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm19);
}


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// Print 21-bit immediate value.
void Decoder::PrintXImm21(Instruction* instr) {
  uint32_t imm = instr->Imm21Value();
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
}


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// Print 21-bit signed immediate value.
void Decoder::PrintSImm21(Instruction* instr) {
  int32_t imm21 = instr->Imm21Value();
  // set sign
  imm21 <<= (32 - kImm21Bits);
  imm21 >>= (32 - kImm21Bits);
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm21);
}


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// Print absoulte address for 21-bit offset or immediate value.
// The absolute address is calculated according following expression:
//      PC + delta_pc + (offset << n_bits)
void Decoder::PrintPCImm21(Instruction* instr, int delta_pc, int n_bits) {
  int32_t imm21 = instr->Imm21Value();
  // set sign
  imm21 <<= (32 - kImm21Bits);
  imm21 >>= (32 - kImm21Bits);
  out_buffer_pos_ +=
      SNPrintF(out_buffer_ + out_buffer_pos_, "%s",
               converter_.NameOfAddress(reinterpret_cast<byte*>(instr) +
                                        delta_pc + (imm21 << n_bits)));
}


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// Print 26-bit hex immediate value.
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void Decoder::PrintXImm26(Instruction* instr) {
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  uint32_t target = static_cast<uint32_t>(instr->Imm26Value())
                    << kImmFieldShift;
  target = (reinterpret_cast<uint32_t>(instr) & ~0xfffffff) | target;
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", target);
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}


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// Print 26-bit signed immediate value.
void Decoder::PrintSImm26(Instruction* instr) {
  int32_t imm26 = instr->Imm26Value();
  // set sign
  imm26 <<= (32 - kImm26Bits);
  imm26 >>= (32 - kImm26Bits);
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm26);
}


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// Print absoulte address for 26-bit offset or immediate value.
// The absolute address is calculated according following expression:
//      PC + delta_pc + (offset << n_bits)
void Decoder::PrintPCImm26(Instruction* instr, int delta_pc, int n_bits) {
  int32_t imm26 = instr->Imm26Value();
  // set sign
  imm26 <<= (32 - kImm26Bits);
  imm26 >>= (32 - kImm26Bits);
  out_buffer_pos_ +=
      SNPrintF(out_buffer_ + out_buffer_pos_, "%s",
               converter_.NameOfAddress(reinterpret_cast<byte*>(instr) +
                                        delta_pc + (imm26 << n_bits)));
}


// Print absoulte address for 26-bit offset or immediate value.
// The absolute address is calculated according following expression:
//      PC[GPRLEN-1 .. 28] || instr_index26 || 00
void Decoder::PrintPCImm26(Instruction* instr) {
  int32_t imm26 = instr->Imm26Value();
  uint32_t pc_mask = ~0xfffffff;
  uint32_t pc = ((uint32_t)(instr + 1) & pc_mask) | (imm26 << 2);
  out_buffer_pos_ +=
      SNPrintF(out_buffer_ + out_buffer_pos_, "%s",
               converter_.NameOfAddress((reinterpret_cast<byte*>(pc))));
}


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// Print 26-bit immediate value.
void Decoder::PrintCode(Instruction* instr) {
  if (instr->OpcodeFieldRaw() != SPECIAL)
    return;  // Not a break or trap instruction.
  switch (instr->FunctionFieldRaw()) {
    case BREAK: {
      int32_t code = instr->Bits(25, 6);
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      out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                  "0x%05x (%d)", code, code);
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      break;
                }
    case TGE:
    case TGEU:
    case TLT:
    case TLTU:
    case TEQ:
    case TNE: {
      int32_t code = instr->Bits(15, 6);
      out_buffer_pos_ +=
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          SNPrintF(out_buffer_ + out_buffer_pos_, "0x%03x", code);
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      break;
    }
    default:  // Not a break or trap instruction.
    break;
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  }
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}


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void Decoder::PrintFormat(Instruction* instr) {
  char formatLetter = ' ';
  switch (instr->RsFieldRaw()) {
    case S:
      formatLetter = 's';
      break;
    case D:
      formatLetter = 'd';
      break;
    case W:
      formatLetter = 'w';
      break;
    case L:
      formatLetter = 'l';
      break;
    default:
      UNREACHABLE();
      break;
  }
  PrintChar(formatLetter);
}


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// Printing of instruction name.
void Decoder::PrintInstructionName(Instruction* instr) {
}


// Handle all register based formatting in this function to reduce the
// complexity of FormatOption.
int Decoder::FormatRegister(Instruction* instr, const char* format) {
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  DCHECK(format[0] == 'r');
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  if (format[1] == 's') {  // 'rs: Rs register.
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    int reg = instr->RsValue();
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    PrintRegister(reg);
    return 2;
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  } else if (format[1] == 't') {  // 'rt: rt register.
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    int reg = instr->RtValue();
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    PrintRegister(reg);
    return 2;
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  } else if (format[1] == 'd') {  // 'rd: rd register.
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    int reg = instr->RdValue();
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    PrintRegister(reg);
    return 2;
  }
  UNREACHABLE();
  return -1;
}


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// Handle all FPUregister based formatting in this function to reduce the
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// complexity of FormatOption.
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int Decoder::FormatFPURegister(Instruction* instr, const char* format) {
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  DCHECK(format[0] == 'f');
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  if ((CTC1 == instr->RsFieldRaw()) || (CFC1 == instr->RsFieldRaw())) {
    if (format[1] == 's') {  // 'fs: fs register.
      int reg = instr->FsValue();
      PrintFPUStatusRegister(reg);
      return 2;
    } else if (format[1] == 't') {  // 'ft: ft register.
      int reg = instr->FtValue();
      PrintFPUStatusRegister(reg);
      return 2;
    } else if (format[1] == 'd') {  // 'fd: fd register.
      int reg = instr->FdValue();
      PrintFPUStatusRegister(reg);
      return 2;
    } else if (format[1] == 'r') {  // 'fr: fr register.
      int reg = instr->FrValue();
      PrintFPUStatusRegister(reg);
      return 2;
    }
  } else {
    if (format[1] == 's') {  // 'fs: fs register.
      int reg = instr->FsValue();
      PrintFPURegister(reg);
      return 2;
    } else if (format[1] == 't') {  // 'ft: ft register.
      int reg = instr->FtValue();
      PrintFPURegister(reg);
      return 2;
    } else if (format[1] == 'd') {  // 'fd: fd register.
      int reg = instr->FdValue();
      PrintFPURegister(reg);
      return 2;
    } else if (format[1] == 'r') {  // 'fr: fr register.
      int reg = instr->FrValue();
      PrintFPURegister(reg);
      return 2;
    }
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  }
  UNREACHABLE();
  return -1;
}


// FormatOption takes a formatting string and interprets it based on
// the current instructions. The format string points to the first
// character of the option string (the option escape has already been
// consumed by the caller.)  FormatOption returns the number of
// characters that were consumed from the formatting string.
int Decoder::FormatOption(Instruction* instr, const char* format) {
  switch (format[0]) {
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    case 'c': {   // 'code for break or trap instructions.
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      DCHECK(STRING_STARTS_WITH(format, "code"));
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      PrintCode(instr);
      return 4;
    }
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    case 'i': {   // 'imm16u or 'imm26.
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      if (format[3] == '1') {
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        if (format[4] == '6') {
          DCHECK(STRING_STARTS_WITH(format, "imm16"));
          switch (format[5]) {
            case 's':
              DCHECK(STRING_STARTS_WITH(format, "imm16s"));
              PrintSImm16(instr);
              break;
            case 'u':
              DCHECK(STRING_STARTS_WITH(format, "imm16u"));
              PrintSImm16(instr);
              break;
            case 'x':
              DCHECK(STRING_STARTS_WITH(format, "imm16x"));
              PrintXImm16(instr);
              break;
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            case 'p': {  // The PC relative address.
              DCHECK(STRING_STARTS_WITH(format, "imm16p"));
              int delta_pc = 0;
              int n_bits = 0;
              switch (format[6]) {
                case '4': {
                  DCHECK(STRING_STARTS_WITH(format, "imm16p4"));
                  delta_pc = 4;
                  switch (format[8]) {
                    case '2':
                      DCHECK(STRING_STARTS_WITH(format, "imm16p4s2"));
                      n_bits = 2;
                      PrintPCImm16(instr, delta_pc, n_bits);
                      return 9;
                  }
                }
              }
            }
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          }
          return 6;
        } else if (format[4] == '8') {
          DCHECK(STRING_STARTS_WITH(format, "imm18"));
          switch (format[5]) {
            case 's':
              DCHECK(STRING_STARTS_WITH(format, "imm18s"));
              PrintSImm18(instr);
              break;
            case 'x':
              DCHECK(STRING_STARTS_WITH(format, "imm18x"));
              PrintXImm18(instr);
              break;
          }
          return 6;
        } else if (format[4] == '9') {
          DCHECK(STRING_STARTS_WITH(format, "imm19"));
          switch (format[5]) {
            case 's':
              DCHECK(STRING_STARTS_WITH(format, "imm19s"));
              PrintSImm19(instr);
              break;
            case 'x':
              DCHECK(STRING_STARTS_WITH(format, "imm19x"));
              PrintXImm19(instr);
              break;
          }
          return 6;
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        }
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      } else if (format[3] == '2' && format[4] == '1') {
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        DCHECK(STRING_STARTS_WITH(format, "imm21"));
        switch (format[5]) {
          case 's':
            DCHECK(STRING_STARTS_WITH(format, "imm21s"));
            PrintSImm21(instr);
            break;
          case 'x':
            DCHECK(STRING_STARTS_WITH(format, "imm21x"));
            PrintXImm21(instr);
            break;
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          case 'p': {  // The PC relative address.
            DCHECK(STRING_STARTS_WITH(format, "imm21p"));
            int delta_pc = 0;
            int n_bits = 0;
            switch (format[6]) {
              case '4': {
                DCHECK(STRING_STARTS_WITH(format, "imm21p4"));
                delta_pc = 4;
                switch (format[8]) {
                  case '2':
                    DCHECK(STRING_STARTS_WITH(format, "imm21p4s2"));
                    n_bits = 2;
                    PrintPCImm21(instr, delta_pc, n_bits);
                    return 9;
                }
              }
            }
          }
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        }
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        return 6;
      } else if (format[3] == '2' && format[4] == '6') {
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        DCHECK(STRING_STARTS_WITH(format, "imm26"));
        switch (format[5]) {
          case 's':
            DCHECK(STRING_STARTS_WITH(format, "imm26s"));
            PrintSImm26(instr);
            break;
          case 'x':
            DCHECK(STRING_STARTS_WITH(format, "imm26x"));
            PrintXImm26(instr);
            break;
659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681
          case 'p': {  // The PC relative address.
            DCHECK(STRING_STARTS_WITH(format, "imm26p"));
            int delta_pc = 0;
            int n_bits = 0;
            switch (format[6]) {
              case '4': {
                DCHECK(STRING_STARTS_WITH(format, "imm26p4"));
                delta_pc = 4;
                switch (format[8]) {
                  case '2':
                    DCHECK(STRING_STARTS_WITH(format, "imm26p4s2"));
                    n_bits = 2;
                    PrintPCImm26(instr, delta_pc, n_bits);
                    return 9;
                }
              }
            }
          }
          case 'j': {  // Absolute address for jump instructions.
            DCHECK(STRING_STARTS_WITH(format, "imm26j"));
            PrintPCImm26(instr);
            break;
          }
682
        }
683
        return 6;
684 685
      }
    }
686
    case 'r': {   // 'r: registers.
687 688
      return FormatRegister(instr, format);
    }
689
    case 'f': {   // 'f: FPUregisters.
690
      return FormatFPURegister(instr, format);
691
    }
692
    case 's': {   // 'sa.
693
      switch (format[1]) {
694 695 696 697 698 699 700 701 702 703 704
        case 'a':
          if (format[2] == '2') {
            DCHECK(STRING_STARTS_WITH(format, "sa2"));  // 'sa2
            PrintLsaSa(instr);
            return 3;
          } else {
            DCHECK(STRING_STARTS_WITH(format, "sa"));
            PrintSa(instr);
            return 2;
          }
          break;
705
        case 'd': {
706
          DCHECK(STRING_STARTS_WITH(format, "sd"));
707 708 709
          PrintSd(instr);
          return 2;
        }
710 711
        case 's': {
          if (format[2] == '1') {
712
              DCHECK(STRING_STARTS_WITH(format, "ss1"));  /* ext size */
713 714 715
              PrintSs1(instr);
              return 3;
          } else {
716
              DCHECK(STRING_STARTS_WITH(format, "ss2"));  /* ins size */
717 718 719 720
              PrintSs2(instr);
              return 3;
          }
        }
721 722
      }
    }
723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739
    case 'b': {
      switch (format[1]) {
        case 'c': {  // 'bc - Special for bc1 cc field.
          DCHECK(STRING_STARTS_WITH(format, "bc"));
          PrintBc(instr);
          return 2;
        }
        case 'p': {
          switch (format[2]) {
            case '2': {  // 'bp2
              DCHECK(STRING_STARTS_WITH(format, "bp2"));
              PrintBp2(instr);
              return 3;
            }
          }
        }
      }
740 741
    }
    case 'C': {   // 'Cc - Special for c.xx.d cc field.
742
      DCHECK(STRING_STARTS_WITH(format, "Cc"));
743
      PrintCc(instr);
744 745
      return 2;
    }
746 747 748
    case 't':
      PrintFormat(instr);
      return 1;
749
  }
750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778
  UNREACHABLE();
  return -1;
}


// Format takes a formatting string for a whole instruction and prints it into
// the output buffer. All escaped options are handed to FormatOption to be
// parsed further.
void Decoder::Format(Instruction* instr, const char* format) {
  char cur = *format++;
  while ((cur != 0) && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
    if (cur == '\'') {  // Single quote is used as the formatting escape.
      format += FormatOption(instr, format);
    } else {
      out_buffer_[out_buffer_pos_++] = cur;
    }
    cur = *format++;
  }
  out_buffer_[out_buffer_pos_]  = '\0';
}


// For currently unimplemented decodings the disassembler calls Unknown(instr)
// which will just print "unknown" of the instruction bits.
void Decoder::Unknown(Instruction* instr) {
  Format(instr, "unknown");
}


779
bool Decoder::DecodeTypeRegisterRsType(Instruction* instr) {
780
  switch (instr->FunctionFieldRaw()) {
781 782 783
    case RINT:
      Format(instr, "rint.'t    'fd, 'fs");
      break;
784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804
    case MIN:
      Format(instr, "min.'t    'fd, 'fs, 'ft");
      break;
    case MAX:
      Format(instr, "max.'t    'fd, 'fs, 'ft");
      break;
    case MINA:
      Format(instr, "mina.'t   'fd, 'fs, 'ft");
      break;
    case MAXA:
      Format(instr, "maxa.'t   'fd, 'fs, 'ft");
      break;
    case SEL:
      Format(instr, "sel.'t      'fd, 'fs, 'ft");
      break;
    case SELEQZ_C:
      Format(instr, "seleqz.'t    'fd, 'fs, 'ft");
      break;
    case SELNEZ_C:
      Format(instr, "selnez.'t    'fd, 'fs, 'ft");
      break;
805 806 807 808 809 810 811 812 813 814 815 816 817
    case MOVZ_C:
      Format(instr, "movz.'t    'fd, 'fs, 'rt");
      break;
    case MOVN_C:
      Format(instr, "movn.'t    'fd, 'fs, 'rt");
      break;
    case MOVF:
      if (instr->Bit(16)) {
        Format(instr, "movt.'t    'fd, 'fs, 'Cc");
      } else {
        Format(instr, "movf.'t    'fd, 'fs, 'Cc");
      }
      break;
818
    case ADD_D:
819
      Format(instr, "add.'t   'fd, 'fs, 'ft");
820 821
      break;
    case SUB_D:
822
      Format(instr, "sub.'t   'fd, 'fs, 'ft");
823 824
      break;
    case MUL_D:
825
      Format(instr, "mul.'t   'fd, 'fs, 'ft");
826 827
      break;
    case DIV_D:
828
      Format(instr, "div.'t   'fd, 'fs, 'ft");
829 830
      break;
    case ABS_D:
831
      Format(instr, "abs.'t   'fd, 'fs");
832 833
      break;
    case MOV_D:
834
      Format(instr, "mov.'t   'fd, 'fs");
835 836
      break;
    case NEG_D:
837
      Format(instr, "neg.'t   'fd, 'fs");
838 839
      break;
    case SQRT_D:
840
      Format(instr, "sqrt.'t  'fd, 'fs");
841
      break;
842 843 844 845 846 847
    case RECIP_D:
      Format(instr, "recip.'t  'fd, 'fs");
      break;
    case RSQRT_D:
      Format(instr, "rsqrt.'t  'fd, 'fs");
      break;
848
    case CVT_W_D:
849
      Format(instr, "cvt.w.'t 'fd, 'fs");
850 851
      break;
    case CVT_L_D:
852
      Format(instr, "cvt.l.'t 'fd, 'fs");
853 854
      break;
    case TRUNC_W_D:
855
      Format(instr, "trunc.w.'t 'fd, 'fs");
856 857
      break;
    case TRUNC_L_D:
858
      Format(instr, "trunc.l.'t 'fd, 'fs");
859 860
      break;
    case ROUND_W_D:
861
      Format(instr, "round.w.'t 'fd, 'fs");
862
      break;
863 864 865
    case ROUND_L_D:
      Format(instr, "round.l.'t 'fd, 'fs");
      break;
866
    case FLOOR_W_D:
867
      Format(instr, "floor.w.'t 'fd, 'fs");
868
      break;
869 870 871
    case FLOOR_L_D:
      Format(instr, "floor.l.'t 'fd, 'fs");
      break;
872
    case CEIL_W_D:
873
      Format(instr, "ceil.w.'t 'fd, 'fs");
874
      break;
875 876 877
    case CLASS_D:
      Format(instr, "class.'t 'fd, 'fs");
      break;
878 879 880
    case CEIL_L_D:
      Format(instr, "ceil.l.'t 'fd, 'fs");
      break;
881
    case CVT_S_D:
882
      Format(instr, "cvt.s.'t 'fd, 'fs");
883 884
      break;
    case C_F_D:
885
      Format(instr, "c.f.'t   'fs, 'ft, 'Cc");
886 887
      break;
    case C_UN_D:
888
      Format(instr, "c.un.'t  'fs, 'ft, 'Cc");
889 890
      break;
    case C_EQ_D:
891
      Format(instr, "c.eq.'t  'fs, 'ft, 'Cc");
892 893
      break;
    case C_UEQ_D:
894
      Format(instr, "c.ueq.'t 'fs, 'ft, 'Cc");
895 896
      break;
    case C_OLT_D:
897
      Format(instr, "c.olt.'t 'fs, 'ft, 'Cc");
898 899
      break;
    case C_ULT_D:
900
      Format(instr, "c.ult.'t 'fs, 'ft, 'Cc");
901 902
      break;
    case C_OLE_D:
903
      Format(instr, "c.ole.'t 'fs, 'ft, 'Cc");
904 905
      break;
    case C_ULE_D:
906
      Format(instr, "c.ule.'t 'fs, 'ft, 'Cc");
907 908
      break;
    default:
909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931
      return false;
  }
  return true;
}


void Decoder::DecodeTypeRegisterSRsType(Instruction* instr) {
  if (!DecodeTypeRegisterRsType(instr)) {
    switch (instr->FunctionFieldRaw()) {
      case CVT_D_S:
        Format(instr, "cvt.d.'t 'fd, 'fs");
        break;
      default:
        Format(instr, "unknown.cop1.'t");
        break;
    }
  }
}


void Decoder::DecodeTypeRegisterDRsType(Instruction* instr) {
  if (!DecodeTypeRegisterRsType(instr)) {
    Format(instr, "unknown.cop1.'t");
932 933 934 935 936 937 938 939 940 941 942 943
  }
}


void Decoder::DecodeTypeRegisterLRsType(Instruction* instr) {
  switch (instr->FunctionFieldRaw()) {
    case CVT_D_L:
      Format(instr, "cvt.d.l 'fd, 'fs");
      break;
    case CVT_S_L:
      Format(instr, "cvt.s.l 'fd, 'fs");
      break;
944 945 946
    case CMP_AF:
      Format(instr, "cmp.af.d  'fd,  'fs, 'ft");
      break;
947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982
    case CMP_UN:
      Format(instr, "cmp.un.d  'fd,  'fs, 'ft");
      break;
    case CMP_EQ:
      Format(instr, "cmp.eq.d  'fd,  'fs, 'ft");
      break;
    case CMP_UEQ:
      Format(instr, "cmp.ueq.d  'fd,  'fs, 'ft");
      break;
    case CMP_LT:
      Format(instr, "cmp.lt.d  'fd,  'fs, 'ft");
      break;
    case CMP_ULT:
      Format(instr, "cmp.ult.d  'fd,  'fs, 'ft");
      break;
    case CMP_LE:
      Format(instr, "cmp.le.d  'fd,  'fs, 'ft");
      break;
    case CMP_ULE:
      Format(instr, "cmp.ule.d  'fd,  'fs, 'ft");
      break;
    case CMP_OR:
      Format(instr, "cmp.or.d  'fd,  'fs, 'ft");
      break;
    case CMP_UNE:
      Format(instr, "cmp.une.d  'fd,  'fs, 'ft");
      break;
    case CMP_NE:
      Format(instr, "cmp.ne.d  'fd,  'fs, 'ft");
      break;
    default:
      UNREACHABLE();
  }
}


983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029
void Decoder::DecodeTypeRegisterWRsType(Instruction* instr) {
  switch (instr->FunctionValue()) {
    case CVT_S_W:  // Convert word to float (single).
      Format(instr, "cvt.s.w 'fd, 'fs");
      break;
    case CVT_D_W:  // Convert word to double.
      Format(instr, "cvt.d.w 'fd, 'fs");
      break;
    case CMP_AF:
      Format(instr, "cmp.af.s    'fd, 'fs, 'ft");
      break;
    case CMP_UN:
      Format(instr, "cmp.un.s    'fd, 'fs, 'ft");
      break;
    case CMP_EQ:
      Format(instr, "cmp.eq.s    'fd, 'fs, 'ft");
      break;
    case CMP_UEQ:
      Format(instr, "cmp.ueq.s   'fd, 'fs, 'ft");
      break;
    case CMP_LT:
      Format(instr, "cmp.lt.s    'fd, 'fs, 'ft");
      break;
    case CMP_ULT:
      Format(instr, "cmp.ult.s   'fd, 'fs, 'ft");
      break;
    case CMP_LE:
      Format(instr, "cmp.le.s    'fd, 'fs, 'ft");
      break;
    case CMP_ULE:
      Format(instr, "cmp.ule.s   'fd, 'fs, 'ft");
      break;
    case CMP_OR:
      Format(instr, "cmp.or.s    'fd, 'fs, 'ft");
      break;
    case CMP_UNE:
      Format(instr, "cmp.une.s   'fd, 'fs, 'ft");
      break;
    case CMP_NE:
      Format(instr, "cmp.ne.s    'fd, 'fs, 'ft");
      break;
    default:
      UNREACHABLE();
  }
}


1030 1031 1032 1033 1034 1035
void Decoder::DecodeTypeRegisterSPECIAL(Instruction* instr) {
  switch (instr->FunctionFieldRaw()) {
    case JR:
      Format(instr, "jr      'rs");
      break;
    case JALR:
1036
      Format(instr, "jalr    'rs, 'rd");
1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074
      break;
    case SLL:
      if (0x0 == static_cast<int>(instr->InstructionBits()))
        Format(instr, "nop");
      else
        Format(instr, "sll     'rd, 'rt, 'sa");
      break;
    case SRL:
      if (instr->RsValue() == 0) {
        Format(instr, "srl     'rd, 'rt, 'sa");
      } else {
        if (IsMipsArchVariant(kMips32r2)) {
          Format(instr, "rotr    'rd, 'rt, 'sa");
        } else {
          Unknown(instr);
        }
      }
      break;
    case SRA:
      Format(instr, "sra     'rd, 'rt, 'sa");
      break;
    case SLLV:
      Format(instr, "sllv    'rd, 'rt, 'rs");
      break;
    case SRLV:
      if (instr->SaValue() == 0) {
        Format(instr, "srlv    'rd, 'rt, 'rs");
      } else {
        if (IsMipsArchVariant(kMips32r2)) {
          Format(instr, "rotrv   'rd, 'rt, 'rs");
        } else {
          Unknown(instr);
        }
      }
      break;
    case SRAV:
      Format(instr, "srav    'rd, 'rt, 'rs");
      break;
1075 1076 1077
    case LSA:
      Format(instr, "lsa     'rd, 'rt, 'rs, 'sa2");
      break;
1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207
    case MFHI:
      if (instr->Bits(25, 16) == 0) {
        Format(instr, "mfhi    'rd");
      } else {
        if ((instr->FunctionFieldRaw() == CLZ_R6) && (instr->FdValue() == 1)) {
          Format(instr, "clz     'rd, 'rs");
        } else if ((instr->FunctionFieldRaw() == CLO_R6) &&
                   (instr->FdValue() == 1)) {
          Format(instr, "clo     'rd, 'rs");
        }
      }
      break;
    case MFLO:
      Format(instr, "mflo    'rd");
      break;
    case MULT:  // @Mips32r6 == MUL_MUH.
      if (!IsMipsArchVariant(kMips32r6)) {
        Format(instr, "mult    'rs, 'rt");
      } else {
        if (instr->SaValue() == MUL_OP) {
          Format(instr, "mul    'rd, 'rs, 'rt");
        } else {
          Format(instr, "muh    'rd, 'rs, 'rt");
        }
      }
      break;
    case MULTU:  // @Mips32r6 == MUL_MUH_U.
      if (!IsMipsArchVariant(kMips32r6)) {
        Format(instr, "multu   'rs, 'rt");
      } else {
        if (instr->SaValue() == MUL_OP) {
          Format(instr, "mulu   'rd, 'rs, 'rt");
        } else {
          Format(instr, "muhu   'rd, 'rs, 'rt");
        }
      }
      break;
    case DIV:  // @Mips32r6 == DIV_MOD.
      if (!IsMipsArchVariant(kMips32r6)) {
        Format(instr, "div     'rs, 'rt");
      } else {
        if (instr->SaValue() == DIV_OP) {
          Format(instr, "div    'rd, 'rs, 'rt");
        } else {
          Format(instr, "mod    'rd, 'rs, 'rt");
        }
      }
      break;
    case DIVU:  // @Mips32r6 == DIV_MOD_U.
      if (!IsMipsArchVariant(kMips32r6)) {
        Format(instr, "divu    'rs, 'rt");
      } else {
        if (instr->SaValue() == DIV_OP) {
          Format(instr, "divu   'rd, 'rs, 'rt");
        } else {
          Format(instr, "modu   'rd, 'rs, 'rt");
        }
      }
      break;
    case ADD:
      Format(instr, "add     'rd, 'rs, 'rt");
      break;
    case ADDU:
      Format(instr, "addu    'rd, 'rs, 'rt");
      break;
    case SUB:
      Format(instr, "sub     'rd, 'rs, 'rt");
      break;
    case SUBU:
      Format(instr, "subu    'rd, 'rs, 'rt");
      break;
    case AND:
      Format(instr, "and     'rd, 'rs, 'rt");
      break;
    case OR:
      if (0 == instr->RsValue()) {
        Format(instr, "mov     'rd, 'rt");
      } else if (0 == instr->RtValue()) {
        Format(instr, "mov     'rd, 'rs");
      } else {
        Format(instr, "or      'rd, 'rs, 'rt");
      }
      break;
    case XOR:
      Format(instr, "xor     'rd, 'rs, 'rt");
      break;
    case NOR:
      Format(instr, "nor     'rd, 'rs, 'rt");
      break;
    case SLT:
      Format(instr, "slt     'rd, 'rs, 'rt");
      break;
    case SLTU:
      Format(instr, "sltu    'rd, 'rs, 'rt");
      break;
    case BREAK:
      Format(instr, "break, code: 'code");
      break;
    case TGE:
      Format(instr, "tge     'rs, 'rt, code: 'code");
      break;
    case TGEU:
      Format(instr, "tgeu    'rs, 'rt, code: 'code");
      break;
    case TLT:
      Format(instr, "tlt     'rs, 'rt, code: 'code");
      break;
    case TLTU:
      Format(instr, "tltu    'rs, 'rt, code: 'code");
      break;
    case TEQ:
      Format(instr, "teq     'rs, 'rt, code: 'code");
      break;
    case TNE:
      Format(instr, "tne     'rs, 'rt, code: 'code");
      break;
    case MOVZ:
      Format(instr, "movz    'rd, 'rs, 'rt");
      break;
    case MOVN:
      Format(instr, "movn    'rd, 'rs, 'rt");
      break;
    case MOVCI:
      if (instr->Bit(16)) {
        Format(instr, "movt    'rd, 'rs, 'bc");
      } else {
        Format(instr, "movf    'rd, 'rs, 'bc");
      }
      break;
    case SELEQZ_S:
1208
      Format(instr, "seleqz    'rd, 'rs, 'rt");
1209 1210
      break;
    case SELNEZ_S:
1211
      Format(instr, "selnez    'rd, 'rs, 'rt");
1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237
      break;
    default:
      UNREACHABLE();
  }
}


void Decoder::DecodeTypeRegisterSPECIAL2(Instruction* instr) {
  switch (instr->FunctionFieldRaw()) {
    case MUL:
      Format(instr, "mul     'rd, 'rs, 'rt");
      break;
    case CLZ:
      if (!IsMipsArchVariant(kMips32r6)) {
        Format(instr, "clz     'rd, 'rs");
      }
      break;
    default:
      UNREACHABLE();
  }
}


void Decoder::DecodeTypeRegisterSPECIAL3(Instruction* instr) {
  switch (instr->FunctionFieldRaw()) {
    case INS: {
1238
      if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
1239 1240 1241 1242 1243 1244 1245
        Format(instr, "ins     'rt, 'rs, 'sa, 'ss2");
      } else {
        Unknown(instr);
      }
      break;
    }
    case EXT: {
1246
      if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
1247 1248 1249 1250 1251 1252
        Format(instr, "ext     'rt, 'rs, 'sa, 'ss1");
      } else {
        Unknown(instr);
      }
      break;
    }
1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284
    case BSHFL: {
      int sa = instr->SaFieldRaw() >> kSaShift;
      switch (sa) {
        case BITSWAP: {
          if (IsMipsArchVariant(kMips32r6)) {
            Format(instr, "bitswap 'rd, 'rt");
          } else {
            Unknown(instr);
          }
          break;
        }
        case SEB:
        case SEH:
        case WSBH:
          UNREACHABLE();
          break;
        default: {
          sa >>= kBp2Bits;
          switch (sa) {
            case ALIGN: {
              if (IsMipsArchVariant(kMips32r6)) {
                Format(instr, "align  'rd, 'rs, 'rt, 'bp2");
              } else {
                Unknown(instr);
              }
              break;
            }
            default:
              UNREACHABLE();
              break;
          }
        }
1285 1286 1287
      }
      break;
    }
1288 1289 1290 1291 1292 1293
    default:
      UNREACHABLE();
  }
}


1294 1295
void Decoder::DecodeTypeRegister(Instruction* instr) {
  switch (instr->OpcodeFieldRaw()) {
1296
    case COP1:    // Coprocessor instructions.
1297
      switch (instr->RsFieldRaw()) {
1298
        case BC1:   // bc1 handled in DecodeTypeImmediate.
1299 1300 1301
          UNREACHABLE();
          break;
        case MFC1:
1302
          Format(instr, "mfc1    'rt, 'fs");
1303 1304
          break;
        case MFHC1:
1305
          Format(instr, "mfhc1   'rt, 'fs");
1306 1307
          break;
        case MTC1:
1308
          Format(instr, "mtc1    'rt, 'fs");
1309 1310 1311
          break;
        // These are called "fs" too, although they are not FPU registers.
        case CTC1:
1312
          Format(instr, "ctc1    'rt, 'fs");
1313 1314
          break;
        case CFC1:
1315
          Format(instr, "cfc1    'rt, 'fs");
1316 1317
          break;
        case MTHC1:
1318
          Format(instr, "mthc1   'rt, 'fs");
1319
          break;
1320 1321 1322
        case S:
          DecodeTypeRegisterSRsType(instr);
          break;
1323
        case D:
1324
          DecodeTypeRegisterDRsType(instr);
1325
          break;
1326
        case L:
1327
          DecodeTypeRegisterLRsType(instr);
1328
          break;
1329 1330 1331
        case W:
          DecodeTypeRegisterWRsType(instr);
          break;
1332 1333 1334 1335 1336
        case PS:
          UNIMPLEMENTED_MIPS();
          break;
        default:
          UNREACHABLE();
1337
      }
1338
      break;
1339 1340 1341 1342 1343 1344 1345
    case COP1X:
      switch (instr->FunctionFieldRaw()) {
        case MADD_D:
          Format(instr, "madd.d  'fd, 'fr, 'fs, 'ft");
          break;
        default:
          UNREACHABLE();
1346
      }
1347
      break;
1348
    case SPECIAL:
1349
      DecodeTypeRegisterSPECIAL(instr);
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      break;
    case SPECIAL2:
1352
      DecodeTypeRegisterSPECIAL2(instr);
1353 1354
      break;
    case SPECIAL3:
1355
      DecodeTypeRegisterSPECIAL3(instr);
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      break;
    default:
      UNREACHABLE();
1359
  }
1360 1361 1362 1363 1364
}


void Decoder::DecodeTypeImmediate(Instruction* instr) {
  switch (instr->OpcodeFieldRaw()) {
1365 1366 1367 1368
    case COP1:
      switch (instr->RsFieldRaw()) {
        case BC1:
          if (instr->FBtrueValue()) {
1369
            Format(instr, "bc1t    'bc, 'imm16u -> 'imm16p4s2");
1370
          } else {
1371
            Format(instr, "bc1f    'bc, 'imm16u -> 'imm16p4s2");
1372 1373
          }
          break;
1374
        case BC1EQZ:
1375
          Format(instr, "bc1eqz    'ft, 'imm16u -> 'imm16p4s2");
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          break;
        case BC1NEZ:
1378
          Format(instr, "bc1nez    'ft, 'imm16u -> 'imm16p4s2");
1379
          break;
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        default:
          UNREACHABLE();
1382
      }
1383

1384
      break;  // Case COP1.
1385
    // ------------- REGIMM class.
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    case REGIMM:
      switch (instr->RtFieldRaw()) {
        case BLTZ:
1389
          Format(instr, "bltz    'rs, 'imm16u -> 'imm16p4s2");
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          break;
        case BLTZAL:
1392
          Format(instr, "bltzal  'rs, 'imm16u -> 'imm16p4s2");
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          break;
        case BGEZ:
1395
          Format(instr, "bgez    'rs, 'imm16u -> 'imm16p4s2");
1396
          break;
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        case BGEZAL: {
          if (instr->RsValue() == 0)
            Format(instr, "bal     'imm16s -> 'imm16p4s2");
          else
            Format(instr, "bgezal  'rs, 'imm16u -> 'imm16p4s2");
1402
          break;
1403
        }
1404
        case BGEZALL:
1405
          Format(instr, "bgezall 'rs, 'imm16u -> 'imm16p4s2");
1406
          break;
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        default:
          UNREACHABLE();
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      }
    break;  // Case REGIMM.
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    // ------------- Branch instructions.
    case BEQ:
1413
      Format(instr, "beq     'rs, 'rt, 'imm16u -> 'imm16p4s2");
1414
      break;
1415
    case BC:
1416
      Format(instr, "bc      'imm26s -> 'imm26p4s2");
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      break;
    case BALC:
1419
      Format(instr, "balc    'imm26s -> 'imm26p4s2");
1420
      break;
1421
    case BNE:
1422
      Format(instr, "bne     'rs, 'rt, 'imm16u -> 'imm16p4s2");
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      break;
    case BLEZ:
1425 1426 1427 1428
      if ((instr->RtValue() == 0) && (instr->RsValue() != 0)) {
        Format(instr, "blez    'rs, 'imm16u -> 'imm16p4s2");
      } else if ((instr->RtValue() != instr->RsValue()) &&
                 (instr->RsValue() != 0) && (instr->RtValue() != 0)) {
1429
        Format(instr, "bgeuc   'rs, 'rt, 'imm16u -> 'imm16p4s2");
1430 1431
      } else if ((instr->RtValue() == instr->RsValue()) &&
                 (instr->RtValue() != 0)) {
1432
        Format(instr, "bgezalc 'rs, 'imm16u -> 'imm16p4s2");
1433
      } else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
1434
        Format(instr, "blezalc 'rt, 'imm16u -> 'imm16p4s2");
1435 1436 1437
      } else {
        UNREACHABLE();
      }
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      break;
    case BGTZ:
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      if ((instr->RtValue() == 0) && (instr->RsValue() != 0)) {
        Format(instr, "bgtz    'rs, 'imm16u -> 'imm16p4s2");
      } else if ((instr->RtValue() != instr->RsValue()) &&
                 (instr->RsValue() != 0) && (instr->RtValue() != 0)) {
        Format(instr, "bltuc   'rs, 'rt, 'imm16u -> 'imm16p4s2");
      } else if ((instr->RtValue() == instr->RsValue()) &&
                 (instr->RtValue() != 0)) {
        Format(instr, "bltzalc 'rt, 'imm16u -> 'imm16p4s2");
      } else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
        Format(instr, "bgtzalc 'rt, 'imm16u -> 'imm16p4s2");
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      } else {
        UNREACHABLE();
      }
      break;
    case BLEZL:
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      if ((instr->RtValue() == instr->RsValue()) && (instr->RtValue() != 0)) {
        Format(instr, "bgezc    'rt, 'imm16u -> 'imm16p4s2");
      } else if ((instr->RtValue() != instr->RsValue()) &&
                 (instr->RsValue() != 0) && (instr->RtValue() != 0)) {
        Format(instr, "bgec     'rs, 'rt, 'imm16u -> 'imm16p4s2");
      } else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
        Format(instr, "blezc    'rt, 'imm16u -> 'imm16p4s2");
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      } else {
        UNREACHABLE();
      }
      break;
    case BGTZL:
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      if ((instr->RtValue() == instr->RsValue()) && (instr->RtValue() != 0)) {
        Format(instr, "bltzc    'rt, 'imm16u -> 'imm16p4s2");
      } else if ((instr->RtValue() != instr->RsValue()) &&
                 (instr->RsValue() != 0) && (instr->RtValue() != 0)) {
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        Format(instr, "bltc    'rs, 'rt, 'imm16u -> 'imm16p4s2");
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      } else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
        Format(instr, "bgtzc    'rt, 'imm16u -> 'imm16p4s2");
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      } else {
        UNREACHABLE();
      }
      break;
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    case POP66:
      if (instr->RsValue() == JIC) {
        Format(instr, "jic     'rt, 'imm16s");
      } else {
1482
        Format(instr, "beqzc   'rs, 'imm21s -> 'imm21p4s2");
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      }
      break;
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    case POP76:
      if (instr->RsValue() == JIALC) {
1487
        Format(instr, "jialc   'rt, 'imm16s");
1488
      } else {
1489
        Format(instr, "bnezc   'rs, 'imm21s -> 'imm21p4s2");
1490
      }
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      break;
    // ------------- Arithmetic instructions.
    case ADDI:
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      if (!IsMipsArchVariant(kMips32r6)) {
        Format(instr, "addi    'rt, 'rs, 'imm16s");
      } else {
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        int rs_reg = instr->RsValue();
        int rt_reg = instr->RtValue();
        // Check if BOVC, BEQZALC or BEQC instruction.
        if (rs_reg >= rt_reg) {
1501
          Format(instr, "bovc  'rs, 'rt, 'imm16s -> 'imm16p4s2");
1502
        } else {
1503
          DCHECK(rt_reg > 0);
1504 1505 1506 1507 1508
          if (rs_reg == 0) {
            Format(instr, "beqzalc 'rt, 'imm16s -> 'imm16p4s2");
          } else {
            Format(instr, "beqc    'rs, 'rt, 'imm16s -> 'imm16p4s2");
          }
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        }
      }
      break;
    case DADDI:
      if (IsMipsArchVariant(kMips32r6)) {
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        int rs_reg = instr->RsValue();
        int rt_reg = instr->RtValue();
        // Check if BNVC, BNEZALC or BNEC instruction.
        if (rs_reg >= rt_reg) {
1518
          Format(instr, "bnvc  'rs, 'rt, 'imm16s -> 'imm16p4s2");
1519
        } else {
1520
          DCHECK(rt_reg > 0);
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          if (rs_reg == 0) {
            Format(instr, "bnezalc 'rt, 'imm16s -> 'imm16p4s2");
          } else {
            Format(instr, "bnec  'rs, 'rt, 'imm16s -> 'imm16p4s2");
          }
1526 1527
        }
      }
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      break;
    case ADDIU:
1530
      Format(instr, "addiu   'rt, 'rs, 'imm16s");
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      break;
    case SLTI:
1533
      Format(instr, "slti    'rt, 'rs, 'imm16s");
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      break;
    case SLTIU:
1536
      Format(instr, "sltiu   'rt, 'rs, 'imm16u");
1537 1538
      break;
    case ANDI:
1539
      Format(instr, "andi    'rt, 'rs, 'imm16x");
1540 1541
      break;
    case ORI:
1542
      Format(instr, "ori     'rt, 'rs, 'imm16x");
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      break;
    case XORI:
1545
      Format(instr, "xori    'rt, 'rs, 'imm16x");
1546 1547
      break;
    case LUI:
1548 1549 1550 1551
      if (!IsMipsArchVariant(kMips32r6)) {
        Format(instr, "lui     'rt, 'imm16x");
      } else {
        if (instr->RsValue() != 0) {
1552
          Format(instr, "aui     'rt, 'rs, 'imm16x");
1553 1554 1555 1556
        } else {
          Format(instr, "lui     'rt, 'imm16x");
        }
      }
1557 1558 1559
      break;
    // ------------- Memory instructions.
    case LB:
1560
      Format(instr, "lb      'rt, 'imm16s('rs)");
1561
      break;
1562
    case LH:
1563
      Format(instr, "lh      'rt, 'imm16s('rs)");
1564 1565
      break;
    case LWL:
1566
      Format(instr, "lwl     'rt, 'imm16s('rs)");
1567
      break;
1568
    case LW:
1569
      Format(instr, "lw      'rt, 'imm16s('rs)");
1570 1571
      break;
    case LBU:
1572
      Format(instr, "lbu     'rt, 'imm16s('rs)");
1573
      break;
1574
    case LHU:
1575
      Format(instr, "lhu     'rt, 'imm16s('rs)");
1576 1577
      break;
    case LWR:
1578
      Format(instr, "lwr     'rt, 'imm16s('rs)");
1579
      break;
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plind44@gmail.com committed
1580 1581 1582
    case PREF:
      Format(instr, "pref    'rt, 'imm16s('rs)");
      break;
1583
    case SB:
1584
      Format(instr, "sb      'rt, 'imm16s('rs)");
1585
      break;
1586
    case SH:
1587
      Format(instr, "sh      'rt, 'imm16s('rs)");
1588 1589
      break;
    case SWL:
1590
      Format(instr, "swl     'rt, 'imm16s('rs)");
1591
      break;
1592
    case SW:
1593
      Format(instr, "sw      'rt, 'imm16s('rs)");
1594
      break;
1595
    case SWR:
1596
      Format(instr, "swr     'rt, 'imm16s('rs)");
1597
      break;
1598
    case LWC1:
1599
      Format(instr, "lwc1    'ft, 'imm16s('rs)");
1600 1601
      break;
    case LDC1:
1602
      Format(instr, "ldc1    'ft, 'imm16s('rs)");
1603 1604
      break;
    case SWC1:
1605
      Format(instr, "swc1    'ft, 'imm16s('rs)");
1606 1607
      break;
    case SDC1:
1608
      Format(instr, "sdc1    'ft, 'imm16s('rs)");
1609
      break;
1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638
    case PCREL: {
      int32_t imm21 = instr->Imm21Value();
      // rt field: 5-bits checking
      uint8_t rt = (imm21 >> kImm16Bits);
      switch (rt) {
        case ALUIPC:
          Format(instr, "aluipc  'rs, 'imm16s");
          break;
        case AUIPC:
          Format(instr, "auipc   'rs, 'imm16s");
          break;
        default: {
          // rt field: checking of the most significant 2-bits
          rt = (imm21 >> kImm19Bits);
          switch (rt) {
            case LWPC:
              Format(instr, "lwpc    'rs, 'imm19s");
              break;
            case ADDIUPC:
              Format(instr, "addiupc 'rs, 'imm19s");
              break;
            default:
              UNREACHABLE();
              break;
          }
        }
      }
      break;
    }
1639
    default:
1640
      printf("a 0x%x \n", instr->OpcodeFieldRaw());
1641 1642
      UNREACHABLE();
      break;
1643
  }
1644 1645 1646 1647 1648 1649
}


void Decoder::DecodeTypeJump(Instruction* instr) {
  switch (instr->OpcodeFieldRaw()) {
    case J:
1650
      Format(instr, "j       'imm26x -> 'imm26j");
1651 1652
      break;
    case JAL:
1653
      Format(instr, "jal     'imm26x -> 'imm26j");
1654 1655 1656 1657 1658 1659 1660 1661
      break;
    default:
      UNREACHABLE();
  }
}


// Disassemble the instruction at *instr_ptr into the output buffer.
1662
int Decoder::InstructionDecode(byte* instr_ptr) {
1663 1664
  Instruction* instr = Instruction::At(instr_ptr);
  // Print raw instruction bytes.
1665 1666 1667
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                   "%08x       ",
                                   instr->InstructionBits());
1668
  switch (instr->InstructionType(Instruction::EXTRA)) {
1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681
    case Instruction::kRegisterType: {
      DecodeTypeRegister(instr);
      break;
    }
    case Instruction::kImmediateType: {
      DecodeTypeImmediate(instr);
      break;
    }
    case Instruction::kJumpType: {
      DecodeTypeJump(instr);
      break;
    }
    default: {
1682
      Format(instr, "UNSUPPORTED");
1683 1684 1685
      UNSUPPORTED_MIPS();
    }
  }
1686
  return Instruction::kInstrSize;
1687 1688 1689
}


1690 1691
}  // namespace internal
}  // namespace v8
1692 1693 1694 1695 1696 1697


//------------------------------------------------------------------------------

namespace disasm {

1698
const char* NameConverter::NameOfAddress(byte* addr) const {
1699
  v8::internal::SNPrintF(tmp_buffer_, "%p", addr);
1700
  return tmp_buffer_.start();
1701 1702 1703
}


1704
const char* NameConverter::NameOfConstant(byte* addr) const {
1705 1706 1707 1708 1709
  return NameOfAddress(addr);
}


const char* NameConverter::NameOfCPURegister(int reg) const {
1710
  return v8::internal::Registers::Name(reg);
1711 1712 1713 1714
}


const char* NameConverter::NameOfXMMRegister(int reg) const {
1715
  return v8::internal::FPURegisters::Name(reg);
1716 1717 1718 1719
}


const char* NameConverter::NameOfByteCPURegister(int reg) const {
1720
  UNREACHABLE();  // MIPS does not have the concept of a byte register.
1721 1722 1723 1724
  return "nobytereg";
}


1725
const char* NameConverter::NameInCode(byte* addr) const {
1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741
  // The default name converter is called for unknown code. So we will not try
  // to access any memory.
  return "";
}


//------------------------------------------------------------------------------

Disassembler::Disassembler(const NameConverter& converter)
    : converter_(converter) {}


Disassembler::~Disassembler() {}


int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
1742
                                    byte* instruction) {
1743
  v8::internal::Decoder d(converter_, buffer);
1744 1745 1746 1747
  return d.InstructionDecode(instruction);
}


1748
// The MIPS assembler does not currently use constant pools.
1749
int Disassembler::ConstantPoolSizeAt(byte* instruction) {
1750 1751 1752 1753
  return -1;
}


1754
void Disassembler::Disassemble(FILE* f, byte* begin, byte* end) {
1755 1756
  NameConverter converter;
  Disassembler d(converter);
1757
  for (byte* pc = begin; pc < end;) {
1758 1759
    v8::internal::EmbeddedVector<char, 128> buffer;
    buffer[0] = '\0';
1760
    byte* prev_pc = pc;
1761
    pc += d.InstructionDecode(buffer, pc);
1762 1763
    v8::internal::PrintF(f, "%p    %08x      %s\n",
        prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
1764 1765 1766
  }
}

1767

1768 1769 1770 1771
#undef UNSUPPORTED

}  // namespace disasm

1772
#endif  // V8_TARGET_ARCH_MIPS