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Commit 70c90758 authored by Djordje.Pesic's avatar Djordje.Pesic Committed by Commit bot
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MIPS: Fix bug in disassembler for JALR 

Adding missing rd register in JALR disassembly, for mips and mipps64

Review URL: https://codereview.chromium.org/1297183002

Cr-Commit-Position: refs/heads/master@{#30214}
parent 4106a4cb
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Showing with 2 additions and 2 deletions
src/mips/disasm-mips.cc
View file @ 70c90758
......@@ -987,7 +987,7 @@ void Decoder::DecodeTypeRegisterSPECIAL(Instruction* instr) {
Format(instr, "jr 'rs");
break;
case JALR:
Format(instr, "jalr 'rs");
Format(instr, "jalr 'rs, 'rd");
break;
case SLL:
if (0x0 == static_cast<int>(instr->InstructionBits()))
......
src/mips64/disasm-mips64.cc
View file @ 70c90758
......@@ -1073,7 +1073,7 @@ void Decoder::DecodeTypeRegisterSPECIAL(Instruction* instr) {
Format(instr, "jr 'rs");
break;
case JALR:
Format(instr, "jalr 'rs");
Format(instr, "jalr 'rs, 'rd");
break;
case SLL:
if (0x0 == static_cast<int>(instr->InstructionBits()))
......
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