assembler-s390.cc 79.7 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
// Copyright (c) 1994-2006 Sun Microsystems Inc.
// All Rights Reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistribution in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// - Neither the name of Sun Microsystems or the names of contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
// OF THE POSSIBILITY OF SUCH DAMAGE.

// The original source code covered by the above license above has been
// modified significantly by Google Inc.
// Copyright 2014 the V8 project authors. All rights reserved.

#include "src/s390/assembler-s390.h"
38 39 40
#include <sys/auxv.h>
#include <set>
#include <string>
41 42 43 44 45 46 47 48 49

#if V8_TARGET_ARCH_S390

#if V8_HOST_ARCH_S390
#include <elf.h>  // Required for auxv checks for STFLE support
#endif

#include "src/base/bits.h"
#include "src/base/cpu.h"
50
#include "src/code-stubs.h"
51
#include "src/macro-assembler.h"
52
#include "src/s390/assembler-s390-inl.h"
53 54 55 56 57 58 59 60 61 62

namespace v8 {
namespace internal {

// Get the CPU features enabled by the build.
static unsigned CpuFeaturesImpliedByCompiler() {
  unsigned answer = 0;
  return answer;
}

63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
static bool supportsCPUFeature(const char* feature) {
  static std::set<std::string> features;
  static std::set<std::string> all_available_features = {
      "iesan3", "zarch",  "stfle",    "msa", "ldisp", "eimm",
      "dfp",    "etf3eh", "highgprs", "te",  "vx"};
  if (features.empty()) {
#if V8_HOST_ARCH_S390

#ifndef HWCAP_S390_VX
#define HWCAP_S390_VX 2048
#endif
#define CHECK_AVAILABILITY_FOR(mask, value) \
  if (f & mask) features.insert(value);

    // initialize feature vector
    uint64_t f = getauxval(AT_HWCAP);
    CHECK_AVAILABILITY_FOR(HWCAP_S390_ESAN3, "iesan3")
    CHECK_AVAILABILITY_FOR(HWCAP_S390_ZARCH, "zarch")
    CHECK_AVAILABILITY_FOR(HWCAP_S390_STFLE, "stfle")
    CHECK_AVAILABILITY_FOR(HWCAP_S390_MSA, "msa")
    CHECK_AVAILABILITY_FOR(HWCAP_S390_LDISP, "ldisp")
    CHECK_AVAILABILITY_FOR(HWCAP_S390_EIMM, "eimm")
    CHECK_AVAILABILITY_FOR(HWCAP_S390_DFP, "dfp")
    CHECK_AVAILABILITY_FOR(HWCAP_S390_ETF3EH, "etf3eh")
    CHECK_AVAILABILITY_FOR(HWCAP_S390_HIGH_GPRS, "highgprs")
    CHECK_AVAILABILITY_FOR(HWCAP_S390_TE, "te")
    CHECK_AVAILABILITY_FOR(HWCAP_S390_VX, "vx")
#else
    // import all features
    features.insert(all_available_features.begin(),
                    all_available_features.end());
#endif
  }
  USE(all_available_features);
  return features.find(feature) != features.end();
}

100 101 102 103 104 105 106 107
// Check whether Store Facility STFLE instruction is available on the platform.
// Instruction returns a bit vector of the enabled hardware facilities.
static bool supportsSTFLE() {
#if V8_HOST_ARCH_S390
  static bool read_tried = false;
  static uint32_t auxv_hwcap = 0;

  if (!read_tried) {
108
    // Open the AUXV (auxiliary vector) pseudo-file
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148
    int fd = open("/proc/self/auxv", O_RDONLY);

    read_tried = true;
    if (fd != -1) {
#if V8_TARGET_ARCH_S390X
      static Elf64_auxv_t buffer[16];
      Elf64_auxv_t* auxv_element;
#else
      static Elf32_auxv_t buffer[16];
      Elf32_auxv_t* auxv_element;
#endif
      int bytes_read = 0;
      while (bytes_read >= 0) {
        // Read a chunk of the AUXV
        bytes_read = read(fd, buffer, sizeof(buffer));
        // Locate and read the platform field of AUXV if it is in the chunk
        for (auxv_element = buffer;
             auxv_element + sizeof(auxv_element) <= buffer + bytes_read &&
             auxv_element->a_type != AT_NULL;
             auxv_element++) {
          // We are looking for HWCAP entry in AUXV to search for STFLE support
          if (auxv_element->a_type == AT_HWCAP) {
            /* Note: Both auxv_hwcap and buffer are static */
            auxv_hwcap = auxv_element->a_un.a_val;
            goto done_reading;
          }
        }
      }
    done_reading:
      close(fd);
    }
  }

  // Did not find result
  if (0 == auxv_hwcap) {
    return false;
  }

  // HWCAP_S390_STFLE is defined to be 4 in include/asm/elf.h.  Currently
  // hardcoded in case that include file does not exist.
149 150
  const uint32_t _HWCAP_S390_STFLE = 4;
  return (auxv_hwcap & _HWCAP_S390_STFLE);
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
#else
  // STFLE is not available on non-s390 hosts
  return false;
#endif
}

void CpuFeatures::ProbeImpl(bool cross_compile) {
  supported_ |= CpuFeaturesImpliedByCompiler();
  icache_line_size_ = 256;

  // Only use statically determined features for cross compile (snapshot).
  if (cross_compile) return;

#ifdef DEBUG
  initialized_ = true;
#endif

  static bool performSTFLE = supportsSTFLE();

// Need to define host, as we are generating inlined S390 assembly to test
// for facilities.
#if V8_HOST_ARCH_S390
  if (performSTFLE) {
    // STFLE D(B) requires:
    //    GPR0 to specify # of double words to update minus 1.
    //      i.e. GPR0 = 0 for 1 doubleword
    //    D(B) to specify to memory location to store the facilities bits
    // The facilities we are checking for are:
    //   Bit 45 - Distinct Operands for instructions like ARK, SRK, etc.
    // As such, we require only 1 double word
181
    int64_t facilities[3] = {0L};
182 183 184 185
    // LHI sets up GPR0
    // STFLE is specified as .insn, as opcode is not recognized.
    // We register the instructions kill r0 (LHI) and the CC (STFLE).
    asm volatile(
186
        "lhi   0,2\n"
187 188 189 190 191
        ".insn s,0xb2b00000,%0\n"
        : "=Q"(facilities)
        :
        : "cc", "r0");

192
    uint64_t one = static_cast<uint64_t>(1);
193
    // Test for Distinct Operands Facility - Bit 45
194
    if (facilities[0] & (one << (63 - 45))) {
195 196 197
      supported_ |= (1u << DISTINCT_OPS);
    }
    // Test for General Instruction Extension Facility - Bit 34
198
    if (facilities[0] & (one << (63 - 34))) {
199 200 201
      supported_ |= (1u << GENERAL_INSTR_EXT);
    }
    // Test for Floating Point Extension Facility - Bit 37
202
    if (facilities[0] & (one << (63 - 37))) {
203 204
      supported_ |= (1u << FLOATING_POINT_EXT);
    }
205
    // Test for Vector Facility - Bit 129
206 207
    if (facilities[2] & (one << (63 - (129 - 128))) &&
        supportsCPUFeature("vx")) {
208 209
      supported_ |= (1u << VECTOR_FACILITY);
    }
jyan's avatar
jyan committed
210 211 212 213
    // Test for Miscellaneous Instruction Extension Facility - Bit 58
    if (facilities[0] & (1lu << (63 - 58))) {
      supported_ |= (1u << MISC_INSTR_EXT2);
    }
214 215 216 217 218 219 220
  }
#else
  // All distinct ops instructions can be simulated
  supported_ |= (1u << DISTINCT_OPS);
  // RISBG can be simulated
  supported_ |= (1u << GENERAL_INSTR_EXT);
  supported_ |= (1u << FLOATING_POINT_EXT);
jyan's avatar
jyan committed
221
  supported_ |= (1u << MISC_INSTR_EXT2);
222
  USE(performSTFLE);  // To avoid assert
223
  USE(supportsCPUFeature);
224
  supported_ |= (1u << VECTOR_FACILITY);
225 226 227 228 229
#endif
  supported_ |= (1u << FPU);
}

void CpuFeatures::PrintTarget() {
230
  const char* s390_arch = nullptr;
231 232 233 234 235 236 237 238 239 240 241 242 243 244 245

#if V8_TARGET_ARCH_S390X
  s390_arch = "s390x";
#else
  s390_arch = "s390";
#endif

  printf("target %s\n", s390_arch);
}

void CpuFeatures::PrintFeatures() {
  printf("FPU=%d\n", CpuFeatures::IsSupported(FPU));
  printf("FPU_EXT=%d\n", CpuFeatures::IsSupported(FLOATING_POINT_EXT));
  printf("GENERAL_INSTR=%d\n", CpuFeatures::IsSupported(GENERAL_INSTR_EXT));
  printf("DISTINCT_OPS=%d\n", CpuFeatures::IsSupported(DISTINCT_OPS));
246
  printf("VECTOR_FACILITY=%d\n", CpuFeatures::IsSupported(VECTOR_FACILITY));
jyan's avatar
jyan committed
247
  printf("MISC_INSTR_EXT2=%d\n", CpuFeatures::IsSupported(MISC_INSTR_EXT2));
248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272
}

Register ToRegister(int num) {
  DCHECK(num >= 0 && num < kNumRegisters);
  const Register kRegisters[] = {r0, r1, r2,  r3, r4, r5,  r6,  r7,
                                 r8, r9, r10, fp, ip, r13, r14, sp};
  return kRegisters[num];
}

// -----------------------------------------------------------------------------
// Implementation of RelocInfo

const int RelocInfo::kApplyMask =
    RelocInfo::kCodeTargetMask | 1 << RelocInfo::INTERNAL_REFERENCE;

bool RelocInfo::IsCodedSpecially() {
  // The deserializer needs to know whether a pointer is specially
  // coded.  Being specially coded on S390 means that it is an iihf/iilf
  // instruction sequence, and that is always the case inside code
  // objects.
  return true;
}

bool RelocInfo::IsInConstantPool() { return false; }

273
Address RelocInfo::embedded_address() const {
274
  return Assembler::target_address_at(pc_, constant_pool_);
275 276
}

277
uint32_t RelocInfo::embedded_size() const {
278 279
  return static_cast<uint32_t>(reinterpret_cast<intptr_t>(
      Assembler::target_address_at(pc_, constant_pool_)));
280 281
}

282
void RelocInfo::set_embedded_address(Address address,
283
                                     ICacheFlushMode flush_mode) {
284
  Assembler::set_target_address_at(pc_, constant_pool_, address, flush_mode);
285 286
}

287 288
void RelocInfo::set_embedded_size(uint32_t size, ICacheFlushMode flush_mode) {
  Assembler::set_target_address_at(pc_, constant_pool_,
289
                                   reinterpret_cast<Address>(size), flush_mode);
290 291
}

292
void RelocInfo::set_js_to_wasm_address(Address address,
293 294
                                       ICacheFlushMode icache_flush_mode) {
  DCHECK_EQ(rmode_, JS_TO_WASM_CALL);
295
  set_embedded_address(address, icache_flush_mode);
296 297 298 299 300 301 302
}

Address RelocInfo::js_to_wasm_address() const {
  DCHECK_EQ(rmode_, JS_TO_WASM_CALL);
  return embedded_address();
}

303 304 305 306
// -----------------------------------------------------------------------------
// Implementation of Operand and MemOperand
// See assembler-s390-inl.h for inlined constructors

307 308
Operand::Operand(Handle<HeapObject> handle) {
  AllowHandleDereference using_location;
309
  rm_ = no_reg;
310
  value_.immediate = reinterpret_cast<intptr_t>(handle.address());
311
  rmode_ = RelocInfo::EMBEDDED_OBJECT;
312 313
}

314 315 316 317 318 319 320 321 322
Operand Operand::EmbeddedNumber(double value) {
  int32_t smi;
  if (DoubleToSmiInteger(value, &smi)) return Operand(Smi::FromInt(smi));
  Operand result(0, RelocInfo::EMBEDDED_OBJECT);
  result.is_heap_object_request_ = true;
  result.value_.heap_object_request = HeapObjectRequest(value);
  return result;
}

323 324
MemOperand::MemOperand(Register rn, int32_t offset)
    : baseRegister(rn), indexRegister(r0), offset_(offset) {}
325

326 327
MemOperand::MemOperand(Register rx, Register rb, int32_t offset)
    : baseRegister(rb), indexRegister(rx), offset_(offset) {}
328

329 330 331 332 333 334 335 336
void Assembler::AllocateAndInstallRequestedHeapObjects(Isolate* isolate) {
  for (auto& request : heap_object_requests_) {
    Handle<HeapObject> object;
    Address pc = buffer_ + request.offset();
    switch (request.kind()) {
      case HeapObjectRequest::kHeapNumber:
        object = isolate->factory()->NewHeapNumber(request.heap_number(),
                                                   IMMUTABLE, TENURED);
337
        set_target_address_at(pc, static_cast<Address>(nullptr),
338 339 340 341 342 343 344 345 346 347 348 349 350 351
                              reinterpret_cast<Address>(object.location()),
                              SKIP_ICACHE_FLUSH);
        break;
      case HeapObjectRequest::kCodeStub:
        request.code_stub()->set_isolate(isolate);
        SixByteInstr instr =
            Instruction::InstructionBits(reinterpret_cast<const byte*>(pc));
        int index = instr & 0xFFFFFFFF;
        code_targets_[index] = request.code_stub()->GetCode();
        break;
    }
  }
}

352 353 354
// -----------------------------------------------------------------------------
// Specific instructions, constants, and masks.

355
Assembler::Assembler(IsolateData isolate_data, void* buffer, int buffer_size)
356
    : AssemblerBase(isolate_data, buffer, buffer_size) {
357
  reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
358
  code_targets_.reserve(100);
359 360 361 362 363

  last_bound_pos_ = 0;
  relocations_.reserve(128);
}

364
void Assembler::GetCode(Isolate* isolate, CodeDesc* desc) {
365 366
  EmitRelocations();

367 368
  AllocateAndInstallRequestedHeapObjects(isolate);

369 370 371 372 373 374
  // Set up code descriptor.
  desc->buffer = buffer_;
  desc->buffer_size = buffer_size_;
  desc->instr_size = pc_offset();
  desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
  desc->origin = this;
375 376
  desc->unwinding_info_size = 0;
  desc->unwinding_info = nullptr;
377 378 379
}

void Assembler::Align(int m) {
380
  DCHECK(m >= 4 && base::bits::IsPowerOfTwo(m));
381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442
  while ((pc_offset() & (m - 1)) != 0) {
    nop(0);
  }
}

void Assembler::CodeTargetAlign() { Align(8); }

Condition Assembler::GetCondition(Instr instr) {
  switch (instr & kCondMask) {
    case BT:
      return eq;
    case BF:
      return ne;
    default:
      UNIMPLEMENTED();
  }
  return al;
}

#if V8_TARGET_ARCH_S390X
// This code assumes a FIXED_SEQUENCE for 64bit loads (iihf/iilf)
bool Assembler::Is64BitLoadIntoIP(SixByteInstr instr1, SixByteInstr instr2) {
  // Check the instructions are the iihf/iilf load into ip
  return (((instr1 >> 32) == 0xC0C8) && ((instr2 >> 32) == 0xC0C9));
}
#else
// This code assumes a FIXED_SEQUENCE for 32bit loads (iilf)
bool Assembler::Is32BitLoadIntoIP(SixByteInstr instr) {
  // Check the instruction is an iilf load into ip/r12.
  return ((instr >> 32) == 0xC0C9);
}
#endif

// Labels refer to positions in the (to be) generated code.
// There are bound, linked, and unused labels.
//
// Bound labels refer to known positions in the already
// generated code. pos() is the position the label refers to.
//
// Linked labels refer to unknown positions in the code
// to be generated; pos() is the position of the last
// instruction using the label.

// The link chain is terminated by a negative code position (must be aligned)
const int kEndOfChain = -4;

// Returns the target address of the relative instructions, typically
// of the form: pos + imm (where immediate is in # of halfwords for
// BR* and LARL).
int Assembler::target_at(int pos) {
  SixByteInstr instr = instr_at(pos);
  // check which type of branch this is 16 or 26 bit offset
  Opcode opcode = Instruction::S390OpcodeValue(buffer_ + pos);

  if (BRC == opcode || BRCT == opcode || BRCTG == opcode) {
    int16_t imm16 = SIGN_EXT_IMM16((instr & kImm16Mask));
    imm16 <<= 1;  // BRC immediate is in # of halfwords
    if (imm16 == 0) return kEndOfChain;
    return pos + imm16;
  } else if (LLILF == opcode || BRCL == opcode || LARL == opcode ||
             BRASL == opcode) {
    int32_t imm32 =
443
        static_cast<int32_t>(instr & (static_cast<uint64_t>(0xFFFFFFFF)));
444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466
    if (LLILF != opcode)
      imm32 <<= 1;  // BR* + LARL treat immediate in # of halfwords
    if (imm32 == 0) return kEndOfChain;
    return pos + imm32;
  }

  // Unknown condition
  DCHECK(false);
  return -1;
}

// Update the target address of the current relative instruction.
void Assembler::target_at_put(int pos, int target_pos, bool* is_branch) {
  SixByteInstr instr = instr_at(pos);
  Opcode opcode = Instruction::S390OpcodeValue(buffer_ + pos);

  if (is_branch != nullptr) {
    *is_branch = (opcode == BRC || opcode == BRCT || opcode == BRCTG ||
                  opcode == BRCL || opcode == BRASL);
  }

  if (BRC == opcode || BRCT == opcode || BRCTG == opcode) {
    int16_t imm16 = target_pos - pos;
467
    instr &= (~0xFFFF);
468
    DCHECK(is_int16(imm16));
469 470 471 472 473
    instr_at_put<FourByteInstr>(pos, instr | (imm16 >> 1));
    return;
  } else if (BRCL == opcode || LARL == opcode || BRASL == opcode) {
    // Immediate is in # of halfwords
    int32_t imm32 = target_pos - pos;
474
    instr &= (~static_cast<uint64_t>(0xFFFFFFFF));
475 476 477
    instr_at_put<SixByteInstr>(pos, instr | (imm32 >> 1));
    return;
  } else if (LLILF == opcode) {
478
    DCHECK(target_pos == kEndOfChain || target_pos >= 0);
479 480 481
    // Emitted label constant, not part of a branch.
    // Make label relative to Code* of generated Code object.
    int32_t imm32 = target_pos + (Code::kHeaderSize - kHeapObjectTag);
482
    instr &= (~static_cast<uint64_t>(0xFFFFFFFF));
483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538
    instr_at_put<SixByteInstr>(pos, instr | imm32);
    return;
  }
  DCHECK(false);
}

// Returns the maximum number of bits given instruction can address.
int Assembler::max_reach_from(int pos) {
  Opcode opcode = Instruction::S390OpcodeValue(buffer_ + pos);

  // Check which type of instr.  In theory, we can return
  // the values below + 1, given offset is # of halfwords
  if (BRC == opcode || BRCT == opcode || BRCTG == opcode) {
    return 16;
  } else if (LLILF == opcode || BRCL == opcode || LARL == opcode ||
             BRASL == opcode) {
    return 31;  // Using 31 as workaround instead of 32 as
                // is_intn(x,32) doesn't work on 32-bit platforms.
                // llilf: Emitted label constant, not part of
                //        a branch (regexp PushBacktrack).
  }
  DCHECK(false);
  return 16;
}

void Assembler::bind_to(Label* L, int pos) {
  DCHECK(0 <= pos && pos <= pc_offset());  // must have a valid binding position
  bool is_branch = false;
  while (L->is_linked()) {
    int fixup_pos = L->pos();
#ifdef DEBUG
    int32_t offset = pos - fixup_pos;
    int maxReach = max_reach_from(fixup_pos);
#endif
    next(L);  // call next before overwriting link with target at fixup_pos
    DCHECK(is_intn(offset, maxReach));
    target_at_put(fixup_pos, pos, &is_branch);
  }
  L->bind_to(pos);

  // Keep track of the last bound label so we don't eliminate any instructions
  // before a bound label.
  if (pos > last_bound_pos_) last_bound_pos_ = pos;
}

void Assembler::bind(Label* L) {
  DCHECK(!L->is_bound());  // label can only be bound once
  bind_to(L, pc_offset());
}

void Assembler::next(Label* L) {
  DCHECK(L->is_linked());
  int link = target_at(L->pos());
  if (link == kEndOfChain) {
    L->Unuse();
  } else {
539
    DCHECK_GE(link, 0);
540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598
    L->link_to(link);
  }
}

bool Assembler::is_near(Label* L, Condition cond) {
  DCHECK(L->is_bound());
  if (L->is_bound() == false) return false;

  int maxReach = ((cond == al) ? 26 : 16);
  int offset = L->pos() - pc_offset();

  return is_intn(offset, maxReach);
}

int Assembler::link(Label* L) {
  int position;
  if (L->is_bound()) {
    position = L->pos();
  } else {
    if (L->is_linked()) {
      position = L->pos();  // L's link
    } else {
      // was: target_pos = kEndOfChain;
      // However, using self to mark the first reference
      // should avoid most instances of branch offset overflow.  See
      // target_at() for where this is converted back to kEndOfChain.
      position = pc_offset();
    }
    L->link_to(pc_offset());
  }

  return position;
}

void Assembler::load_label_offset(Register r1, Label* L) {
  int target_pos;
  int constant;
  if (L->is_bound()) {
    target_pos = L->pos();
    constant = target_pos + (Code::kHeaderSize - kHeapObjectTag);
  } else {
    if (L->is_linked()) {
      target_pos = L->pos();  // L's link
    } else {
      // was: target_pos = kEndOfChain;
      // However, using branch to self to mark the first reference
      // should avoid most instances of branch offset overflow.  See
      // target_at() for where this is converted back to kEndOfChain.
      target_pos = pc_offset();
    }
    L->link_to(pc_offset());

    constant = target_pos - pc_offset();
  }
  llilf(r1, Operand(constant));
}

// Pseudo op - branch on condition
void Assembler::branchOnCond(Condition c, int branch_offset, bool is_bound) {
599 600
  int offset_in_halfwords = branch_offset / 2;
  if (is_bound && is_int16(offset_in_halfwords)) {
jyan's avatar
jyan committed
601
    brc(c, Operand(offset_in_halfwords));  // short jump
602
  } else {
603
    brcl(c, Operand(offset_in_halfwords));  // long jump
604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668
  }
}

// 32-bit Store Multiple - short displacement (12-bits unsigned)
void Assembler::stm(Register r1, Register r2, const MemOperand& src) {
  rs_form(STM, r1, r2, src.rb(), src.offset());
}

// 32-bit Store Multiple - long displacement (20-bits signed)
void Assembler::stmy(Register r1, Register r2, const MemOperand& src) {
  rsy_form(STMY, r1, r2, src.rb(), src.offset());
}

// 64-bit Store Multiple - long displacement (20-bits signed)
void Assembler::stmg(Register r1, Register r2, const MemOperand& src) {
  rsy_form(STMG, r1, r2, src.rb(), src.offset());
}

// Exception-generating instructions and debugging support.
// Stops with a non-negative code less than kNumOfWatchedStops support
// enabling/disabling and a counter feature. See simulator-s390.h .
void Assembler::stop(const char* msg, Condition cond, int32_t code,
                     CRegister cr) {
  if (cond != al) {
    Label skip;
    b(NegateCondition(cond), &skip, Label::kNear);
    bkpt(0);
    bind(&skip);
  } else {
    bkpt(0);
  }
}

void Assembler::bkpt(uint32_t imm16) {
  // GDB software breakpoint instruction
  emit2bytes(0x0001);
}

// Pseudo instructions.
void Assembler::nop(int type) {
  switch (type) {
    case 0:
      lr(r0, r0);
      break;
    case DEBUG_BREAK_NOP:
      // TODO(john.yan): Use a better NOP break
      oill(r3, Operand::Zero());
      break;
    default:
      UNIMPLEMENTED();
  }
}



// RI1 format: <insn> R1,I2
//    +--------+----+----+------------------+
//    | OpCode | R1 |OpCd|        I2        |
//    +--------+----+----+------------------+
//    0        8    12   16                31
#define RI1_FORM_EMIT(name, op) \
  void Assembler::name(Register r, const Operand& i2) { ri_form(op, r, i2); }

void Assembler::ri_form(Opcode op, Register r1, const Operand& i2) {
  DCHECK(is_uint12(op));
669
  DCHECK(is_uint16(i2.immediate()) || is_int16(i2.immediate()));
670
  emit4bytes((op & 0xFF0) * B20 | r1.code() * B20 | (op & 0xF) * B16 |
671
             (i2.immediate() & 0xFFFF));
672 673 674 675 676 677 678 679 680 681 682 683 684
}

// RI2 format: <insn> M1,I2
//    +--------+----+----+------------------+
//    | OpCode | M1 |OpCd|        I2        |
//    +--------+----+----+------------------+
//    0        8    12   16                31
#define RI2_FORM_EMIT(name, op) \
  void Assembler::name(Condition m, const Operand& i2) { ri_form(op, m, i2); }

void Assembler::ri_form(Opcode op, Condition m1, const Operand& i2) {
  DCHECK(is_uint12(op));
  DCHECK(is_uint4(m1));
685
  DCHECK(op == BRC ? is_int16(i2.immediate()) : is_uint16(i2.immediate()));
686
  emit4bytes((op & 0xFF0) * B20 | m1 * B20 | (op & 0xF) * B16 |
687
             (i2.immediate() & 0xFFFF));
688 689 690 691 692 693 694 695 696 697 698
}

// RIE-f format: <insn> R1,R2,I3,I4,I5
//    +--------+----+----+------------------+--------+--------+
//    | OpCode | R1 | R2 |   I3   |    I4   |   I5   | OpCode |
//    +--------+----+----+------------------+--------+--------+
//    0        8    12   16      24         32       40      47
void Assembler::rie_f_form(Opcode op, Register r1, Register r2,
                           const Operand& i3, const Operand& i4,
                           const Operand& i5) {
  DCHECK(is_uint16(op));
699 700 701
  DCHECK(is_uint8(i3.immediate()));
  DCHECK(is_uint8(i4.immediate()));
  DCHECK(is_uint8(i5.immediate()));
702 703 704
  uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
                  (static_cast<uint64_t>(r1.code())) * B36 |
                  (static_cast<uint64_t>(r2.code())) * B32 |
705 706 707
                  (static_cast<uint64_t>(i3.immediate())) * B24 |
                  (static_cast<uint64_t>(i4.immediate())) * B16 |
                  (static_cast<uint64_t>(i5.immediate())) * B8 |
708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724
                  (static_cast<uint64_t>(op & 0x00FF));
  emit6bytes(code);
}

// RIE format: <insn> R1,R3,I2
//    +--------+----+----+------------------+--------+--------+
//    | OpCode | R1 | R3 |        I2        |////////| OpCode |
//    +--------+----+----+------------------+--------+--------+
//    0        8    12   16                 32       40      47
#define RIE_FORM_EMIT(name, op)                                       \
  void Assembler::name(Register r1, Register r3, const Operand& i2) { \
    rie_form(op, r1, r3, i2);                                         \
  }

void Assembler::rie_form(Opcode op, Register r1, Register r3,
                         const Operand& i2) {
  DCHECK(is_uint16(op));
725
  DCHECK(is_int16(i2.immediate()));
726 727 728
  uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
                  (static_cast<uint64_t>(r1.code())) * B36 |
                  (static_cast<uint64_t>(r3.code())) * B32 |
729
                  (static_cast<uint64_t>(i2.immediate() & 0xFFFF)) * B16 |
730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785
                  (static_cast<uint64_t>(op & 0x00FF));
  emit6bytes(code);
}

// RS1 format: <insn> R1,R3,D2(B2)
//    +--------+----+----+----+-------------+
//    | OpCode | R1 | R3 | B2 |     D2      |
//    +--------+----+----+----+-------------+
//    0        8    12   16   20           31
#define RS1_FORM_EMIT(name, op)                                            \
  void Assembler::name(Register r1, Register r3, Register b2, Disp d2) {   \
    rs_form(op, r1, r3, b2, d2);                                           \
  }                                                                        \
  void Assembler::name(Register r1, Register r3, const MemOperand& opnd) { \
    name(r1, r3, opnd.getBaseRegister(), opnd.getDisplacement());          \
  }

void Assembler::rs_form(Opcode op, Register r1, Register r3, Register b2,
                        const Disp d2) {
  DCHECK(is_uint12(d2));
  emit4bytes(op * B24 | r1.code() * B20 | r3.code() * B16 | b2.code() * B12 |
             d2);
}

// RS2 format: <insn> R1,M3,D2(B2)
//    +--------+----+----+----+-------------+
//    | OpCode | R1 | M3 | B2 |     D2      |
//    +--------+----+----+----+-------------+
//    0        8    12   16   20           31
#define RS2_FORM_EMIT(name, op)                                             \
  void Assembler::name(Register r1, Condition m3, Register b2, Disp d2) {   \
    rs_form(op, r1, m3, b2, d2);                                            \
  }                                                                         \
  void Assembler::name(Register r1, Condition m3, const MemOperand& opnd) { \
    name(r1, m3, opnd.getBaseRegister(), opnd.getDisplacement());           \
  }

void Assembler::rs_form(Opcode op, Register r1, Condition m3, Register b2,
                        const Disp d2) {
  DCHECK(is_uint12(d2));
  emit4bytes(op * B24 | r1.code() * B20 | m3 * B16 | b2.code() * B12 | d2);
}

// RSI format: <insn> R1,R3,I2
//    +--------+----+----+------------------+
//    | OpCode | R1 | R3 |        RI2       |
//    +--------+----+----+------------------+
//    0        8    12   16                 31
#define RSI_FORM_EMIT(name, op)                                       \
  void Assembler::name(Register r1, Register r3, const Operand& i2) { \
    rsi_form(op, r1, r3, i2);                                         \
  }

void Assembler::rsi_form(Opcode op, Register r1, Register r3,
                         const Operand& i2) {
  DCHECK(is_uint8(op));
786 787 788
  DCHECK(is_uint16(i2.immediate()));
  emit4bytes(op * B24 | r1.code() * B20 | r3.code() * B16 |
             (i2.immediate() & 0xFFFF));
789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939
}

// RSL format: <insn> R1,R3,D2(B2)
//    +--------+----+----+----+-------------+--------+--------+
//    | OpCode | L1 |    | B2 |    D2       |        | OpCode |
//    +--------+----+----+----+-------------+--------+--------+
//    0        8    12   16   20            32       40      47
#define RSL_FORM_EMIT(name, op)                           \
  void Assembler::name(Length l1, Register b2, Disp d2) { \
    rsl_form(op, l1, b2, d2);                             \
  }

void Assembler::rsl_form(Opcode op, Length l1, Register b2, Disp d2) {
  DCHECK(is_uint16(op));
  uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
                  (static_cast<uint64_t>(l1)) * B36 |
                  (static_cast<uint64_t>(b2.code())) * B28 |
                  (static_cast<uint64_t>(d2)) * B16 |
                  (static_cast<uint64_t>(op & 0x00FF));
  emit6bytes(code);
}

// RSY1 format: <insn> R1,R3,D2(B2)
//    +--------+----+----+----+-------------+--------+--------+
//    | OpCode | R1 | R3 | B2 |    DL2      |  DH2   | OpCode |
//    +--------+----+----+----+-------------+--------+--------+
//    0        8    12   16   20            32       40      47
#define RSY1_FORM_EMIT(name, op)                                           \
  void Assembler::name(Register r1, Register r3, Register b2, Disp d2) {   \
    rsy_form(op, r1, r3, b2, d2);                                          \
  }                                                                        \
  void Assembler::name(Register r1, Register r3, const MemOperand& opnd) { \
    name(r1, r3, opnd.getBaseRegister(), opnd.getDisplacement());          \
  }

void Assembler::rsy_form(Opcode op, Register r1, Register r3, Register b2,
                         const Disp d2) {
  DCHECK(is_int20(d2));
  DCHECK(is_uint16(op));
  uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
                  (static_cast<uint64_t>(r1.code())) * B36 |
                  (static_cast<uint64_t>(r3.code())) * B32 |
                  (static_cast<uint64_t>(b2.code())) * B28 |
                  (static_cast<uint64_t>(d2 & 0x0FFF)) * B16 |
                  (static_cast<uint64_t>(d2 & 0x0FF000)) >> 4 |
                  (static_cast<uint64_t>(op & 0x00FF));
  emit6bytes(code);
}

// RSY2 format: <insn> R1,M3,D2(B2)
//    +--------+----+----+----+-------------+--------+--------+
//    | OpCode | R1 | M3 | B2 |    DL2      |  DH2   | OpCode |
//    +--------+----+----+----+-------------+--------+--------+
//    0        8    12   16   20            32       40      47
#define RSY2_FORM_EMIT(name, op)                                            \
  void Assembler::name(Register r1, Condition m3, Register b2, Disp d2) {   \
    rsy_form(op, r1, m3, b2, d2);                                           \
  }                                                                         \
  void Assembler::name(Register r1, Condition m3, const MemOperand& opnd) { \
    name(r1, m3, opnd.getBaseRegister(), opnd.getDisplacement());           \
  }

void Assembler::rsy_form(Opcode op, Register r1, Condition m3, Register b2,
                         const Disp d2) {
  DCHECK(is_int20(d2));
  DCHECK(is_uint16(op));
  uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
                  (static_cast<uint64_t>(r1.code())) * B36 |
                  (static_cast<uint64_t>(m3)) * B32 |
                  (static_cast<uint64_t>(b2.code())) * B28 |
                  (static_cast<uint64_t>(d2 & 0x0FFF)) * B16 |
                  (static_cast<uint64_t>(d2 & 0x0FF000)) >> 4 |
                  (static_cast<uint64_t>(op & 0x00FF));
  emit6bytes(code);
}

// RXE format: <insn> R1,D2(X2,B2)
//    +--------+----+----+----+-------------+--------+--------+
//    | OpCode | R1 | X2 | B2 |     D2      |////////| OpCode |
//    +--------+----+----+----+-------------+--------+--------+
//    0        8    12   16   20            32       40      47
#define RXE_FORM_EMIT(name, op)                                          \
  void Assembler::name(Register r1, Register x2, Register b2, Disp d2) { \
    rxe_form(op, r1, x2, b2, d2);                                        \
  }                                                                      \
  void Assembler::name(Register r1, const MemOperand& opnd) {            \
    name(r1, opnd.getIndexRegister(), opnd.getBaseRegister(),            \
         opnd.getDisplacement());                                        \
  }

void Assembler::rxe_form(Opcode op, Register r1, Register x2, Register b2,
                         Disp d2) {
  DCHECK(is_uint12(d2));
  DCHECK(is_uint16(op));
  uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
                  (static_cast<uint64_t>(r1.code())) * B36 |
                  (static_cast<uint64_t>(x2.code())) * B32 |
                  (static_cast<uint64_t>(b2.code())) * B28 |
                  (static_cast<uint64_t>(d2 & 0x0FFF)) * B16 |
                  (static_cast<uint64_t>(op & 0x00FF));
  emit6bytes(code);
}

// RRS format: <insn> R1,R2,M3,D4(B4)
//    +--------+----+----+----+-------------+----+---+--------+
//    | OpCode | R1 | R2 | B4 |     D4      | M3 |///| OpCode |
//    +--------+----+----+----+-------------+----+---+--------+
//    0        8    12   16   20            32   36   40      47
#define RRS_FORM_EMIT(name, op)                                        \
  void Assembler::name(Register r1, Register r2, Register b4, Disp d4, \
                       Condition m3) {                                 \
    rrs_form(op, r1, r2, b4, d4, m3);                                  \
  }                                                                    \
  void Assembler::name(Register r1, Register r2, Condition m3,         \
                       const MemOperand& opnd) {                       \
    name(r1, r2, opnd.getBaseRegister(), opnd.getDisplacement(), m3);  \
  }

void Assembler::rrs_form(Opcode op, Register r1, Register r2, Register b4,
                         Disp d4, Condition m3) {
  DCHECK(is_uint12(d4));
  DCHECK(is_uint16(op));
  uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
                  (static_cast<uint64_t>(r1.code())) * B36 |
                  (static_cast<uint64_t>(r2.code())) * B32 |
                  (static_cast<uint64_t>(b4.code())) * B28 |
                  (static_cast<uint64_t>(d4)) * B16 |
                  (static_cast<uint64_t>(m3)) << 12 |
                  (static_cast<uint64_t>(op & 0x00FF));
  emit6bytes(code);
}

// RIS format: <insn> R1,I2,M3,D4(B4)
//    +--------+----+----+----+-------------+--------+--------+
//    | OpCode | R1 | M3 | B4 |     D4      |   I2   | OpCode |
//    +--------+----+----+----+-------------+--------+--------+
//    0        8    12   16   20            32        40      47
#define RIS_FORM_EMIT(name, op)                                         \
  void Assembler::name(Register r1, Condition m3, Register b4, Disp d4, \
                       const Operand& i2) {                             \
    ris_form(op, r1, m3, b4, d4, i2);                                   \
  }                                                                     \
  void Assembler::name(Register r1, const Operand& i2, Condition m3,    \
                       const MemOperand& opnd) {                        \
    name(r1, m3, opnd.getBaseRegister(), opnd.getDisplacement(), i2);   \
  }

void Assembler::ris_form(Opcode op, Register r1, Condition m3, Register b4,
                         Disp d4, const Operand& i2) {
  DCHECK(is_uint12(d4));
  DCHECK(is_uint16(op));
940
  DCHECK(is_uint8(i2.immediate()));
941 942 943 944 945
  uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
                  (static_cast<uint64_t>(r1.code())) * B36 |
                  (static_cast<uint64_t>(m3)) * B32 |
                  (static_cast<uint64_t>(b4.code())) * B28 |
                  (static_cast<uint64_t>(d4)) * B16 |
946
                  (static_cast<uint64_t>(i2.immediate())) << 8 |
947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980
                  (static_cast<uint64_t>(op & 0x00FF));
  emit6bytes(code);
}

// S format: <insn> D2(B2)
//    +------------------+----+-------------+
//    |      OpCode      | B2 |     D2      |
//    +------------------+----+-------------+
//    0                  16   20           31
#define S_FORM_EMIT(name, op)                                        \
  void Assembler::name(Register b1, Disp d2) { s_form(op, b1, d2); } \
  void Assembler::name(const MemOperand& opnd) {                     \
    name(opnd.getBaseRegister(), opnd.getDisplacement());            \
  }

void Assembler::s_form(Opcode op, Register b1, Disp d2) {
  DCHECK(is_uint12(d2));
  emit4bytes(op << 16 | b1.code() * B12 | d2);
}

// SI format: <insn> D1(B1),I2
//    +--------+---------+----+-------------+
//    | OpCode |   I2    | B1 |     D1      |
//    +--------+---------+----+-------------+
//    0        8         16   20           31
#define SI_FORM_EMIT(name, op)                                      \
  void Assembler::name(const Operand& i2, Register b1, Disp d1) {   \
    si_form(op, i2, b1, d1);                                        \
  }                                                                 \
  void Assembler::name(const MemOperand& opnd, const Operand& i2) { \
    name(i2, opnd.getBaseRegister(), opnd.getDisplacement());       \
  }

void Assembler::si_form(Opcode op, const Operand& i2, Register b1, Disp d1) {
981
  emit4bytes((op & 0x00FF) << 24 | i2.immediate() * B16 | b1.code() * B12 | d1);
982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997
}

// SIY format: <insn> D1(B1),I2
//    +--------+---------+----+-------------+--------+--------+
//    | OpCode |   I2    | B1 |     DL1     |  DH1   | OpCode |
//    +--------+---------+----+-------------+--------+--------+
//    0        8         16   20            32   36   40      47
#define SIY_FORM_EMIT(name, op)                                     \
  void Assembler::name(const Operand& i2, Register b1, Disp d1) {   \
    siy_form(op, i2, b1, d1);                                       \
  }                                                                 \
  void Assembler::name(const MemOperand& opnd, const Operand& i2) { \
    name(i2, opnd.getBaseRegister(), opnd.getDisplacement());       \
  }

void Assembler::siy_form(Opcode op, const Operand& i2, Register b1, Disp d1) {
998
  DCHECK(is_uint20(d1) || is_int20(d1));
999
  DCHECK(is_uint16(op));
1000
  DCHECK(is_uint8(i2.immediate()));
1001
  uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
1002
                  (static_cast<uint64_t>(i2.immediate())) * B32 |
1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025
                  (static_cast<uint64_t>(b1.code())) * B28 |
                  (static_cast<uint64_t>(d1 & 0x0FFF)) * B16 |
                  (static_cast<uint64_t>(d1 & 0x0FF000)) >> 4 |
                  (static_cast<uint64_t>(op & 0x00FF));
  emit6bytes(code);
}

// SIL format: <insn> D1(B1),I2
//    +------------------+----+-------------+-----------------+
//    |     OpCode       | B1 |      D1     |        I2       |
//    +------------------+----+-------------+-----------------+
//    0                 16   20            32                47
#define SIL_FORM_EMIT(name, op)                                     \
  void Assembler::name(Register b1, Disp d1, const Operand& i2) {   \
    sil_form(op, b1, d1, i2);                                       \
  }                                                                 \
  void Assembler::name(const MemOperand& opnd, const Operand& i2) { \
    name(opnd.getBaseRegister(), opnd.getDisplacement(), i2);       \
  }

void Assembler::sil_form(Opcode op, Register b1, Disp d1, const Operand& i2) {
  DCHECK(is_uint12(d1));
  DCHECK(is_uint16(op));
1026
  DCHECK(is_uint16(i2.immediate()));
1027 1028 1029
  uint64_t code = (static_cast<uint64_t>(op)) * B32 |
                  (static_cast<uint64_t>(b1.code())) * B28 |
                  (static_cast<uint64_t>(d1)) * B16 |
1030
                  (static_cast<uint64_t>(i2.immediate()));
1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143
  emit6bytes(code);
}

// RXF format: <insn> R1,R3,D2(X2,B2)
//    +--------+----+----+----+-------------+----+---+--------+
//    | OpCode | R3 | X2 | B2 |     D2      | R1 |///| OpCode |
//    +--------+----+----+----+-------------+----+---+--------+
//    0        8    12   16   20            32   36  40      47
#define RXF_FORM_EMIT(name, op)                                            \
  void Assembler::name(Register r1, Register r3, Register b2, Register x2, \
                       Disp d2) {                                          \
    rxf_form(op, r1, r3, b2, x2, d2);                                      \
  }                                                                        \
  void Assembler::name(Register r1, Register r3, const MemOperand& opnd) { \
    name(r1, r3, opnd.getBaseRegister(), opnd.getIndexRegister(),          \
         opnd.getDisplacement());                                          \
  }

void Assembler::rxf_form(Opcode op, Register r1, Register r3, Register b2,
                         Register x2, Disp d2) {
  DCHECK(is_uint12(d2));
  DCHECK(is_uint16(op));
  uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
                  (static_cast<uint64_t>(r3.code())) * B36 |
                  (static_cast<uint64_t>(x2.code())) * B32 |
                  (static_cast<uint64_t>(b2.code())) * B28 |
                  (static_cast<uint64_t>(d2)) * B16 |
                  (static_cast<uint64_t>(r1.code())) * B12 |
                  (static_cast<uint64_t>(op & 0x00FF));
  emit6bytes(code);
}

// SS1 format: <insn> D1(L,B1),D2(B3)
//    +--------+----+----+----+-------------+----+------------+
//    | OpCode |    L    | B1 |     D1      | B2 |     D2     |
//    +--------+----+----+----+-------------+----+------------+
//    0        8    12   16   20            32   36          47
#define SS1_FORM_EMIT(name, op)                                                \
  void Assembler::name(Register b1, Disp d1, Register b2, Disp d2, Length l) { \
    ss_form(op, l, b1, d1, b2, d2);                                            \
  }                                                                            \
  void Assembler::name(const MemOperand& opnd1, const MemOperand& opnd2,       \
                       Length length) {                                        \
    name(opnd1.getBaseRegister(), opnd1.getDisplacement(),                     \
         opnd2.getBaseRegister(), opnd2.getDisplacement(), length);            \
  }

void Assembler::ss_form(Opcode op, Length l, Register b1, Disp d1, Register b2,
                        Disp d2) {
  DCHECK(is_uint12(d2));
  DCHECK(is_uint12(d1));
  DCHECK(is_uint8(op));
  DCHECK(is_uint8(l));
  uint64_t code =
      (static_cast<uint64_t>(op)) * B40 | (static_cast<uint64_t>(l)) * B32 |
      (static_cast<uint64_t>(b1.code())) * B28 |
      (static_cast<uint64_t>(d1)) * B16 |
      (static_cast<uint64_t>(b2.code())) * B12 | (static_cast<uint64_t>(d2));
  emit6bytes(code);
}

// SS2 format: <insn> D1(L1,B1), D2(L3,B3)
//    +--------+----+----+----+-------------+----+------------+
//    | OpCode | L1 | L2 | B1 |     D1      | B2 |     D2     |
//    +--------+----+----+----+-------------+----+------------+
//    0        8    12   16   20            32   36          47
#define SS2_FORM_EMIT(name, op)                                               \
  void Assembler::name(Register b1, Disp d1, Register b2, Disp d2, Length l1, \
                       Length l2) {                                           \
    ss_form(op, l1, l2, b1, d1, b2, d2);                                      \
  }                                                                           \
  void Assembler::name(const MemOperand& opnd1, const MemOperand& opnd2,      \
                       Length length1, Length length2) {                      \
    name(opnd1.getBaseRegister(), opnd1.getDisplacement(),                    \
         opnd2.getBaseRegister(), opnd2.getDisplacement(), length1, length2); \
  }

void Assembler::ss_form(Opcode op, Length l1, Length l2, Register b1, Disp d1,
                        Register b2, Disp d2) {
  DCHECK(is_uint12(d2));
  DCHECK(is_uint12(d1));
  DCHECK(is_uint8(op));
  DCHECK(is_uint4(l2));
  DCHECK(is_uint4(l1));
  uint64_t code =
      (static_cast<uint64_t>(op)) * B40 | (static_cast<uint64_t>(l1)) * B36 |
      (static_cast<uint64_t>(l2)) * B32 |
      (static_cast<uint64_t>(b1.code())) * B28 |
      (static_cast<uint64_t>(d1)) * B16 |
      (static_cast<uint64_t>(b2.code())) * B12 | (static_cast<uint64_t>(d2));
  emit6bytes(code);
}

// SS3 format: <insn> D1(L1,B1), D2(I3,B2)
//    +--------+----+----+----+-------------+----+------------+
//    | OpCode | L1 | I3 | B1 |     D1      | B2 |     D2     |
//    +--------+----+----+----+-------------+----+------------+
//    0        8    12   16   20            32   36          47
#define SS3_FORM_EMIT(name, op)                                              \
  void Assembler::name(const Operand& i3, Register b1, Disp d1, Register b2, \
                       Disp d2, Length l1) {                                 \
    ss_form(op, l1, i3, b1, d1, b2, d2);                                     \
  }                                                                          \
  void Assembler::name(const MemOperand& opnd1, const MemOperand& opnd2,     \
                       Length length) {                                      \
    DCHECK(false);                                                           \
  }
void Assembler::ss_form(Opcode op, Length l1, const Operand& i3, Register b1,
                        Disp d1, Register b2, Disp d2) {
  DCHECK(is_uint12(d2));
  DCHECK(is_uint12(d1));
  DCHECK(is_uint8(op));
  DCHECK(is_uint4(l1));
1144
  DCHECK(is_uint4(i3.immediate()));
1145 1146
  uint64_t code =
      (static_cast<uint64_t>(op)) * B40 | (static_cast<uint64_t>(l1)) * B36 |
1147
      (static_cast<uint64_t>(i3.immediate())) * B32 |
1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341
      (static_cast<uint64_t>(b1.code())) * B28 |
      (static_cast<uint64_t>(d1)) * B16 |
      (static_cast<uint64_t>(b2.code())) * B12 | (static_cast<uint64_t>(d2));
  emit6bytes(code);
}

// SS4 format: <insn> D1(R1,B1), D2(R3,B2)
//    +--------+----+----+----+-------------+----+------------+
//    | OpCode | R1 | R3 | B1 |     D1      | B2 |     D2     |
//    +--------+----+----+----+-------------+----+------------+
//    0        8    12   16   20            32   36          47
#define SS4_FORM_EMIT(name, op)                                            \
  void Assembler::name(Register r1, Register r3, Register b1, Disp d1,     \
                       Register b2, Disp d2) {                             \
    ss_form(op, r1, r3, b1, d1, b2, d2);                                   \
  }                                                                        \
  void Assembler::name(const MemOperand& opnd1, const MemOperand& opnd2) { \
    DCHECK(false);                                                         \
  }
void Assembler::ss_form(Opcode op, Register r1, Register r3, Register b1,
                        Disp d1, Register b2, Disp d2) {
  DCHECK(is_uint12(d2));
  DCHECK(is_uint12(d1));
  DCHECK(is_uint8(op));
  uint64_t code = (static_cast<uint64_t>(op)) * B40 |
                  (static_cast<uint64_t>(r1.code())) * B36 |
                  (static_cast<uint64_t>(r3.code())) * B32 |
                  (static_cast<uint64_t>(b1.code())) * B28 |
                  (static_cast<uint64_t>(d1)) * B16 |
                  (static_cast<uint64_t>(b2.code())) * B12 |
                  (static_cast<uint64_t>(d2));
  emit6bytes(code);
}

// SS5 format: <insn> D1(R1,B1), D2(R3,B2)
//    +--------+----+----+----+-------------+----+------------+
//    | OpCode | R1 | R3 | B2 |     D2      | B4 |     D4     |
//    +--------+----+----+----+-------------+----+------------+
//    0        8    12   16   20            32   36          47
#define SS5_FORM_EMIT(name, op)                                            \
  void Assembler::name(Register r1, Register r3, Register b2, Disp d2,     \
                       Register b4, Disp d4) {                             \
    ss_form(op, r1, r3, b2, d2, b4, d4); /*SS5 use the same form as SS4*/  \
  }                                                                        \
  void Assembler::name(const MemOperand& opnd1, const MemOperand& opnd2) { \
    DCHECK(false);                                                         \
  }

#define SS6_FORM_EMIT(name, op) SS1_FORM_EMIT(name, op)

// SSE format: <insn> D1(B1),D2(B2)
//    +------------------+----+-------------+----+------------+
//    |      OpCode      | B1 |     D1      | B2 |     D2     |
//    +------------------+----+-------------+----+------------+
//    0        8    12   16   20            32   36           47
#define SSE_FORM_EMIT(name, op)                                            \
  void Assembler::name(Register b1, Disp d1, Register b2, Disp d2) {       \
    sse_form(op, b1, d1, b2, d2);                                          \
  }                                                                        \
  void Assembler::name(const MemOperand& opnd1, const MemOperand& opnd2) { \
    name(opnd1.getBaseRegister(), opnd1.getDisplacement(),                 \
         opnd2.getBaseRegister(), opnd2.getDisplacement());                \
  }
void Assembler::sse_form(Opcode op, Register b1, Disp d1, Register b2,
                         Disp d2) {
  DCHECK(is_uint12(d2));
  DCHECK(is_uint12(d1));
  DCHECK(is_uint16(op));
  uint64_t code = (static_cast<uint64_t>(op)) * B32 |
                  (static_cast<uint64_t>(b1.code())) * B28 |
                  (static_cast<uint64_t>(d1)) * B16 |
                  (static_cast<uint64_t>(b2.code())) * B12 |
                  (static_cast<uint64_t>(d2));
  emit6bytes(code);
}

// SSF format: <insn> R3, D1(B1),D2(B2),R3
//    +--------+----+----+----+-------------+----+------------+
//    | OpCode | R3 |OpCd| B1 |     D1      | B2 |     D2     |
//    +--------+----+----+----+-------------+----+------------+
//    0        8    12   16   20            32   36           47
#define SSF_FORM_EMIT(name, op)                                        \
  void Assembler::name(Register r3, Register b1, Disp d1, Register b2, \
                       Disp d2) {                                      \
    ssf_form(op, r3, b1, d1, b2, d2);                                  \
  }                                                                    \
  void Assembler::name(Register r3, const MemOperand& opnd1,           \
                       const MemOperand& opnd2) {                      \
    name(r3, opnd1.getBaseRegister(), opnd1.getDisplacement(),         \
         opnd2.getBaseRegister(), opnd2.getDisplacement());            \
  }

void Assembler::ssf_form(Opcode op, Register r3, Register b1, Disp d1,
                         Register b2, Disp d2) {
  DCHECK(is_uint12(d2));
  DCHECK(is_uint12(d1));
  DCHECK(is_uint12(op));
  uint64_t code = (static_cast<uint64_t>(op & 0xFF0)) * B36 |
                  (static_cast<uint64_t>(r3.code())) * B36 |
                  (static_cast<uint64_t>(op & 0x00F)) * B32 |
                  (static_cast<uint64_t>(b1.code())) * B28 |
                  (static_cast<uint64_t>(d1)) * B16 |
                  (static_cast<uint64_t>(b2.code())) * B12 |
                  (static_cast<uint64_t>(d2));
  emit6bytes(code);
}

//  RRF1 format: <insn> R1,R2,R3
//    +------------------+----+----+----+----+
//    |      OpCode      | R3 |    | R1 | R2 |
//    +------------------+----+----+----+----+
//    0                  16   20   24   28  31
#define RRF1_FORM_EMIT(name, op)                                        \
  void Assembler::name(Register r1, Register r2, Register r3) {         \
    rrf1_form(op << 16 | r3.code() * B12 | r1.code() * B4 | r2.code()); \
  }

void Assembler::rrf1_form(Opcode op, Register r1, Register r2, Register r3) {
  uint32_t code = op << 16 | r3.code() * B12 | r1.code() * B4 | r2.code();
  emit4bytes(code);
}

void Assembler::rrf1_form(uint32_t code) { emit4bytes(code); }

//  RRF2 format: <insn> R1,R2,M3
//    +------------------+----+----+----+----+
//    |      OpCode      | M3 |    | R1 | R2 |
//    +------------------+----+----+----+----+
//    0                  16   20   24   28  31
#define RRF2_FORM_EMIT(name, op)                                 \
  void Assembler::name(Condition m3, Register r1, Register r2) { \
    rrf2_form(op << 16 | m3 * B12 | r1.code() * B4 | r2.code()); \
  }

void Assembler::rrf2_form(uint32_t code) { emit4bytes(code); }

//  RRF3 format: <insn> R1,R2,R3,M4
//    +------------------+----+----+----+----+
//    |      OpCode      | R3 | M4 | R1 | R2 |
//    +------------------+----+----+----+----+
//    0                  16   20   24   28  31
#define RRF3_FORM_EMIT(name, op)                                             \
  void Assembler::name(Register r3, Conition m4, Register r1, Register r2) { \
    rrf3_form(op << 16 | r3.code() * B12 | m4 * B8 | r1.code() * B4 |        \
              r2.code());                                                    \
  }

void Assembler::rrf3_form(uint32_t code) { emit4bytes(code); }

//  RRF-e format: <insn> R1,M3,R2,M4
//    +------------------+----+----+----+----+
//    |      OpCode      | M3 | M4 | R1 | R2 |
//    +------------------+----+----+----+----+
//    0                  16   20   24   28  31
void Assembler::rrfe_form(Opcode op, Condition m3, Condition m4, Register r1,
                          Register r2) {
  uint32_t code = op << 16 | m3 * B12 | m4 * B8 | r1.code() * B4 | r2.code();
  emit4bytes(code);
}

// end of S390 Instruction generation

// start of S390 instruction
SS1_FORM_EMIT(ed, ED)
SS1_FORM_EMIT(mvn, MVN)
SS1_FORM_EMIT(nc, NC)
SI_FORM_EMIT(ni, NI)
RI1_FORM_EMIT(nilh, NILH)
RI1_FORM_EMIT(nill, NILL)
RI1_FORM_EMIT(oill, OILL)
RI1_FORM_EMIT(tmll, TMLL)
SS1_FORM_EMIT(tr, TR)
S_FORM_EMIT(ts, TS)

// -------------------------
// Load Address Instructions
// -------------------------
// Load Address Relative Long
void Assembler::larl(Register r1, Label* l) {
  larl(r1, Operand(branch_offset(l)));
}

// -----------------
// Load Instructions
// -----------------
// Load Halfword Immediate (32)
void Assembler::lhi(Register r, const Operand& imm) { ri_form(LHI, r, imm); }

// Load Halfword Immediate (64)
void Assembler::lghi(Register r, const Operand& imm) { ri_form(LGHI, r, imm); }

// -------------------------
// Load Logical Instructions
// -------------------------
1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353
// Load On Condition R-R (32)
void Assembler::locr(Condition m3, Register r1, Register r2) {
  rrf2_form(LOCR << 16 | m3 * B12 | r1.code() * B4 | r2.code());
}

// Load On Condition R-R (64)
void Assembler::locgr(Condition m3, Register r1, Register r2) {
  rrf2_form(LOCGR << 16 | m3 * B12 | r1.code() * B4 | r2.code());
}

// Load On Condition R-M (32)
void Assembler::loc(Condition m3, Register r1, const MemOperand& src) {
1354
  rsy_form(LOC, r1, m3, src.rb(), src.offset());
1355 1356 1357 1358
}

// Load On Condition R-M (64)
void Assembler::locg(Condition m3, Register r1, const MemOperand& src) {
1359
  rsy_form(LOCG, r1, m3, src.rb(), src.offset());
1360 1361
}

1362 1363 1364 1365 1366 1367 1368 1369 1370 1371
// -------------------
// Branch Instructions
// -------------------
// Branch on Count (64)
// Branch Relative and Save (32)
void Assembler::bras(Register r, const Operand& opnd) {
  ri_form(BRAS, r, opnd);
}

// Branch relative on Condition (32)
1372
void Assembler::brc(Condition c, const Operand& opnd) { ri_form(BRC, c, opnd); }
1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444

// Branch On Count (32)
void Assembler::brct(Register r1, const Operand& imm) {
  // BRCT encodes # of halfwords, so divide by 2.
  int16_t numHalfwords = static_cast<int16_t>(imm.immediate()) / 2;
  Operand halfwordOp = Operand(numHalfwords);
  halfwordOp.setBits(16);
  ri_form(BRCT, r1, halfwordOp);
}

// Branch On Count (32)
void Assembler::brctg(Register r1, const Operand& imm) {
  // BRCTG encodes # of halfwords, so divide by 2.
  int16_t numHalfwords = static_cast<int16_t>(imm.immediate()) / 2;
  Operand halfwordOp = Operand(numHalfwords);
  halfwordOp.setBits(16);
  ri_form(BRCTG, r1, halfwordOp);
}

// --------------------
// Compare Instructions
// --------------------
// Compare Halfword Immediate (32)
void Assembler::chi(Register r, const Operand& opnd) { ri_form(CHI, r, opnd); }

// Compare Halfword Immediate (64)
void Assembler::cghi(Register r, const Operand& opnd) {
  ri_form(CGHI, r, opnd);
}

// ----------------------------
// Compare Logical Instructions
// ----------------------------
// Compare Immediate (Mem - Imm) (8)
void Assembler::cli(const MemOperand& opnd, const Operand& imm) {
  si_form(CLI, imm, opnd.rb(), opnd.offset());
}

// Compare Immediate (Mem - Imm) (8)
void Assembler::cliy(const MemOperand& opnd, const Operand& imm) {
  siy_form(CLIY, imm, opnd.rb(), opnd.offset());
}

// Compare logical - mem to mem operation
void Assembler::clc(const MemOperand& opnd1, const MemOperand& opnd2,
                    Length length) {
  ss_form(CLC, length - 1, opnd1.getBaseRegister(), opnd1.getDisplacement(),
          opnd2.getBaseRegister(), opnd2.getDisplacement());
}

// ----------------------------
// Test Under Mask Instructions
// ----------------------------
// Test Under Mask (Mem - Imm) (8)
void Assembler::tm(const MemOperand& opnd, const Operand& imm) {
  si_form(TM, imm, opnd.rb(), opnd.offset());
}

// Test Under Mask (Mem - Imm) (8)
void Assembler::tmy(const MemOperand& opnd, const Operand& imm) {
  siy_form(TMY, imm, opnd.rb(), opnd.offset());
}

// -------------------------------
// Rotate and Insert Selected Bits
// -------------------------------
// Rotate-And-Insert-Selected-Bits
void Assembler::risbg(Register dst, Register src, const Operand& startBit,
                      const Operand& endBit, const Operand& shiftAmt,
                      bool zeroBits) {
  // High tag the top bit of I4/EndBit to zero out any unselected bits
  if (zeroBits)
1445
    rie_f_form(RISBG, dst, src, startBit, Operand(endBit.immediate() | 0x80),
1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456
               shiftAmt);
  else
    rie_f_form(RISBG, dst, src, startBit, endBit, shiftAmt);
}

// Rotate-And-Insert-Selected-Bits
void Assembler::risbgn(Register dst, Register src, const Operand& startBit,
                       const Operand& endBit, const Operand& shiftAmt,
                       bool zeroBits) {
  // High tag the top bit of I4/EndBit to zero out any unselected bits
  if (zeroBits)
1457
    rie_f_form(RISBGN, dst, src, startBit, Operand(endBit.immediate() | 0x80),
1458 1459 1460 1461 1462 1463 1464 1465
               shiftAmt);
  else
    rie_f_form(RISBGN, dst, src, startBit, endBit, shiftAmt);
}

// ---------------------------
// Move Character Instructions
// ---------------------------
1466
// Move character - mem to mem operation
1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490
void Assembler::mvc(const MemOperand& opnd1, const MemOperand& opnd2,
                    uint32_t length) {
  ss_form(MVC, length - 1, opnd1.getBaseRegister(), opnd1.getDisplacement(),
          opnd2.getBaseRegister(), opnd2.getDisplacement());
}

// -----------------------
// 32-bit Add Instructions
// -----------------------
// Add Halfword Immediate (32)
void Assembler::ahi(Register r1, const Operand& i2) { ri_form(AHI, r1, i2); }

// Add Halfword Immediate (32)
void Assembler::ahik(Register r1, Register r3, const Operand& i2) {
  rie_form(AHIK, r1, r3, i2);
}

// Add Register-Register-Register (32)
void Assembler::ark(Register r1, Register r2, Register r3) {
  rrf1_form(ARK, r1, r2, r3);
}

// Add Storage-Imm (32)
void Assembler::asi(const MemOperand& opnd, const Operand& imm) {
1491
  DCHECK(is_int8(imm.immediate()));
1492
  DCHECK(is_int20(opnd.offset()));
1493 1494
  siy_form(ASI, Operand(0xFF & imm.immediate()), opnd.rb(),
           0xFFFFF & opnd.offset());
1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514
}

// -----------------------
// 64-bit Add Instructions
// -----------------------
// Add Halfword Immediate (64)
void Assembler::aghi(Register r1, const Operand& i2) { ri_form(AGHI, r1, i2); }

// Add Halfword Immediate (64)
void Assembler::aghik(Register r1, Register r3, const Operand& i2) {
  rie_form(AGHIK, r1, r3, i2);
}

// Add Register-Register-Register (64)
void Assembler::agrk(Register r1, Register r2, Register r3) {
  rrf1_form(AGRK, r1, r2, r3);
}

// Add Storage-Imm (64)
void Assembler::agsi(const MemOperand& opnd, const Operand& imm) {
1515
  DCHECK(is_int8(imm.immediate()));
1516
  DCHECK(is_int20(opnd.offset()));
1517 1518
  siy_form(AGSI, Operand(0xFF & imm.immediate()), opnd.rb(),
           0xFFFFF & opnd.offset());
1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576
}

// -------------------------------
// 32-bit Add Logical Instructions
// -------------------------------
// Add Logical Register-Register-Register (32)
void Assembler::alrk(Register r1, Register r2, Register r3) {
  rrf1_form(ALRK, r1, r2, r3);
}

// -------------------------------
// 64-bit Add Logical Instructions
// -------------------------------
// Add Logical Register-Register-Register (64)
void Assembler::algrk(Register r1, Register r2, Register r3) {
  rrf1_form(ALGRK, r1, r2, r3);
}

// ----------------------------
// 32-bit Subtract Instructions
// ----------------------------
// Subtract Register-Register-Register (32)
void Assembler::srk(Register r1, Register r2, Register r3) {
  rrf1_form(SRK, r1, r2, r3);
}

// ----------------------------
// 64-bit Subtract Instructions
// ----------------------------
// Subtract Register-Register-Register (64)
void Assembler::sgrk(Register r1, Register r2, Register r3) {
  rrf1_form(SGRK, r1, r2, r3);
}

// ------------------------------------
// 32-bit Subtract Logical Instructions
// ------------------------------------
// Subtract Logical Register-Register-Register (32)
void Assembler::slrk(Register r1, Register r2, Register r3) {
  rrf1_form(SLRK, r1, r2, r3);
}

// ------------------------------------
// 64-bit Subtract Logical Instructions
// ------------------------------------
// Subtract Logical Register-Register-Register (64)
void Assembler::slgrk(Register r1, Register r2, Register r3) {
  rrf1_form(SLGRK, r1, r2, r3);
}

// ----------------------------
// 32-bit Multiply Instructions
// ----------------------------
// Multiply Halfword Immediate (32)
void Assembler::mhi(Register r1, const Operand& opnd) {
  ri_form(MHI, r1, opnd);
}

jyan's avatar
jyan committed
1577 1578 1579 1580 1581 1582 1583 1584 1585 1586
// Multiply Single Register (32)
void Assembler::msrkc(Register r1, Register r2, Register r3) {
  rrf1_form(MSRKC, r1, r2, r3);
}

// Multiply Single Register (64)
void Assembler::msgrkc(Register r1, Register r2, Register r3) {
  rrf1_form(MSGRKC, r1, r2, r3);
}

1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642
// ----------------------------
// 64-bit Multiply Instructions
// ----------------------------
// Multiply Halfword Immediate (64)
void Assembler::mghi(Register r1, const Operand& opnd) {
  ri_form(MGHI, r1, opnd);
}

// --------------------
// Bitwise Instructions
// --------------------
// AND Register-Register-Register (32)
void Assembler::nrk(Register r1, Register r2, Register r3) {
  rrf1_form(NRK, r1, r2, r3);
}

// AND Register-Register-Register (64)
void Assembler::ngrk(Register r1, Register r2, Register r3) {
  rrf1_form(NGRK, r1, r2, r3);
}

// OR Register-Register-Register (32)
void Assembler::ork(Register r1, Register r2, Register r3) {
  rrf1_form(ORK, r1, r2, r3);
}

// OR Register-Register-Register (64)
void Assembler::ogrk(Register r1, Register r2, Register r3) {
  rrf1_form(OGRK, r1, r2, r3);
}

// XOR Register-Register-Register (32)
void Assembler::xrk(Register r1, Register r2, Register r3) {
  rrf1_form(XRK, r1, r2, r3);
}

// XOR Register-Register-Register (64)
void Assembler::xgrk(Register r1, Register r2, Register r3) {
  rrf1_form(XGRK, r1, r2, r3);
}

// XOR Storage-Storage
void Assembler::xc(const MemOperand& opnd1, const MemOperand& opnd2,
                   Length length) {
  ss_form(XC, length - 1, opnd1.getBaseRegister(), opnd1.getDisplacement(),
          opnd2.getBaseRegister(), opnd2.getDisplacement());
}

void Assembler::EnsureSpaceFor(int space_needed) {
  if (buffer_space() <= (kGap + space_needed)) {
    GrowBuffer(space_needed);
  }
}

// Rotate Left Single Logical (32)
void Assembler::rll(Register r1, Register r3, Register opnd) {
1643
  DCHECK(opnd != r0);
1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659
  rsy_form(RLL, r1, r3, opnd, 0);
}

// Rotate Left Single Logical (32)
void Assembler::rll(Register r1, Register r3, const Operand& opnd) {
  rsy_form(RLL, r1, r3, r0, opnd.immediate());
}

// Rotate Left Single Logical (32)
void Assembler::rll(Register r1, Register r3, Register r2,
                    const Operand& opnd) {
  rsy_form(RLL, r1, r3, r2, opnd.immediate());
}

// Rotate Left Single Logical (64)
void Assembler::rllg(Register r1, Register r3, Register opnd) {
1660
  DCHECK(opnd != r0);
1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676
  rsy_form(RLLG, r1, r3, opnd, 0);
}

// Rotate Left Single Logical (64)
void Assembler::rllg(Register r1, Register r3, const Operand& opnd) {
  rsy_form(RLLG, r1, r3, r0, opnd.immediate());
}

// Rotate Left Single Logical (64)
void Assembler::rllg(Register r1, Register r3, Register r2,
                     const Operand& opnd) {
  rsy_form(RLLG, r1, r3, r2, opnd.immediate());
}

// Shift Left Single Logical (32)
void Assembler::sll(Register r1, Register opnd) {
1677
  DCHECK(opnd != r0);
1678 1679 1680 1681 1682 1683 1684 1685 1686 1687
  rs_form(SLL, r1, r0, opnd, 0);
}

// Shift Left Single Logical (32)
void Assembler::sll(Register r1, const Operand& opnd) {
  rs_form(SLL, r1, r0, r0, opnd.immediate());
}

// Shift Left Single Logical (32)
void Assembler::sllk(Register r1, Register r3, Register opnd) {
1688
  DCHECK(opnd != r0);
1689 1690 1691 1692 1693 1694 1695 1696 1697 1698
  rsy_form(SLLK, r1, r3, opnd, 0);
}

// Shift Left Single Logical (32)
void Assembler::sllk(Register r1, Register r3, const Operand& opnd) {
  rsy_form(SLLK, r1, r3, r0, opnd.immediate());
}

// Shift Left Single Logical (64)
void Assembler::sllg(Register r1, Register r3, Register opnd) {
1699
  DCHECK(opnd != r0);
1700 1701 1702 1703 1704 1705 1706 1707
  rsy_form(SLLG, r1, r3, opnd, 0);
}

// Shift Left Single Logical (64)
void Assembler::sllg(Register r1, Register r3, const Operand& opnd) {
  rsy_form(SLLG, r1, r3, r0, opnd.immediate());
}

1708 1709
// Shift Left Double Logical (64)
void Assembler::sldl(Register r1, Register b2, const Operand& opnd) {
1710
  DCHECK_EQ(r1.code() % 2, 0);
1711 1712 1713
  rs_form(SLDL, r1, r0, b2, opnd.immediate());
}

1714 1715
// Shift Right Single Logical (32)
void Assembler::srl(Register r1, Register opnd) {
1716
  DCHECK(opnd != r0);
1717 1718 1719
  rs_form(SRL, r1, r0, opnd, 0);
}

1720 1721
// Shift Right Double Arith (64)
void Assembler::srda(Register r1, Register b2, const Operand& opnd) {
1722
  DCHECK_EQ(r1.code() % 2, 0);
1723 1724 1725 1726 1727
  rs_form(SRDA, r1, r0, b2, opnd.immediate());
}

// Shift Right Double Logical (64)
void Assembler::srdl(Register r1, Register b2, const Operand& opnd) {
1728
  DCHECK_EQ(r1.code() % 2, 0);
1729 1730 1731
  rs_form(SRDL, r1, r0, b2, opnd.immediate());
}

1732 1733 1734 1735 1736 1737 1738
// Shift Right Single Logical (32)
void Assembler::srl(Register r1, const Operand& opnd) {
  rs_form(SRL, r1, r0, r0, opnd.immediate());
}

// Shift Right Single Logical (32)
void Assembler::srlk(Register r1, Register r3, Register opnd) {
1739
  DCHECK(opnd != r0);
1740 1741 1742 1743 1744 1745 1746 1747 1748 1749
  rsy_form(SRLK, r1, r3, opnd, 0);
}

// Shift Right Single Logical (32)
void Assembler::srlk(Register r1, Register r3, const Operand& opnd) {
  rsy_form(SRLK, r1, r3, r0, opnd.immediate());
}

// Shift Right Single Logical (64)
void Assembler::srlg(Register r1, Register r3, Register opnd) {
1750
  DCHECK(opnd != r0);
1751 1752 1753 1754 1755 1756 1757 1758 1759 1760
  rsy_form(SRLG, r1, r3, opnd, 0);
}

// Shift Right Single Logical (64)
void Assembler::srlg(Register r1, Register r3, const Operand& opnd) {
  rsy_form(SRLG, r1, r3, r0, opnd.immediate());
}

// Shift Left Single (32)
void Assembler::sla(Register r1, Register opnd) {
1761
  DCHECK(opnd != r0);
1762 1763 1764 1765 1766 1767 1768 1769 1770 1771
  rs_form(SLA, r1, r0, opnd, 0);
}

// Shift Left Single (32)
void Assembler::sla(Register r1, const Operand& opnd) {
  rs_form(SLA, r1, r0, r0, opnd.immediate());
}

// Shift Left Single (32)
void Assembler::slak(Register r1, Register r3, Register opnd) {
1772
  DCHECK(opnd != r0);
1773 1774 1775 1776 1777 1778 1779 1780 1781 1782
  rsy_form(SLAK, r1, r3, opnd, 0);
}

// Shift Left Single (32)
void Assembler::slak(Register r1, Register r3, const Operand& opnd) {
  rsy_form(SLAK, r1, r3, r0, opnd.immediate());
}

// Shift Left Single (64)
void Assembler::slag(Register r1, Register r3, Register opnd) {
1783
  DCHECK(opnd != r0);
1784 1785 1786 1787 1788 1789 1790 1791 1792 1793
  rsy_form(SLAG, r1, r3, opnd, 0);
}

// Shift Left Single (64)
void Assembler::slag(Register r1, Register r3, const Operand& opnd) {
  rsy_form(SLAG, r1, r3, r0, opnd.immediate());
}

// Shift Right Single (32)
void Assembler::sra(Register r1, Register opnd) {
1794
  DCHECK(opnd != r0);
1795 1796 1797 1798 1799 1800 1801 1802 1803 1804
  rs_form(SRA, r1, r0, opnd, 0);
}

// Shift Right Single (32)
void Assembler::sra(Register r1, const Operand& opnd) {
  rs_form(SRA, r1, r0, r0, opnd.immediate());
}

// Shift Right Single (32)
void Assembler::srak(Register r1, Register r3, Register opnd) {
1805
  DCHECK(opnd != r0);
1806 1807 1808 1809 1810 1811 1812 1813 1814 1815
  rsy_form(SRAK, r1, r3, opnd, 0);
}

// Shift Right Single (32)
void Assembler::srak(Register r1, Register r3, const Operand& opnd) {
  rsy_form(SRAK, r1, r3, r0, opnd.immediate());
}

// Shift Right Single (64)
void Assembler::srag(Register r1, Register r3, Register opnd) {
1816
  DCHECK(opnd != r0);
1817 1818 1819 1820 1821 1822 1823 1824 1825
  rsy_form(SRAG, r1, r3, opnd, 0);
}

void Assembler::srag(Register r1, Register r3, const Operand& opnd) {
  rsy_form(SRAG, r1, r3, r0, opnd.immediate());
}

// Shift Right Double
void Assembler::srda(Register r1, const Operand& opnd) {
1826
  DCHECK_EQ(r1.code() % 2, 0);
1827 1828 1829 1830 1831
  rs_form(SRDA, r1, r0, r0, opnd.immediate());
}

// Shift Right Double Logical
void Assembler::srdl(Register r1, const Operand& opnd) {
1832
  DCHECK_EQ(r1.code() % 2, 0);
1833 1834 1835
  rs_form(SRDL, r1, r0, r0, opnd.immediate());
}

1836
void Assembler::call(Handle<Code> target, RelocInfo::Mode rmode) {
1837 1838
  EnsureSpace ensure_space(this);

1839
  int32_t target_index = emit_code_target(target, rmode);
1840 1841 1842
  brasl(r14, Operand(target_index));
}

1843 1844 1845 1846 1847 1848 1849 1850
void Assembler::call(CodeStub* stub) {
  EnsureSpace ensure_space(this);
  RequestHeapObject(HeapObjectRequest(stub));
  int32_t target_index =
      emit_code_target(Handle<Code>(), RelocInfo::CODE_TARGET);
  brasl(r14, Operand(target_index));
}

1851 1852 1853 1854 1855
void Assembler::jump(Handle<Code> target, RelocInfo::Mode rmode,
                     Condition cond) {
  EnsureSpace ensure_space(this);

  int32_t target_index = emit_code_target(target, rmode);
1856
  brcl(cond, Operand(target_index));
1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873
}

// 32-bit Load Multiple - short displacement (12-bits unsigned)
void Assembler::lm(Register r1, Register r2, const MemOperand& src) {
  rs_form(LM, r1, r2, src.rb(), src.offset());
}

// 32-bit Load Multiple - long displacement (20-bits signed)
void Assembler::lmy(Register r1, Register r2, const MemOperand& src) {
  rsy_form(LMY, r1, r2, src.rb(), src.offset());
}

// 64-bit Load Multiple - long displacement (20-bits signed)
void Assembler::lmg(Register r1, Register r2, const MemOperand& src) {
  rsy_form(LMG, r1, r2, src.rb(), src.offset());
}

1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888
// 32-bit Compare and Swap
void Assembler::cs(Register r1, Register r2, const MemOperand& src) {
  rs_form(CS, r1, r2, src.rb(), src.offset());
}

// 32-bit Compare and Swap
void Assembler::csy(Register r1, Register r2, const MemOperand& src) {
  rsy_form(CSY, r1, r2, src.rb(), src.offset());
}

// 64-bit Compare and Swap
void Assembler::csg(Register r1, Register r2, const MemOperand& src) {
  rsy_form(CSG, r1, r2, src.rb(), src.offset());
}

1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928
// Move integer (32)
void Assembler::mvhi(const MemOperand& opnd1, const Operand& i2) {
  sil_form(MVHI, opnd1.getBaseRegister(), opnd1.getDisplacement(), i2);
}

// Move integer (64)
void Assembler::mvghi(const MemOperand& opnd1, const Operand& i2) {
  sil_form(MVGHI, opnd1.getBaseRegister(), opnd1.getDisplacement(), i2);
}

// Insert Immediate (high high)
void Assembler::iihh(Register r1, const Operand& opnd) {
  ri_form(IIHH, r1, opnd);
}

// Insert Immediate (high low)
void Assembler::iihl(Register r1, const Operand& opnd) {
  ri_form(IIHL, r1, opnd);
}

// Insert Immediate (low high)
void Assembler::iilh(Register r1, const Operand& opnd) {
  ri_form(IILH, r1, opnd);
}

// Insert Immediate (low low)
void Assembler::iill(Register r1, const Operand& opnd) {
  ri_form(IILL, r1, opnd);
}

// GPR <-> FPR Instructions

// Floating point instructions
//
// Add Register-Storage (LB)
void Assembler::adb(DoubleRegister r1, const MemOperand& opnd) {
  rxe_form(ADB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
           opnd.offset());
}

1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940
// Add Register-Storage (LB)
void Assembler::aeb(DoubleRegister r1, const MemOperand& opnd) {
  rxe_form(AEB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
           opnd.offset());
}

// Sub Register-Storage (LB)
void Assembler::seb(DoubleRegister r1, const MemOperand& opnd) {
  rxe_form(SEB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
           opnd.offset());
}

1941 1942 1943 1944 1945 1946
// Divide Register-Storage (LB)
void Assembler::ddb(DoubleRegister r1, const MemOperand& opnd) {
  rxe_form(DDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
           opnd.offset());
}

1947 1948 1949 1950 1951 1952
// Divide Register-Storage (LB)
void Assembler::deb(DoubleRegister r1, const MemOperand& opnd) {
  rxe_form(DEB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
           opnd.offset());
}

1953 1954 1955 1956 1957 1958
// Multiply Register-Storage (LB)
void Assembler::mdb(DoubleRegister r1, const MemOperand& opnd) {
  rxe_form(MDB, Register::from_code(r1.code()), opnd.rb(), opnd.rx(),
           opnd.offset());
}

1959 1960 1961 1962 1963 1964
// Multiply Register-Storage (LB)
void Assembler::meeb(DoubleRegister r1, const MemOperand& opnd) {
  rxe_form(MEEB, Register::from_code(r1.code()), opnd.rb(), opnd.rx(),
           opnd.offset());
}

1965 1966 1967 1968 1969 1970
// Subtract Register-Storage (LB)
void Assembler::sdb(DoubleRegister r1, const MemOperand& opnd) {
  rxe_form(SDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
           opnd.offset());
}

jyan's avatar
jyan committed
1971 1972 1973 1974 1975 1976 1977 1978 1979 1980
void Assembler::ceb(DoubleRegister r1, const MemOperand& opnd) {
  rxe_form(CEB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
           opnd.offset());
}

void Assembler::cdb(DoubleRegister r1, const MemOperand& opnd) {
  rxe_form(CDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
           opnd.offset());
}

1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019
// Square Root (LB)
void Assembler::sqdb(DoubleRegister r1, const MemOperand& opnd) {
  rxe_form(SQDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
           opnd.offset());
}

// Convert to Fixed point (64<-S)
void Assembler::cgebr(Condition m, Register r1, DoubleRegister r2) {
  rrfe_form(CGEBR, m, Condition(0), r1, Register::from_code(r2.code()));
}

// Convert to Fixed point (64<-L)
void Assembler::cgdbr(Condition m, Register r1, DoubleRegister r2) {
  rrfe_form(CGDBR, m, Condition(0), r1, Register::from_code(r2.code()));
}

// Convert to Fixed point (32<-L)
void Assembler::cfdbr(Condition m, Register r1, DoubleRegister r2) {
  rrfe_form(CFDBR, m, Condition(0), r1, Register::from_code(r2.code()));
}

// Convert to Fixed Logical (64<-L)
void Assembler::clgdbr(Condition m3, Condition m4, Register r1,
                       DoubleRegister r2) {
  DCHECK_EQ(m4, Condition(0));
  rrfe_form(CLGDBR, m3, m4, r1, Register::from_code(r2.code()));
}

// Convert to Fixed Logical (64<-F32)
void Assembler::clgebr(Condition m3, Condition m4, Register r1,
                       DoubleRegister r2) {
  DCHECK_EQ(m4, Condition(0));
  rrfe_form(CLGEBR, m3, m4, r1, Register::from_code(r2.code()));
}

// Convert to Fixed Logical (32<-F64)
void Assembler::clfdbr(Condition m3, Condition m4, Register r1,
                       DoubleRegister r2) {
  DCHECK_EQ(m4, Condition(0));
2020
  rrfe_form(CLFDBR, m3, Condition(0), r1, Register::from_code(r2.code()));
2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042
}

// Convert to Fixed Logical (32<-F32)
void Assembler::clfebr(Condition m3, Condition m4, Register r1,
                       DoubleRegister r2) {
  DCHECK_EQ(m4, Condition(0));
  rrfe_form(CLFEBR, m3, Condition(0), r1, Register::from_code(r2.code()));
}

// Convert from Fixed Logical (L<-64)
void Assembler::celgbr(Condition m3, Condition m4, DoubleRegister r1,
                       Register r2) {
  DCHECK_EQ(m3, Condition(0));
  DCHECK_EQ(m4, Condition(0));
  rrfe_form(CELGBR, Condition(0), Condition(0), Register::from_code(r1.code()),
            r2);
}

// Convert from Fixed Logical (F32<-32)
void Assembler::celfbr(Condition m3, Condition m4, DoubleRegister r1,
                       Register r2) {
  DCHECK_EQ(m4, Condition(0));
2043
  rrfe_form(CELFBR, m3, Condition(0), Register::from_code(r1.code()), r2);
2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062
}

// Convert from Fixed Logical (L<-64)
void Assembler::cdlgbr(Condition m3, Condition m4, DoubleRegister r1,
                       Register r2) {
  DCHECK_EQ(m3, Condition(0));
  DCHECK_EQ(m4, Condition(0));
  rrfe_form(CDLGBR, Condition(0), Condition(0), Register::from_code(r1.code()),
            r2);
}

// Convert from Fixed Logical (L<-32)
void Assembler::cdlfbr(Condition m3, Condition m4, DoubleRegister r1,
                       Register r2) {
  DCHECK_EQ(m4, Condition(0));
  rrfe_form(CDLFBR, m3, Condition(0), Register::from_code(r1.code()), r2);
}

// Convert from Fixed point (S<-32)
2063 2064
void Assembler::cefbr(Condition m3, DoubleRegister r1, Register r2) {
  rrfe_form(CEFBR, m3, Condition(0), Register::from_code(r1.code()), r2);
2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092
}

// Convert to Fixed point (32<-S)
void Assembler::cfebr(Condition m3, Register r1, DoubleRegister r2) {
  rrfe_form(CFEBR, m3, Condition(0), r1, Register::from_code(r2.code()));
}

// Load (L <- S)
void Assembler::ldeb(DoubleRegister d1, const MemOperand& opnd) {
  rxe_form(LDEB, Register::from_code(d1.code()), opnd.rx(), opnd.rb(),
           opnd.offset());
}

// Load FP Integer
void Assembler::fiebra(DoubleRegister d1, DoubleRegister d2, FIDBRA_MASK3 m3) {
  rrf2_form(FIEBRA << 16 | m3 * B12 | d1.code() * B4 | d2.code());
}

// Load FP Integer
void Assembler::fidbra(DoubleRegister d1, DoubleRegister d2, FIDBRA_MASK3 m3) {
  rrf2_form(FIDBRA << 16 | m3 * B12 | d1.code() * B4 | d2.code());
}

// end of S390instructions

bool Assembler::IsNop(SixByteInstr instr, int type) {
  DCHECK((0 == type) || (DEBUG_BREAK_NOP == type));
  if (DEBUG_BREAK_NOP == type) {
2093
    return ((instr & 0xFFFFFFFF) == 0xA53B0000);  // oill r3, 0
2094
  }
2095
  return ((instr & 0xFFFF) == 0x1800);  // lr r0,r0
2096 2097
}

2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112
// dummy instruction reserved for special use.
void Assembler::dumy(int r1, int x2, int b2, int d2) {
#if defined(USE_SIMULATOR)
  int op = 0xE353;
  uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
                  (static_cast<uint64_t>(r1) & 0xF) * B36 |
                  (static_cast<uint64_t>(x2) & 0xF) * B32 |
                  (static_cast<uint64_t>(b2) & 0xF) * B28 |
                  (static_cast<uint64_t>(d2 & 0x0FFF)) * B16 |
                  (static_cast<uint64_t>(d2 & 0x0FF000)) >> 4 |
                  (static_cast<uint64_t>(op & 0x00FF));
  emit6bytes(code);
#endif
}

2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128
void Assembler::GrowBuffer(int needed) {
  if (!own_buffer_) FATAL("external code buffer is too small");

  // Compute new buffer size.
  CodeDesc desc;  // the new buffer
  if (buffer_size_ < 4 * KB) {
    desc.buffer_size = 4 * KB;
  } else if (buffer_size_ < 1 * MB) {
    desc.buffer_size = 2 * buffer_size_;
  } else {
    desc.buffer_size = buffer_size_ + 1 * MB;
  }
  int space = buffer_space() + (desc.buffer_size - buffer_size_);
  if (space < needed) {
    desc.buffer_size += needed - space;
  }
2129 2130 2131

  // Some internal data structures overflow for very large buffers,
  // they must ensure that kMaximalBufferSize is not too large.
2132
  if (desc.buffer_size > kMaximalBufferSize) {
2133 2134
    V8::FatalProcessOutOfMemory("Assembler::GrowBuffer");
  }
2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214

  // Set up new buffer.
  desc.buffer = NewArray<byte>(desc.buffer_size);
  desc.origin = this;

  desc.instr_size = pc_offset();
  desc.reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();

  // Copy the data.
  intptr_t pc_delta = desc.buffer - buffer_;
  intptr_t rc_delta =
      (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_);
  memmove(desc.buffer, buffer_, desc.instr_size);
  memmove(reloc_info_writer.pos() + rc_delta, reloc_info_writer.pos(),
          desc.reloc_size);

  // Switch buffers.
  DeleteArray(buffer_);
  buffer_ = desc.buffer;
  buffer_size_ = desc.buffer_size;
  pc_ += pc_delta;
  reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
                               reloc_info_writer.last_pc() + pc_delta);

  // None of our relocation types are pc relative pointing outside the code
  // buffer nor pc absolute pointing inside the code buffer, so there is no need
  // to relocate any emitted relocation entries.
}

void Assembler::db(uint8_t data) {
  CheckBuffer();
  *reinterpret_cast<uint8_t*>(pc_) = data;
  pc_ += sizeof(uint8_t);
}

void Assembler::dd(uint32_t data) {
  CheckBuffer();
  *reinterpret_cast<uint32_t*>(pc_) = data;
  pc_ += sizeof(uint32_t);
}

void Assembler::dq(uint64_t value) {
  CheckBuffer();
  *reinterpret_cast<uint64_t*>(pc_) = value;
  pc_ += sizeof(uint64_t);
}

void Assembler::dp(uintptr_t data) {
  CheckBuffer();
  *reinterpret_cast<uintptr_t*>(pc_) = data;
  pc_ += sizeof(uintptr_t);
}

void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
  if (RelocInfo::IsNone(rmode) ||
      // Don't record external references unless the heap will be serialized.
      (rmode == RelocInfo::EXTERNAL_REFERENCE && !serializer_enabled() &&
       !emit_debug_code())) {
    return;
  }
  DeferredRelocInfo rinfo(pc_offset(), rmode, data);
  relocations_.push_back(rinfo);
}

void Assembler::emit_label_addr(Label* label) {
  CheckBuffer();
  RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE);
  int position = link(label);
  DCHECK(label->is_bound());
  // Keep internal references relative until EmitRelocations.
  dp(position);
}

void Assembler::EmitRelocations() {
  EnsureSpaceFor(relocations_.size() * kMaxRelocSize);

  for (std::vector<DeferredRelocInfo>::iterator it = relocations_.begin();
       it != relocations_.end(); it++) {
    RelocInfo::Mode rmode = it->rmode();
    Address pc = buffer_ + it->position();
2215
    RelocInfo rinfo(pc, rmode, it->data(), nullptr);
2216 2217 2218 2219 2220 2221 2222 2223

    // Fix up internal references now that they are guaranteed to be bound.
    if (RelocInfo::IsInternalReference(rmode)) {
      // Jump table entry
      intptr_t pos = reinterpret_cast<intptr_t>(Memory::Address_at(pc));
      Memory::Address_at(pc) = buffer_ + pos;
    } else if (RelocInfo::IsInternalReferenceEncoded(rmode)) {
      // mov sequence
2224
      intptr_t pos = reinterpret_cast<intptr_t>(target_address_at(pc, nullptr));
2225
      set_target_address_at(pc, nullptr, buffer_ + pos, SKIP_ICACHE_FLUSH);
2226 2227 2228 2229 2230 2231 2232 2233 2234
    }

    reloc_info_writer.Write(&rinfo);
  }
}

}  // namespace internal
}  // namespace v8
#endif  // V8_TARGET_ARCH_S390