S390: Impl Left/Right Logical/Arith Shift Pair

Implement Left/Right Logical/Arithmetic Shift Pair operations for s390

R=joransiu@ca.ibm.com, mbrandy@us.ibm.com, michael_dawson@ca.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1835973003

Cr-Commit-Position: refs/heads/master@{#35087}

src/s390/assembler-s390.cc

@@ -2336,12 +2336,30 @@ void Assembler::sllg(Register r1, Register r3, const Operand& opnd) {
   rsy_form(SLLG, r1, r3, r0, opnd.immediate());
 }
 
+// Shift Left Double Logical (64)
+void Assembler::sldl(Register r1, Register b2, const Operand& opnd) {
+  DCHECK(r1.code() % 2 == 0);
+  rs_form(SLDL, r1, r0, b2, opnd.immediate());
+}
+
 // Shift Right Single Logical (32)
 void Assembler::srl(Register r1, Register opnd) {
   DCHECK(!opnd.is(r0));
   rs_form(SRL, r1, r0, opnd, 0);
 }
 
+// Shift Right Double Arith (64)
+void Assembler::srda(Register r1, Register b2, const Operand& opnd) {
+  DCHECK(r1.code() % 2 == 0);
+  rs_form(SRDA, r1, r0, b2, opnd.immediate());
+}
+
+// Shift Right Double Logical (64)
+void Assembler::srdl(Register r1, Register b2, const Operand& opnd) {
+  DCHECK(r1.code() % 2 == 0);
+  rs_form(SRDL, r1, r0, b2, opnd.immediate());
+}
+
 // Shift Right Single Logical (32)
 void Assembler::srl(Register r1, const Operand& opnd) {
   rs_form(SRL, r1, r0, r0, opnd.immediate());

src/s390/assembler-s390.h

@@ -951,6 +951,9 @@ class Assembler : public AssemblerBase {
   void srdl(Register r1, const Operand& opnd);
   void slag(Register r1, Register r3, const Operand& opnd);
   void slag(Register r1, Register r3, const Register opnd);
+  void sldl(Register r1, Register b2, const Operand& opnd);
+  void srdl(Register r1, Register b2, const Operand& opnd);
+  void srda(Register r1, Register b2, const Operand& opnd);
 
   // Rotate and Insert Selected Bits
   void risbg(Register dst, Register src, const Operand& startBit,

src/s390/disasm-s390.cc

@@ -643,6 +643,9 @@ bool Decoder::DecodeFourByte(Instruction* instr) {
     case SRA:
       Format(instr, "sra\t'r1,'d1('r3)");
       break;
+    case SLDL:
+      Format(instr, "sldl\t'r1,'d1('r3)");
+      break;
     case AGR:
       Format(instr, "agr\t'r5,'r6");
       break;
@@ -968,10 +971,10 @@ bool Decoder::DecodeFourByte(Instruction* instr) {
       Format(instr, "sth\t'r1,'d1('r2d,'r3)");
       break;
     case SRDA:
-      Format(instr, "srda\t'r1,'d1");
+      Format(instr, "srda\t'r1,'d1('r3)");
       break;
     case SRDL:
-      Format(instr, "srdl\t'r1,'d1");
+      Format(instr, "srdl\t'r1,'d1('r3)");
       break;
     case MADBR:
       Format(instr, "madbr\t'f3,'f5,'f6");

src/s390/macro-assembler-s390.cc

@@ -892,51 +892,61 @@ void MacroAssembler::ConvertDoubleToUnsignedInt64(
 void MacroAssembler::ShiftLeftPair(Register dst_low, Register dst_high,
                                    Register src_low, Register src_high,
                                    Register scratch, Register shift) {
-  DCHECK(!AreAliased(dst_low, src_high, shift));
-  DCHECK(!AreAliased(dst_high, src_low, shift));
-  UNIMPLEMENTED();
+  LoadRR(r0, src_high);
+  LoadRR(r1, src_low);
+  sldl(r0, shift, Operand::Zero());
+  LoadRR(dst_high, r0);
+  LoadRR(dst_low, r1);
 }
 
 void MacroAssembler::ShiftLeftPair(Register dst_low, Register dst_high,
                                    Register src_low, Register src_high,
                                    uint32_t shift) {
-  DCHECK(!AreAliased(dst_low, src_high));
-  DCHECK(!AreAliased(dst_high, src_low));
-  UNIMPLEMENTED();
-  Label less_than_32;
-  Label done;
+  LoadRR(r0, src_high);
+  LoadRR(r1, src_low);
+  sldl(r0, r0, Operand(shift));
+  LoadRR(dst_high, r0);
+  LoadRR(dst_low, r1);
 }
 
 void MacroAssembler::ShiftRightPair(Register dst_low, Register dst_high,
                                     Register src_low, Register src_high,
                                     Register scratch, Register shift) {
-  DCHECK(!AreAliased(dst_low, src_high, shift));
-  DCHECK(!AreAliased(dst_high, src_low, shift));
-  UNIMPLEMENTED();
+  LoadRR(r0, src_high);
+  LoadRR(r1, src_low);
+  srdl(r0, shift, Operand::Zero());
+  LoadRR(dst_high, r0);
+  LoadRR(dst_low, r1);
 }
 
 void MacroAssembler::ShiftRightPair(Register dst_low, Register dst_high,
                                     Register src_low, Register src_high,
                                     uint32_t shift) {
-  DCHECK(!AreAliased(dst_low, src_high));
-  DCHECK(!AreAliased(dst_high, src_low));
-  UNIMPLEMENTED();
+  LoadRR(r0, src_high);
+  LoadRR(r1, src_low);
+  srdl(r0, r0, Operand(shift));
+  LoadRR(dst_high, r0);
+  LoadRR(dst_low, r1);
 }
 
 void MacroAssembler::ShiftRightArithPair(Register dst_low, Register dst_high,
                                          Register src_low, Register src_high,
                                          Register scratch, Register shift) {
-  DCHECK(!AreAliased(dst_low, src_high, shift));
-  DCHECK(!AreAliased(dst_high, src_low, shift));
-  UNIMPLEMENTED();
+  LoadRR(r0, src_high);
+  LoadRR(r1, src_low);
+  srda(r0, shift, Operand::Zero());
+  LoadRR(dst_high, r0);
+  LoadRR(dst_low, r1);
 }
 
 void MacroAssembler::ShiftRightArithPair(Register dst_low, Register dst_high,
                                          Register src_low, Register src_high,
                                          uint32_t shift) {
-  DCHECK(!AreAliased(dst_low, src_high));
-  DCHECK(!AreAliased(dst_high, src_low));
-  UNIMPLEMENTED();
+  LoadRR(r0, src_high);
+  LoadRR(r1, src_low);
+  srdl(r0, r0, Operand(shift));
+  LoadRR(dst_high, r0);
+  LoadRR(dst_low, r1);
 }
 #endif
 

src/s390/simulator-s390.cc

@@ -2191,6 +2191,25 @@ bool Simulator::DecodeFourByte(Instruction* instr) {
       set_low_register(r1, alu_out);
       break;
     }
+    case SLDL: {
+      RSInstruction* rsInstr = reinterpret_cast<RSInstruction*>(instr);
+      int r1 = rsInstr->R1Value();
+      int b2 = rsInstr->B2Value();
+      intptr_t d2 = rsInstr->D2Value();
+      // only takes rightmost 6bits
+      int64_t b2_val = b2 == 0 ? 0 : get_register(b2);
+      int shiftBits = (b2_val + d2) & 0x3F;
+
+      DCHECK(r1 % 2 == 0);
+      uint32_t r1_val = get_low_register<uint32_t>(r1);
+      uint32_t r1_next_val = get_low_register<uint32_t>(r1 + 1);
+      uint64_t alu_out = (static_cast<uint64_t>(r1_val) << 32) |
+                         (static_cast<uint64_t>(r1_next_val));
+      alu_out <<= shiftBits;
+      set_low_register(r1 + 1, static_cast<uint32_t>(alu_out));
+      set_low_register(r1, static_cast<uint32_t>(alu_out >> 32));
+      break;
+    }
     case SLA:
     case SRA: {
       RSInstruction* rsInstr = reinterpret_cast<RSInstruction*>(instr);